JP2006339597A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, which comprises a full silicide gate of which short-circuit is prevented between a gate electrode and a source-drain diffusion layer. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate; a pair of source-drain diffusion layers formed, with a specified interval, to regulate a channel region on the surface layer of the semiconductor substrate; silicide layers formed on the surface layers of the pair of source-drain diffusion layers; a gate insulating film formed in the region sandwiched between the pair of source-drain diffusion layers on the semiconductor substrate; a gate electrode which is so formed, on the gate insulating film, as to contact it, with a polysilicon being made into silicide; and an insulating side wall which is provided on the side surface of the gate electrode and the gate insulating film so that it is protruded above the upper surface of the gate electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using a fully silicided gate electrode in which the entire gate electrode is silicided and a manufacturing method thereof.

  In SoC transistors of 45 nm generation and later, application of a high dielectric constant gate insulating film (High-k) and a metal gate electrode is being studied in order to achieve both low power consumption during standby and high current drive capability. Several techniques have been proposed as techniques to which these are applied. For example, after forming a dummy gate insulating film and a dummy gate electrode, implanting impurities in a polycrystalline silicon film in a self-aligned manner to form a source / drain diffusion layer, removing the dummy gate insulating film and the dummy gate electrode, A method of forming a high dielectric constant gate insulating film and a metal gate electrode has been proposed.

  Several methods for forming the metal gate electrode have been proposed. One candidate is a fully silicided gate (hereinafter referred to as a FUSI gate). The FUSI gate is formed by siliciding the gate electrode formed of polysilicon as in the conventional CMOS process. Conventionally, only the upper part of the gate electrode is silicidized, whereas in FUSI, the gate electrode is The difference is that the whole is silicided.

  Compared with the method of forming a metal gate electrode by a damascene process, FUSI has a great advantage in process construction because the know-how of the conventional CMOS process becomes useful.

  By the way, FUSI has the above-mentioned advantages, but also has a specific problem. One of them is the problem of silicide film thickness. In the conventional CMOS process, after forming the source / drain diffusion layer by ion implantation, the upper part of the gate and the source / drain diffusion layer are simultaneously silicided in a self-aligned manner.

  Generally, there is a problem in increasing the silicide film thickness of the source / drain diffusion layer. That is, the silicide on the minute spike may grow abnormally from the silicide layer, and if this penetrates the P / N junction between the source / drain diffusion layer and the substrate, junction leakage increases, resulting in a circuit failure. Cause malfunctions and increase in power consumption. For this reason, it is necessary to form the source / drain diffusion layer to a depth that can sufficiently cover the silicide layer. When the silicide layer becomes thicker, the source / drain diffusion layer must be deepened accordingly. .

  However, if the depth of the source / drain diffusion layer is formed deeply, the junction capacitance increases, leading to a reduction in circuit speed. Therefore, it is not preferable to increase the thickness of the silicide layer. Therefore, in order to simultaneously silicide the gate electrode and the source / drain diffusion layer by the side-side process without increasing the thickness of the silicide layer of the source / drain diffusion layer, the polysilicon film thickness of the gate electrode is finished to FUSI. It is necessary to make it thinner.

  In this case, since the level difference between the gate electrode and the source / drain diffusion layer is reduced, when the silicide of the source / drain diffusion layer abnormally grows, a short (between the source / drain diffusion layer and the gate electrode ( In the following, this will be referred to as “silicic scooping”). In order to avoid this, it is necessary to secure a sufficient level difference between the gate electrode and the source / drain diffusion layer, while keeping the silicide of the source / drain diffusion layer thin, and the gate electrode is formed of thick polysilicon. In addition to the silicide of the source / drain diffusion layer, a process for siliciding a thick gate electrode is required.

  However, when siliciding the gate electrode and the source / drain diffusion layers separately, in addition to the increase in manufacturing cost associated with the increase in the number of processes, the construction of a process flow when using non-heat-resistant silicide such as NiSi is used. It becomes difficult.

  As described above, the conventional technique has a problem in that it is difficult to form the silicide of the source / drain diffusion layer and the FUSI gate which do not creep up by the salicide process.

  The present invention has been made in view of the above, and an object thereof is to obtain a semiconductor device having a full silicide gate in which a short circuit between a gate electrode and a source / drain diffusion layer is prevented, and a method for manufacturing the same. To do.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a semiconductor substrate and a pair of source / drain formed at a predetermined interval so as to define a channel region in a surface layer of the semiconductor substrate. A diffusion layer; a silicide layer formed on a surface layer of the pair of source / drain diffusion layers; a gate insulating film formed in a region sandwiched between the pair of source / drain diffusion layers on the semiconductor substrate; and gate insulation A gate electrode formed on the film so as to be in contact with the gate insulating film and formed by siliciding polysilicon, and an insulating sidewall provided on the side surface of the gate insulating film and the gate electrode and protruding upward from the upper surface of the gate electrode And.

  According to the present invention, the gate electrode and the source in the semiconductor device having a full silicide gate are provided by providing the insulating sidewall provided on the side surfaces of the gate insulating film and the gate electrode and protruding upward from the upper surface of the gate electrode. -It is possible to obtain a semiconductor device in which a short circuit with the drain diffusion layer is reliably prevented.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view schematically showing the structure of a transistor which is a semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 1, in the semiconductor device according to the present embodiment, element isolation 2 for isolating each element and a region between the element isolations 2 are formed on the surface layer of the semiconductor substrate 1. Source / drain diffusion layers 10 are formed at a distance from each other so as to define a channel region in the active region.

  Between the source / drain diffusion layers 10, a source / drain extension (SDE) layer 7 is formed adjacent to the source / drain diffusion layers 10. A silicide layer 10 a in which a metal is silicided is formed at a surface layer portion of the source / drain diffusion layer 10 at a distance from each other.

  Further, on the source / drain diffusion layer 10 on the semiconductor substrate 1 and on the region sandwiched between the source / drain diffusion layers 10, as shown in FIG. A gate structure having a stacked structure in which a gate insulating film 4 made of high-k) and a full silicide gate electrode (FUSI gate electrode) 5 in which the entire polysilicon electrode is silicided is stacked in this order.

  Further, sidewall spacers 9 made of an insulating film such as a nitride film are formed on the outer side of the gate structure, that is, on the side surfaces. Here, in the semiconductor device according to the present embodiment, the height of the sidewall spacer 9 is provided higher than the height of the gate electrode. That is, in this semiconductor device, the side wall spacer 9 has a shape protruding above the gate electrode.

  An interlayer insulating film 13 covering the gate structure and the element isolation 2 is formed on the semiconductor substrate 1. The interlayer insulating film 13 is formed with a contact 15 made of a conductive material and reaching the silicide layer 10 a from the upper surface of the interlayer insulating film 13 and conducting to the source / drain diffusion layer 10, and further on the interlayer insulating film 13. A wiring layer 16 is formed which is electrically connected to the contact 15.

  In the semiconductor device according to the present embodiment configured as described above, in the semiconductor device having a full silicide gate, the upper surface of full silicide gate electrode 5 is provided on the side surfaces of gate insulating film 4 and full silicide gate electrode 5. By providing the side wall spacer 9 that protrudes further upward, a transistor in which a short circuit between the full silicide gate electrode 5 and the source / drain diffusion layer 10 is reliably prevented is realized.

  The semiconductor device according to the present embodiment configured as described above includes a full silicide gate electrode 5 (metal gate electrode) obtained by siliciding the entire polysilicon electrode as a gate electrode, and a high dielectric constant as a gate insulating film. Since the gate insulating film 4 made of the gate insulating film (High-k) is provided, a transistor that has excellent electrical characteristics and reliability and achieves both low power consumption during standby and high current driving capability is realized.

  Next, a method for manufacturing the semiconductor device according to the present embodiment shown in FIG. 1 will be described with reference to the drawings. 2 to 14 are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the present embodiment. First, a semiconductor substrate 1 is prepared, and element isolation 2 for isolating each semiconductor element is performed on the semiconductor substrate 1 as shown in FIG. 2 by a known method such as an STI (shallow trench isolation) process. Selectively formed.

  Then, ion implantation of impurities such as well forming impurities and threshold adjusting impurities is performed in the regions delimited by the element isolation 2 to form retrograde wells 3 as shown in FIG.

Next, as shown in FIG. 3, a high dielectric constant insulating film 4 a to be a gate insulating film is deposited on the semiconductor substrate 1. As the high dielectric constant insulating film 4a, for example, a film of HfO ₂ , HfSiON, HfAlO, Al ₂ O ₃ or the like is deposited. Further, such a high dielectric constant insulating film 4a is deposited with a film thickness of about 1 nm to 5 nm, for example.

  Then, as shown in FIG. 3, a polysilicon film 5a to be a gate electrode is deposited on the high dielectric constant insulating film 4a. The polysilicon film 5a is formed so thin as to become FUSI in the later salicide process, and is deposited with a film thickness of, for example, about 20 nm to 50 nm.

  Further, as shown in FIG. 3, for example, a tetraethylorthosilicate (TEOS) oxide film 6a is deposited on the polysilicon film 5a as a mask layer in a subsequent gate electrode etching step. The height of the spacer separating the later gate structure and the source / drain diffusion layer can be adjusted by the thickness of the TEOS oxide film 6a deposited at this time. Such a TEOS oxide film 6a is deposited with a film thickness of about 20 nm to 50 nm as an example.

  Then, after patterning the TEOS oxide film 6a by a photoengraving process, anisotropic etching is performed on the polysilicon film 5a and the high dielectric constant insulating film 4a using the patterned TEOS oxide film 6 as a mask, so that FIG. As shown, a gate electrode 5b before silicide and a gate insulating film (high dielectric constant gate insulating film (High-k)) 4 are formed. The TEOS oxide film 6 is used as a dummy layer for forming the sidewall spacer 9 in the following step of forming the sidewall spacer 9.

  Next, in accordance with a normal CMOS formation process, ion implantation is performed on a predetermined region of the semiconductor substrate 1 to form a source / drain extension layer 7 as shown in FIG. The implantation energy and dose for forming the source / drain extension layer 7 are appropriately determined depending on the depth and resistance value of the source / drain extension layer 7 required in each generation.

After the source / drain extension layer 7 is formed, an insulating film 8 such as silicon nitride (Si ₃ N ₄ ) is deposited on the semiconductor substrate 1 and the TEOS oxide film 6 as shown in FIG. The film thickness of the insulating film 8 is, for example, about 10 nm to 50 nm. Then, by performing anisotropic etching of the insulating film 8, sidewall spacers 9 made of an insulating film are formed on the outer peripheral portions of the gate electrode 5b, the gate insulating film 4 and the TEOS oxide film 6 before silicidation as shown in FIG. Is formed.

  Next, ion implantation is performed in accordance with a normal CMOS formation process, and activation annealing is performed, thereby forming the source / drain diffusion layer 10 as shown in FIG. Thereafter, as shown in FIG. 7, the TEOS oxide film 6 on the gate electrode 5b before silicidation is removed to expose the surface of the gate electrode 5b before silicidation. The TEOS oxide film 6 can be removed by, for example, isotropic wet etching using hydrofluoric acid or anisotropic dry etching.

  Here, when the TEOS oxide film 6 is removed, the element isolation 2 is also etched at the same time. Therefore, when the etching amount of the TEOS oxide film 6 is large (for example, 50 nm or more), the element isolation 2 is covered with the photoresist 11 by photolithography as shown in FIG. 8, and then the TEOS oxide film 6 is etched. . Thus, the TEOS oxide film 6 can be etched without etching the element isolation 2.

  After exposing the surface of the gate electrode 5b before silicidation, a metal layer 12 such as nickel (Ni), cobalt (Co), titanium (Ti) or the like is formed by sputtering or CVD (Chemical Vapor Deposition) as shown in FIG. To deposit. When the sputtering method is used for the volume of the metal layer 12, the film thickness of the metal layer 12 deposited on the upper surface of the gate electrode 5b before silicide is reduced when the height of the sidewall spacer 9 is increased. When the CVD method is used, it is possible to deposit a metal layer 12 having a uniform thickness on the source / drain diffusion layer 10.

  Thereafter, by performing a normal silicide process such as annealing at a predetermined temperature, the gate electrode 5b and the source / drain diffusion layer 10 before silicide are silicided. Here, silicidation is performed so that the entire gate electrode 5b before silicidation is silicided. As a result, a silicide layer 10a is formed on the surface layer of the source / drain diffusion layer 10, and a full silicide gate electrode (FUSI gate electrode) 5 in which the entire gate electrode 5b before silicide is silicided is formed.

  Then, the unreacted metal layer 12 is removed, and annealing is performed at a predetermined temperature to reduce the resistance of the silicide layer 10a and the FUSI gate electrode, thereby forming a structure as shown in FIG.

  Thereafter, an oxide film is deposited as an interlayer insulating film 13 as shown in FIG. 11, and a contact hole 14 reaching from the surface of the interlayer insulating film 13 to the silicide layer 10a is formed as shown in FIG. At this time, a contact hole to the gate electrode 5 is also formed in a region outside the screen. Then, the contact hole 14 is filled with a material containing at least a conductive material to form a contact 15 that is electrically connected to the silicide layer 10a (source / drain diffusion layer 10) as shown in FIG. Furthermore, as shown in FIG. 14, the semiconductor device according to the present embodiment shown in FIG. 1 can be manufactured by forming the wiring layer 16 that is electrically connected to the contact 15 on the interlayer insulating film 13.

  In the method of manufacturing a semiconductor device as described above, a full silicide gate electrode 5 (metal gate electrode) in which the entire polysilicon electrode is silicided is formed as a gate electrode, and a high dielectric constant gate insulating film (High Since the gate insulating film 4 made of -k) is formed, it is possible to manufacture a transistor that has excellent electrical characteristics and reliability and achieves both low power consumption during standby and high current drive capability.

  Further, in the manufacturing method of the semiconductor device as described above, the sidewall spacers 9 protruding above the upper surface of the full silicide gate electrode 5 are formed on the side surfaces of the gate insulating film 4 and the full silicide gate electrode 5. A transistor in which a short circuit between the full silicide gate electrode 5 and the source / drain diffusion layer 10 is reliably prevented can be manufactured.

  In the method for manufacturing a semiconductor device as described above, since the gate electrode and the source / drain diffusion layer can be silicided simultaneously, the gate electrode and the source / drain diffusion layer are separately silicided. Thus, there is no increase in manufacturing cost due to an increase in the number of processes, and the construction of a process flow is easy.

Embodiment 2. FIG.
In the second embodiment, a modified example of the semiconductor device according to the first embodiment will be described. FIG. 15 is a cross-sectional view schematically showing a structure of a transistor which is a semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment described above in that the upper portion of the sidewall spacer is flattened. That is, in the semiconductor device according to the present embodiment as shown in FIG. 15, in the surface layer of the semiconductor substrate 1, the element isolation 2 for isolating each element, and the region between the element isolation 2 and the transistor element A source / drain diffusion layer 10 is formed at a distance from each other so as to define a channel region in the active region in which is formed.

  Between the source / drain diffusion layers 10, a source / drain extension (SDE) layer 7 is formed adjacent to the source / drain diffusion layers 10. A silicide layer 10 a in which a metal is silicided is formed at a surface layer portion of the source / drain diffusion layer 10 at a distance from each other.

  Further, on the source / drain diffusion layer 10 on the semiconductor substrate 1 and on the region sandwiched between the source / drain diffusion layers 10, as shown in FIG. A gate structure having a stacked structure in which a gate insulating film 4 made of high-k) and a full silicide gate electrode (FUSI gate electrode) 5 in which the entire polysilicon electrode is silicided is stacked in this order.

  Further, sidewall spacers 9a made of an insulating film such as a nitride film are formed on the outer side, that is, the side surfaces of the gate structure. Here, in the semiconductor device according to the present embodiment, the height of the sidewall spacer 9a is higher than the height of the gate electrode. The upper portion of the sidewall spacer 9a is flattened.

  An interlayer insulating film 13 covering the gate structure and the element isolation 2 is formed on the semiconductor substrate 1. The interlayer insulating film 13 is formed with a contact 15 made of a conductive material and reaching the silicide layer 10 a from the upper surface of the interlayer insulating film 13 and conducting to the source / drain diffusion layer 10, and further on the interlayer insulating film 13. A wiring layer 16 is formed which is electrically connected to the contact 15. Note that members similar to those in the first embodiment are denoted by the same reference numerals as above.

  In the semiconductor device according to the present embodiment configured as described above, in the semiconductor device having a full silicide gate, the upper surface of full silicide gate electrode 5 is provided on the side surfaces of gate insulating film 4 and full silicide gate electrode 5. By providing the side wall spacer 9 that protrudes further upward, a transistor in which a short circuit between the full silicide gate electrode 5 and the source / drain diffusion layer 10 is reliably prevented is realized.

  In addition, the semiconductor device according to the present embodiment configured as described above includes a full silicide gate electrode 5 (metal gate electrode) obtained by siliciding the entire polysilicon electrode as a gate electrode, and a high gate insulating film. Since the gate insulating film 4 made of a dielectric constant gate insulating film (High-k) is provided, a transistor that is excellent in electrical characteristics and reliability and has both reduced power consumption during standby and high current driving capability is realized.

  Furthermore, even if a short circuit occurs between the full silicide gate electrode 5 and the source / drain diffusion layer 10 via the surface of the sidewall spacer 9 in the structure of the first embodiment, the upper portion of the sidewall spacer 9 It is possible to recover from the short-circuit state by scraping and forming the transistor structure according to this embodiment.

  Next, a method for manufacturing the semiconductor device according to the present embodiment shown in FIG. 15 will be described with reference to the drawings. To manufacture the semiconductor device according to the present embodiment, first, the structure shown in FIG. 10 is formed according to the manufacturing method described in the first embodiment (corresponding to FIGS. 2 to 10).

  Next, an interlayer insulating film 21 is deposited as shown in FIG. Then, the interlayer insulating film 21 is polished by, for example, CMP (Chemical Mechanical Polish), and the upper portion of the sidewall spacer 9 is planarized. The interlayer insulating film 21 is polished until the distance L from the upper surface of the full silicide gate electrode 5 to the flat surface of the sidewall spacer 9 becomes a predetermined distance as shown in FIG. As an example, the interlayer insulating film 21 is polished until the distance L from the upper surface 5c of the full silicide gate electrode 5 to the flat surface 9b of the sidewall spacer 9 becomes about 0 to 50 nm. Thereby, the side wall spacer 9a whose upper part is flattened can be formed.

  Thereafter, an interlayer insulating film 13 is deposited in the same manner as the manufacturing method described in the first embodiment, and a contact hole 14 reaching from the surface of the interlayer insulating film 13 to the silicide layer 10a is formed. Then, the contact hole 14 is filled with a material containing at least a conductive material to form a contact 15 that is electrically connected to the silicide layer 10a (source / drain diffusion layer 10). Further, by forming a wiring layer 16 that is electrically connected to the contact 15 on the interlayer insulating film 13, the semiconductor device according to the present embodiment shown in FIG. 15 can be manufactured.

  In the method of manufacturing a semiconductor device as described above, a full silicide gate electrode 5 (metal gate electrode) in which the entire polysilicon electrode is silicided is formed as a gate electrode, and a high dielectric constant gate insulating film (High Since the gate insulating film 4 made of -k) is formed, it is possible to manufacture a transistor that has excellent electrical characteristics and reliability and achieves both low power consumption during standby and high current drive capability.

  Further, in the manufacturing method of the semiconductor device as described above, the sidewall spacers 9 protruding above the upper surface of the full silicide gate electrode 5 are formed on the side surfaces of the gate insulating film 4 and the full silicide gate electrode 5. A transistor in which a short circuit between the full silicide gate electrode 5 and the source / drain diffusion layer 10 is reliably prevented can be manufactured.

  Further, in the method of manufacturing a semiconductor device as described above, the upper surface of the sidewall spacer 9 is scraped and flattened, so that the surface of the sidewall spacer 9 is formed when the structure of Embodiment 1 as shown in FIG. 10 is formed. Even when a short-circuit occurs between the full silicide gate electrode 5 and the source / drain diffusion layer 10 via the top, it is possible to recover from the short-circuit state.

Embodiment 3 FIG.
In the third embodiment, a modified example of the semiconductor device according to the second embodiment described above will be described. FIG. 18 is a cross-sectional view schematically showing a structure of a transistor which is a semiconductor device according to the third embodiment of the present invention. The semiconductor device according to the present embodiment differs from the semiconductor device according to the second embodiment described above in that a silicon nitride film deposition portion 31 is provided in a region other than the transistor circuit element portion. That is, in the semiconductor device according to the present embodiment as shown in FIG. 18, in the surface layer of the semiconductor substrate 1, element isolation 2 for isolating each element, and a region between the element isolation 2 and transistor elements A source / drain diffusion layer 10 is formed at a distance from each other so as to define a channel region in the active region in which is formed.

  Between the source / drain diffusion layers 10, a source / drain extension (SDE) layer 7 is formed adjacent to the source / drain diffusion layers 10. A silicide layer 10 a in which a metal is silicided is formed at a surface layer portion of the source / drain diffusion layer 10 at a distance from each other.

  Further, on the source / drain diffusion layer 10 on the semiconductor substrate 1 and on the region sandwiched between the source / drain diffusion layers 10, as shown in FIG. A gate structure having a stacked structure in which a gate insulating film 4 made of high-k) and a full silicide gate electrode (FUSI gate electrode) 5 in which the entire polysilicon electrode is silicided is stacked in this order.

  Further, sidewall spacers 9a made of an insulating film such as a nitride film are formed on the outer side, that is, the side surfaces of the gate structure. Here, in the semiconductor device according to the present embodiment, the height of the sidewall spacer 9a is higher than the height of the gate electrode. The upper portion of the sidewall spacer 9a is flattened.

  An interlayer insulating film 13 covering the gate structure and the element isolation 2 is formed on the semiconductor substrate 1. The interlayer insulating film 13 is formed with a contact 15 made of a conductive material and reaching the silicide layer 10 a from the upper surface of the interlayer insulating film 13 and conducting to the source / drain diffusion layer 10, and further on the interlayer insulating film 13. A wiring layer 16 is formed which is electrically connected to the contact 15.

  A silicon nitride film deposition portion 31 is provided in a region other than the transistor circuit element portion on the semiconductor substrate 1. Note that members similar to those in the first embodiment are denoted by the same reference numerals as above.

  In the semiconductor device according to the present embodiment configured as described above, in the semiconductor device having a full silicide gate, the upper surface of full silicide gate electrode 5 is provided on the side surfaces of gate insulating film 4 and full silicide gate electrode 5. By providing the side wall spacer 9 that protrudes further upward, a transistor in which a short circuit between the full silicide gate electrode 5 and the source / drain diffusion layer 10 is reliably prevented is realized.

  In addition, the semiconductor device according to the present embodiment configured as described above includes a full silicide gate electrode 5 (metal gate electrode) obtained by siliciding the entire polysilicon electrode as a gate electrode, and a high gate insulating film. Since the gate insulating film 4 made of a dielectric constant gate insulating film (High-k) is provided, a transistor that is excellent in electrical characteristics and reliability and has both reduced power consumption during standby and high current driving capability is realized.

  Even when a short circuit occurs between the full silicide gate electrode 5 and the source / drain diffusion layer 10 via the surface of the sidewall spacer 9 in the structure of the first embodiment, the upper portion of the sidewall spacer 9 It is possible to recover from the short-circuit state by scraping and forming the transistor structure according to this embodiment.

  Furthermore, in the semiconductor device according to the present embodiment configured as described above, since the silicon nitride film deposition portion 31 is provided on the semiconductor substrate 1 in a region other than the transistor circuit element portion, The height is controlled with high accuracy, and a high-quality transistor is realized.

  Next, a method for manufacturing the semiconductor device according to the present embodiment shown in FIG. 18 will be described with reference to the drawings. In order to manufacture the semiconductor device according to the present embodiment, first, the structure shown in FIG. 5 is formed according to the manufacturing method (corresponding to FIGS. 2 to 5) described in the first embodiment.

  Next, before anisotropic etching of the insulating film 8, a part of the region other than the transistor circuit element portion on the semiconductor substrate 1 is covered with a photoresist 32 as shown in FIG. Then, anisotropic etching of the insulating film 8 is performed in the same manner as in the first embodiment, so that the periphery of the gate electrode 5b, the gate insulating film 4 and the TEOS oxide film 6 before silicidation is formed as shown in FIG. A sidewall spacer 9 made of an insulating film is formed. At the same time, a silicon nitride film deposition portion 31 is formed.

  Thereafter, the structure shown in FIG. 21 is formed in accordance with the manufacturing method described in the first and second embodiments. Then, similarly to the second embodiment, the interlayer insulating film 21 is polished by CMP (Chemical Mechanical Polish) to flatten the upper portion of the sidewall spacer 9. Here, in the present embodiment, the polishing of the interlayer insulating film 21 is performed under a condition with a high selectivity to the silicon nitride film. That is, the process is performed under a condition with a high selectivity with respect to the deposited portion 31 of the silicon nitride film. Thereby, as shown in FIG. 22, it is possible to control the polishing of the interlayer insulating film 21 with high accuracy by using the deposited portion 31 of the silicon nitride film as a stopper. Thereby, as shown in FIG. 22, the side wall spacer 9a having a flat upper portion can be formed.

  Thereafter, an interlayer insulating film 13 is deposited in the same manner as the manufacturing method described in the first embodiment, and a contact hole 14 reaching from the surface of the interlayer insulating film 13 to the silicide layer 10a is formed. Then, the contact hole 14 is filled with a material containing at least a conductive material to form a contact 15 that is electrically connected to the silicide layer 10a (source / drain diffusion layer 10). Further, by forming a wiring layer 16 that is electrically connected to the contact 15 on the interlayer insulating film 13, the semiconductor device according to the present embodiment shown in FIG. 18 can be manufactured.

  In the method of manufacturing a semiconductor device as described above, a full silicide gate electrode 5 (metal gate electrode) in which the entire polysilicon electrode is silicided is formed as a gate electrode, and a high dielectric constant gate insulating film (High Since the gate insulating film 4 made of -k) is formed, it is possible to manufacture a transistor that has excellent electrical characteristics and reliability and achieves both low power consumption during standby and high current drive capability.

  Further, in the manufacturing method of the semiconductor device as described above, the sidewall spacers 9 protruding above the upper surface of the full silicide gate electrode 5 are formed on the side surfaces of the gate insulating film 4 and the full silicide gate electrode 5. A transistor in which a short circuit between the full silicide gate electrode 5 and the source / drain diffusion layer 10 is reliably prevented can be manufactured.

  In the method for manufacturing a semiconductor device as described above, the surface of the sidewall spacer 9 is formed when the structure of the first embodiment as shown in FIG. Even when a short-circuit occurs between the full silicide gate electrode 5 and the source / drain diffusion layer 10 via the top, it is possible to recover from the short-circuit state.

  Further, in the method for manufacturing a semiconductor device as described above, the deposition portion 31 of the silicon nitride film is formed on the semiconductor substrate 1 in a region other than the transistor circuit element portion. A high quality transistor can be manufactured by effectively preventing problems such as scraping off the full silicide gate electrode 5.

  As described above, the semiconductor device according to the present invention is useful for a semiconductor device using a fully silicided gate electrode in which the entire gate electrode is silicided, and is particularly suitable for a SoC transistor of the 45 nm generation or later.

1 is a cross-sectional view schematically showing the structure of a semiconductor device according to a first embodiment of the present invention. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. It is sectional drawing which shows typically the structure of the semiconductor device concerning Embodiment 2 of this invention. 7 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment; FIG. 7 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment; FIG. 7 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment; FIG. It is sectional drawing which shows typically the structure of the semiconductor device concerning Embodiment 3 of this invention. 12 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the third embodiment; FIG. 12 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the third embodiment; FIG. 12 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the third embodiment; FIG. 12 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the third embodiment; FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation | separation 3 Retrograde well 4 Gate insulating film 4a High dielectric constant insulating film 5 Full silicide gate electrode 5a Polysilicon film 5c Upper surface of full silicide gate electrode 6 TEOS oxide film 6a TEOS oxide film 7 Source / drain extension layer 8 Insulating film 9 Side wall spacer 9a Side wall spacer 9b Flat surface 10 Source / drain diffusion layer 10a Silicide layer 11 Photoresist 12 Metal layer 13 Interlayer insulating film 14 Contact hole 15 Contact 16 Wiring layer 21 Interlayer insulating film 31 Deposition part 32 Photo Resist

Claims (10)

A semiconductor substrate;
A pair of source / drain diffusion layers formed at predetermined intervals so as to define a channel region in a surface layer of the semiconductor substrate;
Silicide layers respectively formed on the surface layers of the pair of source / drain diffusion layers;
A gate insulating film formed in a region sandwiched between the pair of source / drain diffusion layers on the semiconductor substrate;
A gate electrode formed on and in contact with the gate insulating film on the gate insulating film, wherein the polysilicon is silicided;
An insulating sidewall provided on a side surface of the gate insulating film and the gate electrode, and protruding upward from an upper surface of the gate electrode;
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the gate insulating film is a high dielectric constant gate insulating film. The semiconductor device according to claim 1, wherein an upper surface of the insulating sidewall is flattened. The semiconductor device according to claim 3, further comprising a stopper for polishing and forming the insulating sidewall on the semiconductor substrate. An insulating film layer forming step of forming an insulating film layer for a gate insulating film on a semiconductor substrate;
A polysilicon layer forming step of forming a polysilicon layer for the gate electrode on the insulating film;
A molding step of patterning the gate insulating film insulating film layer and the polysilicon layer to form a gate electrode made of the gate insulating film and polysilicon;
Forming an insulating sidewall on the side surface of the gate electrode made of the gate insulating film and polysilicon, and forming an insulating sidewall protruding above the upper surface of the gate electrode made of polysilicon;
Forming a pair of source / drain diffusion layers at a predetermined interval so as to define a channel region in a peripheral region of the gate insulating film on a surface layer of the semiconductor substrate;
A silicide layer forming step of silicidizing the surface layer of the pair of source / drain diffusion layers to form a silicide layer on the surface layer of the pair of source / drain diffusion layers;
A full silicide gate electrode forming step of forming a full silicide gate electrode by siliciding the entire gate electrode made of polysilicon;
A method for manufacturing a semiconductor device, comprising: Performing the silicide layer forming step and the full silicide gate electrode forming step simultaneously;
A method for manufacturing a semiconductor device according to claim 5. Insulating sidewall forming process
Forming a dummy layer on the polysilicon gate electrode;
Forming an insulating layer on the dummy layer and on the semiconductor substrate;
Forming an insulating sidewall projecting above the upper surface of the gate electrode made of polysilicon on the side surface of the gate electrode made of polysilicon by anisotropically etching the insulating layer;
Removing the dummy layer;
A method for manufacturing a semiconductor device according to claim 5. The method for manufacturing a semiconductor device according to claim 5, further comprising a flattening step of flattening an upper surface of the insulating sidewall. The planarization step comprises:
Forming an insulating layer on the silicide layer, the full silicide gate electrode and the insulating sidewall;
Polishing the insulating metal wall together with the insulating layer to planarize the upper surface of the insulating sidewall;
The method of manufacturing a semiconductor device according to claim 8, further comprising: Forming a stopper for polishing the insulating sidewall on the semiconductor substrate;
Polishing the insulating metal wall together with the insulating layer using the stopper in the planarization step to planarize the upper surface of the insulating sidewall;
A method for manufacturing a semiconductor device according to claim 9.

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