JP4411677B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of forming a self-aligned contact in which contact failure is prevented between gate electrodes of a field effect transistor.
[0002]
[Prior art]
With the miniaturization of semiconductor integrated circuits, the distance between the gate of the transistor and the impurity diffusion layer formed on the surface of the semiconductor substrate is reduced. For this reason, it has been a problem that the contact provided on the impurity diffusion layer and the gate electrode are short-circuited due to misalignment of the lithography process. In order to avoid such a short circuit, a self-aligned contact (SAC) that covers the gate electrode upper portion and the side wall portion with a material different from the interlayer insulating film and prevents the contact from contacting or approaching the gate is provided. Technology has been proposed.
[0003]
In addition, when the misalignment between the contact and the impurity diffusion layer in the lithography process is large, a problem occurs in addition to the short circuit between the gate electrode and the contact as described above. When the contact is disposed on the element isolation region due to misalignment, the surface of the element isolation film is etched during contact etching. As a result, the contact comes into contact with the impurity diffusion layer or the substrate side wall portion joined to the impurity diffusion layer, and junction leakage increases.
[0004]
In order to prevent the etching of the element isolation film as described above, an etching stop film (etching stopper) made of a material having an etching rate slower than that of the interlayer insulating film is formed on the impurity diffusion layer and the element isolation film. A method of depositing an interlayer insulating film was proposed. According to this method, when the contact hole is formed, the etching is performed under such a condition that the etching rate is reduced by the etching stop film. The etching is stopped when the etching stop film is exposed, the etching is restarted after changing the etching conditions, and the etching stop film is removed. Thereby, since the etching of the element isolation film is suppressed, junction leakage is reduced.
[0005]
In recent years, integration of semiconductor devices has been accelerated, and the demand for layout reduction has increased. Therefore, it is necessary to achieve both the formation of the self-aligned contact on the impurity diffusion layer between the gate electrodes and the prevention of etching of the element isolation film during the contact formation.
A conventional technique for forming a contact in a self-aligned manner on the impurity diffusion layer between the gate electrodes while preventing the element isolation film from being etched during contact formation will be described below with reference to FIGS. To do.
[0006]
First, as shown in FIG. 8A, an element isolation region 2 (for example, LOCOS by thermal oxidation) is formed on the surface of the silicon substrate 1. A gate oxide film (SiO 2) is formed on the active region separated by the element isolation region 2. ₂ Film) 3 is formed. A polysilicon layer 4, a laminated film 5 of tungsten nitride and tungsten, and an offset insulating film (silicon nitride film) 6 are laminated thereon, and then these layers are patterned into the shape of a gate electrode. Here, the gate line width and the gate interval are, for example, 0.15 μm and 0.18 μm, respectively.
Using the patterned gate electrode as a mask, a relatively low concentration of impurities is ion-implanted into the silicon substrate 1 to form an LDD (lightly doped drain) region 7.
[0007]
Next, as shown in FIG. 8B, a silicon nitride film is deposited on the entire surface and then etched back to leave the silicon nitride film 8 only on the gate sidewall. Thereby, the sidewall 8 made of the silicon nitride film is formed. At this time, if the thickness of the sidewall 8 is 70 nm, for example, the distance between the gate electrodes is 0.04 μm.
A relatively high concentration of impurities is ion-implanted into the silicon substrate 1 using the sidewalls 8 as a mask, and then annealing is performed to activate the impurities, thereby forming the source / drain regions 9.
[0008]
Next, as shown in FIG. 8C, a silicon nitride film 10 serving as an etching stop film is formed on the entire surface with a film thickness of, for example, 30 nm. At this time, as schematically shown in FIG. 8C, the gap between the gate electrodes is filled with the silicon nitride film 10.
Thereafter, as shown in FIG. 9A, after depositing a silicon oxide film 11 serving as an interlayer insulating film on the entire surface, for example, chemical mechanical polishing (CMP) is performed to planarize the surface.
[0009]
A resist (not shown) is formed on the silicon oxide film 11 by a photolithography process, and then the silicon oxide film 11 is etched using the resist as a mask. Thereby, the contact hole 12 is formed. This etching is anisotropic etching and is performed under the condition that the etching rate of the silicon nitride film 10 is slower than that of the silicon oxide film 11. As a result, the etching stops on the silicon nitride film 10 as shown in FIG.
Subsequently, as shown in FIG. 9B, when anisotropic etching of the silicon nitride film 10 is performed by changing the etching conditions, the impurity diffusion layer between the gate electrodes is prevented while preventing the element isolation region 2 from being etched. A contact hole can be formed thereon in a self-aligning manner.
[0010]
As described above, as a method of forming the contact hole by forming the etching stop film, for example, there is a method described in JP-A-9-275140 or JP-A-9-232252.
The contact hole forming method disclosed in Japanese Patent Laid-Open No. 9-275140 is characterized in that an insulating film covering at least the upper portion of the gate electrode is added between the etching stopper film and the interlayer insulating film on the upper side thereof. .
[0011]
In the conventional contact hole forming method described above, actually, the etching selection ratio of the interlayer insulating film 11 to the etching stop film 10 is not uniform within the wafer surface due to the influence of the microloading effect or the like, and between the gate electrodes ( The etching selectivity is reduced on the gate electrode compared to the diffusion layer at the bottom of the contact hole 12). Therefore, in the step shown in FIG. 9A, the etching stop film 10 on the shoulder of the gate electrode exposed on the side wall of the contact hole 12 tends to disappear faster than the etching stop film 10 on the bottom of the contact hole 12. When the etching stopper film 10 on the shoulder portion of the gate electrode is etched, when the offset insulating film 6 and a part of the side wall 8 are etched, the breakdown voltage between the gate electrode and the contact hole 12 is lowered. Is short-circuited between the gate electrode and the contact hole 12.
[0012]
Therefore, according to the method described in Japanese Patent Laid-Open No. 9-275140, the etching rate of the interlayer insulating film is low at least above the gate electrode, taking into consideration the thickness of the etching stop film 10 to be etched. An insulating film is provided. Thereby, the breakdown voltage between the gate electrode and the contact hole 12 is secured.
[0013]
Further, in the method of forming a contact hole disclosed in Japanese Patent Laid-Open No. 9-232252, an etching stop film is formed to open a contact hole in the interlayer insulating film, and further, silicide is formed at the bottom of the opening to reduce the contact resistance. This is a reduction method. This invention is also one of the solutions for the difference in the etching rate of the etching stopper film between the upper part of the gate electrode and the diffusion layer between the gate electrodes, as in the invention described in Japanese Patent Laid-Open No. 9-275140. .
[0014]
On the diffusion layer between the gate electrodes (bottom of the contact hole), the etching stop film has a lower etching rate than the upper part of the gate electrode. The offset insulating film of the electrode is etched. In order to avoid this, if the etching amount (or over-etching) is reduced, the etching stop film remains at the bottom of the contact hole, resulting in a contact failure.
[0015]
Therefore, according to the method described in Japanese Patent Application Laid-Open No. 9-232252, the etching is stopped in a state where an etching stop film is partially left at the bottom of the contact hole, and a metal layer is formed on the etching stop film. Metal silicide is formed by reacting with the silicon inside. More preferably, an etching stop film made of a silicon nitride film is formed, the etching stop film remaining at the bottom of the contact hole is made a thin film having a thickness of 5 nm or less (0.5 to 5 nm), and then the etching stop film is made of silicon. Ion implantation. As a result, the silicon in the etching stopper film at the bottom of the contact hole can be positively silicidized with the upper metal layer.
[0016]
[Problems to be solved by the invention]
As described above, when an insulating film is provided on the gate electrode and an etching stop film is formed for the purpose of preventing the element isolation region from being etched by etching for forming a contact hole. The contact failure occurs when the film thickness of the etching stop film is less than half of the gate interval.
When the gate interval is reduced due to high integration of the semiconductor device, the space between the gates remains embedded with the silicon nitride film (etching stop film) 10 as shown in FIG. 9B. In this case, the contact between the gates does not reach the silicon substrate 1, resulting in contact failure.
[0017]
If the thickness of the silicon nitride film, which is the side wall of the gate electrode, is reduced in order to avoid contact failure between the gates, the source / drain region approaches immediately below the gate electrode when forming the source / drain region by ion implantation. In addition, the short channel effect of the transistor increases.
In addition, when the thickness of the sidewall is reduced, when the impurity diffusion layer is silicided for the purpose of reducing the resistance of the impurity diffusion layer, the silicide approaches immediately below the transistor. Therefore, the short channel effect of the transistor increases due to diffusion and stress of the refractory metal, and junction leakage in the diffusion layer around the gate increases.
[0018]
In each of the contact hole forming methods described in JP-A-9-275140 and JP-A-9-232252 described above, the etching rate of the etching stopper film differs between the upper part of the gate electrode and the diffusion layer between the gate electrodes. It is a solution to this.
However, when the space between the gates is reduced, it becomes difficult to remove the etching stopper film on the diffusion layer between the gate electrodes even by these methods. In the method described in Japanese Patent Laid-Open No. 9-232252, a part of the etching stop film is intentionally left on the diffusion layer between the gate electrodes, but when the film thickness of the remaining etching stop film exceeds a predetermined value Therefore, silicidation is not sufficiently performed, resulting in contact failure.
[0019]
The present invention has been made in view of the above problems, and therefore the present invention can form a contact hole in a self-aligned manner by preventing contact failure or junction leakage even when the space between gates is reduced. An object is to provide a method for manufacturing a semiconductor device.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductor layer on a substrate, a step of forming an offset insulating film on the conductor layer, the conductor layer, Processing the offset insulating film into a predetermined pattern to form a gate electrode; forming a first sidewall made of a first insulating film on a side wall of the gate electrode; and Forming a second sidewall made of a second insulating film on the surface of the sidewall; and introducing a impurity into the substrate using the second sidewall as a mask to form a source / drain region; Removing the second sidewall, forming a third insulating film on at least the gate electrode and the source / drain region, and forming an upper layer on the third insulating film. Forming an interlayer insulating film, etching the interlayer insulating film between the gate electrodes using the third insulating film as an etching stop film, and opening a contact hole in a self-aligned manner; and the contact hole And a step of removing the etching stop film at the bottom.
[0021]
The method for manufacturing a semiconductor device according to the present invention is preferably characterized in that the first sidewall is made of a silicon nitride film, and the second sidewall is made of a silicon oxide film. In the method for manufacturing a semiconductor device according to the present invention, preferably, the etching stop film is made of a silicon nitride film, and the interlayer insulating film is made of a silicon oxide film.
Preferably, in the method of manufacturing a semiconductor device according to the present invention, an LDD (lightly doped drain) region is formed by introducing an impurity having a concentration lower than that of the source / drain region into the substrate using the gate electrode as a mask. It is characterized by having.
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of forming the first sidewall, a first insulating film is formed on the entire surface, and the first insulating film is formed only on the sidewall of the gate electrode. It is a step of performing anisotropic etching so that the film remains. In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of forming the second sidewall, the second insulating film is formed on the entire surface, and the second insulating film is formed only on the sidewall of the gate electrode. It is a process of performing anisotropic etching so that two insulating films remain.
[0022]
Thereby, while preventing deterioration of transistor characteristics due to an increase in the short channel effect, the insulating film (side wall) on the gate side wall can be thinned, and the space between the source / drain region and the gate electrode can be expanded. In addition, in order to prevent leakage current at the edge of the element isolation region, even if an etching stop film is formed, a contact can be formed on the diffusion layer between the gate electrodes that is narrower than before.
Accordingly, the design rule can be reduced, and the semiconductor device can be highly integrated to increase the speed and power consumption.
[0023]
Furthermore, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a conductor layer on a substrate, a step of forming an offset insulating film on the conductor layer, and the conductor. Processing the layer and the offset insulating film into a predetermined pattern to form a gate electrode; forming a first sidewall made of a first insulating film on a sidewall of the gate electrode; Forming a second sidewall made of a second insulating film on the surface of the first sidewall, and introducing a dopant into the substrate using the second sidewall as a mask to form a source / drain region A step of forming a refractory metal layer on the entire surface, a step of performing heat treatment to form a refractory metal silicide on the surface of the source / drain region, and removing an unreacted refractory metal layer. A step of removing the second sidewall, a step of forming a third insulating film over at least the gate electrode and the source / drain region, and an interlayer over the third insulating film. Forming an insulating film; etching the interlayer insulating film between the gate electrodes using the third insulating film as an etching stop film; and opening a contact hole in a self-aligned manner; and bottom of the contact hole And removing the etching stop film.
[0024]
The method for manufacturing a semiconductor device according to the present invention is preferably characterized in that the refractory metal layer contains cobalt, titanium or nickel. In the method of manufacturing a semiconductor device according to the present invention, preferably, the first sidewall is made of a silicon nitride film, and the second sidewall is made of a silicon oxide film. The method for manufacturing a semiconductor device of the present invention is preferably characterized in that the etching stop film is made of a silicon nitride film and the interlayer insulating film is made of a silicon oxide film.
[0025]
The semiconductor device manufacturing method of the present invention preferably includes a step of forming an LDD region by introducing an impurity at a concentration lower than that of the source / drain region into the substrate using the gate electrode as a mask. And
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of forming the first sidewall, a first insulating film is formed on the entire surface, and the first insulating film is formed only on the sidewall of the gate electrode. It is a step of performing anisotropic etching so that the film remains.
In the method of manufacturing a semiconductor device according to the present invention, preferably, in the step of forming the second sidewall, the second insulating film is formed on the entire surface, and the second insulating film is formed only on the sidewall of the gate electrode. It is a process of performing anisotropic etching so that an insulating film remains.
[0026]
Thereby, while preventing deterioration of transistor characteristics due to an increase in the short channel effect, the insulating film (side wall) on the gate side wall can be thinned, and the space between the source / drain region and the gate electrode can be expanded. Further, according to the method for manufacturing the semiconductor device of the present embodiment, the second sidewall is removed after the silicide is formed. When silicidation is performed, crystal defects such as point defects or dislocations are generated due to diffusion and stress of the refractory metal. However, since silicidation is performed with the second sidewall formed, diffusion of the refractory metal is performed. And the effect of stress is reduced. Therefore, an increase in the short channel effect due to crystal defects due to silicidation can also be prevented.
[0027]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductor layer on a substrate, a step of forming an offset insulating film on the conductor layer, the conductor layer, Processing the offset insulating film into a predetermined pattern to form a gate electrode, forming a sidewall made of a first insulating film on the sidewall of the gate electrode, and using the sidewall as a mask, Introducing impurities into the substrate to form source / drain regions; removing a surface of the sidewall to expose at least a portion of the substrate covered by the sidewall; and at least the gate electrode And forming a second insulating film on the source / drain region, forming an interlayer insulating film on the second insulating film, and Etching the interlayer insulating film between the gate electrodes using the insulating film of 2 as an etching stop film, and opening a contact hole in a self-aligned manner; and removing the etch stop film at the bottom of the contact hole; It is characterized by having.
[0028]
In the method for manufacturing a semiconductor device of the present invention, it is preferable that the step of removing the surface of the sidewall is a step of performing isotropic etching on the sidewall. The method for manufacturing a semiconductor device according to the present invention is preferably characterized in that the sidewall is made of a silicon nitride film. Alternatively, the semiconductor device manufacturing method of the present invention is preferably characterized in that the sidewall is made of a silicon oxide film.
The method for manufacturing a semiconductor device of the present invention is preferably characterized in that the etching stop film is made of a silicon nitride film and the interlayer insulating film is made of a silicon oxide film.
[0029]
The semiconductor device manufacturing method of the present invention preferably includes a step of forming an LDD region by introducing an impurity at a concentration lower than that of the source / drain region into the substrate using the gate electrode as a mask. And
In the method for manufacturing a semiconductor device according to the present invention, preferably, in the step of forming the sidewall, a first insulating film is formed on the entire surface, and the first insulating film remains only on the sidewall of the gate electrode. Thus, it is a process of performing anisotropic etching.
[0030]
Thereby, while preventing deterioration of transistor characteristics due to an increase in the short channel effect, the insulating film (side wall) on the gate side wall can be thinned, and the space between the source / drain region and the gate electrode can be expanded. In addition, in order to prevent leakage current at the edge of the element isolation region, even if an etching stop film is formed, a contact can be formed on the diffusion layer between the gate electrodes that is narrower than before.
Accordingly, the design rule can be reduced, and the semiconductor device can be highly integrated to increase the speed and power consumption.
[0031]
Furthermore, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a conductor layer on a substrate, a step of forming an offset insulating film on the conductor layer, and the conductor. Forming a gate electrode by processing the layer and the offset insulating film into a predetermined pattern; forming a sidewall made of a first insulating film on a sidewall of the gate electrode; and masking the sidewall As a step, an impurity is introduced into the substrate to form a source / drain region, a step of forming a refractory metal layer over the entire surface, and heat treatment to form a refractory metal silicide on the surface of the source / drain region. A step of removing an unreacted refractory metal layer; removing a surface of the sidewall; and at least a part of the substrate covered with the sidewall Exposing, forming a second insulating film over at least the gate electrode and the source / drain region, forming an interlayer insulating film over the second insulating film, and the second Etching the interlayer insulating film between the gate electrodes using an insulating film as an etching stop film to open a contact hole in a self-aligned manner and removing the etch stop film at the bottom of the contact hole It is characterized by that.
[0032]
In the method for manufacturing a semiconductor device of the present invention, it is preferable that the step of removing the surface of the sidewall is a step of performing isotropic etching on the sidewall. The method for manufacturing a semiconductor device according to the present invention is preferably characterized in that the refractory metal layer contains cobalt, titanium or nickel.
The method for manufacturing a semiconductor device according to the present invention is preferably characterized in that the sidewall is made of a silicon nitride film. Alternatively, the semiconductor device manufacturing method of the present invention is preferably characterized in that the sidewall is made of a silicon oxide film.
[0033]
The method for manufacturing a semiconductor device of the present invention is preferably characterized in that the etching stop film is made of a silicon nitride film and the interlayer insulating film is made of a silicon oxide film. In addition, the method for manufacturing a semiconductor device according to the present invention preferably includes a step of forming an LDD region by introducing an impurity at a concentration lower than that of the source / drain region into the substrate using the gate electrode as a mask. It is characterized by.
In the method for manufacturing a semiconductor device according to the present invention, preferably, in the step of forming the sidewall, a first insulating film is formed on the entire surface, and the first insulating film remains only on the sidewall of the gate electrode. Thus, it is a process of performing anisotropic etching.
[0034]
Thereby, while preventing deterioration of transistor characteristics due to an increase in the short channel effect, the insulating film (side wall) on the gate side wall can be thinned, and the space between the source / drain region and the gate electrode can be expanded. Further, according to the method for manufacturing a semiconductor device of the present embodiment, the removal of the sidewall surface (thinning of the sidewall) is performed after the formation of the silicide. When silicidation is performed, crystal defects such as point defects or dislocations are generated due to diffusion or stress of the refractory metal. However, since silicidation is performed before the sidewall is thinned, The effect of stress is reduced. Therefore, an increase in the short channel effect due to crystal defects due to silicidation can also be prevented.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
A method for manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS.
First, as shown in FIG. 1A, an element isolation region 2 is formed on the surface of a silicon substrate 1 in the same manner as in the conventional method. Further, ion implantation of impurities for forming a p well or an n well in the substrate 1 is performed as necessary. A gate oxide film (SiO 2) is formed on the active region separated by the element isolation region 2. ₂ Film) 3 is formed. The thickness of the gate oxide film is 3 nm, for example.
[0036]
A polysilicon layer 4, a laminated film 5 of tungsten nitride and tungsten, and an offset insulating film (silicon nitride film) 6 are laminated thereon. The film thickness of each layer is, for example, 70 nm, 5 nm (tungsten nitride), 60 nm (tungsten), and 100 nm, respectively. After laminating these layers, etching is performed using a resist (not shown) as a mask to pattern the gate electrode. Here, the gate line width and the gate interval are, for example, 0.15 μm and 0.18 μm, respectively.
Using the patterned gate electrode as a mask, a relatively low concentration of impurities is ion-implanted into the silicon substrate 1 to form an LDD (lightly doped drain) region 7.
[0037]
Next, as shown in FIG. 1B, a silicon nitride film is deposited on the entire surface and then etched back to leave the silicon nitride film 8 only on the gate side wall, thereby forming a first side wall 8. At this time, the thickness of the silicon nitride film remaining on the gate side wall in the direction horizontal to the substrate surface (the thickness of the first sidewall 8) is substantially equal to the thickness when the silicon nitride film is deposited on the entire surface. For example, it is 50 nm. Therefore, the interval between the gate electrodes is 0.08 μm.
[0038]
Next, as shown in FIG. 1C, a silicon oxide film 13 is deposited on the entire surface to a thickness of 20 nm, for example. The silicon oxide film 13 formed on the side wall of the gate electrode, that is, the surface of the first sidewall 8 becomes the second sidewall 13 ′. In order to form the source / drain regions 9 in the silicon substrate 1, a relatively high concentration of impurities is ion-implanted using the second sidewall 13 ′ as a mask. A first sidewall (silicon nitride film) 8 having a thickness of 50 nm and a second sidewall 13 ′ having a thickness of 20 nm are formed on the side wall of the gate electrode, and these are formed on the gate during ion implantation. On the other hand, it functions as a spacer having a film thickness of 70 nm.
[0039]
As shown in FIG. 2A, source / drain regions 9 are formed by annealing at 1000 ° C. for 10 seconds in a nitrogen atmosphere after ion implantation.
Next, anisotropic etching is performed on the silicon oxide film 13 to remove only the silicon oxide film 13 on the gate side wall. The thickness of the first sidewall 8 and the second sidewall 13 'remaining on the gate sidewall portion in the direction horizontal to the substrate surface (total sidewall thickness) is, for example, 70 nm.
[0040]
Next, as shown in FIG. 2B, for example, cobalt as a refractory metal is deposited to a thickness of 10 nm on the entire surface to form cobalt silicide 14. For example, the cobalt layer is formed at a substrate temperature of 450 ° C., and then the cobalt layer is reacted with polysilicon by lamp annealing at 550 ° C. for 30 seconds. The unreacted cobalt layer is removed using, for example, sulfuric acid / hydrogen peroxide solution. Thus, the cobalt silicide 14 is formed in a self-aligned manner only on the impurity diffusion layer of the substrate.
After that, as shown in FIG. 2C, the silicon oxide film 13 (second sidewall 13 ′) on the gate sidewall is light etched (HF / H) using, for example, a hydrofluoric acid based solution. ₂ O = 1/400, 80 seconds).
[0041]
According to the method for manufacturing a semiconductor device of this embodiment, the second sidewall 13 ′ is removed after ion implantation for forming the source / drain region 9 and formation of the cobalt silicide 14.
Therefore, an increase in the short channel effect due to the spread of the source / drain regions, which is observed when a thin sidewall is formed, is prevented. Further, when silicidation is performed, crystal defects such as point defects or dislocations are generated due to diffusion or stress of the refractory metal. However, since silicidation is performed with the second sidewall 13 ′ formed, The influence of diffusion and stress of melting point metal is reduced. Therefore, an increase in the short channel effect due to crystal defects due to silicidation can also be prevented.
In the semiconductor device manufacturing method of this embodiment, the insulating film (side wall) on the gate side wall can be thinned without increasing the short channel effect of the transistor due to the spread of the source / drain regions or crystal defects. This is possible, and contact failure can be prevented.
[0042]
Next, as shown in FIG. 3A, a silicon nitride film 10 is formed on the entire surface as an etching stop film with a film thickness of 20 nm, for example. On top of that, a silicon oxide film 11 is deposited as an interlayer insulating film with a film thickness of 1200 nm, for example, and the step formed on the surface of the silicon substrate 1 is flattened. Further, CMP is performed until the thickness of the silicon oxide film 11 becomes 700 nm, for example, to flatten the surface of the silicon oxide film 11.
Subsequently, as shown in FIG. 3B, a resist (not shown) is formed on the upper layer of the silicon oxide film 11 by a photolithography process, and then the silicon oxide film 11 is etched using the resist as a mask. Thereby, the contact hole 12 is formed.
[0043]
This etching is anisotropic etching and is performed under the condition that the etching rate of the silicon oxide film 11 is 20 times that of the silicon nitride film 10 (the etching selectivity of the silicon oxide film 11 is 20). Etching corresponding to the 900 nm-thickness silicon oxide film including over-etching for flattening the surface to be etched is performed on the silicon nitride film 10 by performing, for example, the following etching conditions. .
(Etching conditions)
RF power: 2kW
Etching gas: Ar / O ₂ / C _Four F ₈ = 200/10 / 20sccm
Pressure: 5Pa
[0044]
Next, as shown in FIG. 3C, the etching rate of the silicon nitride film 10 is 10 times that of the silicon substrate 1 (etching selectivity 10) and 7 times that of the silicon oxide film 11 (etching selectivity 7). The silicon nitride film 10 is etched under conditions such that Etching corresponding to the silicon nitride film having a thickness of 30 nm is performed under the following conditions, including overetching for flattening the surface to be etched.
(Etching conditions)
RF power: 500W
Etching gas: Ar / O ₂ / CHF _Three = 100/10 / 20sccm
Pressure: 5Pa
[0045]
After the contact hole 12 is formed as described above, a titanium layer and a titanium nitride layer serving as an adhesion layer or a barrier layer are formed with a thickness of, for example, 20 nm and 50 nm, respectively, on the entire surface including the inside of the contact hole 12 by a conventional method. Further, a tungsten layer is formed to a thickness of 250 nm so as to fill the contact hole 12. Thereafter, CMP is performed to remove the titanium layer, titanium nitride layer, and tungsten layer on the interlayer insulating film 11, thereby forming a tungsten plug in the contact hole 12.
[0046]
In FIG. 3C, the thickness of the insulating film sidewall provided on the side wall of the gate is compared with 70 nm in the case where it is formed by a conventional method (see FIG. 8B). As the side wall 13 ') is removed, the film thickness can be reduced to 20 nm. Therefore, as in the conventional method, even if an etching stop film (silicon nitride film 10) having a thickness of 20 nm is formed, the space between the gate electrodes is filled with the silicon nitride film 10 (see FIG. 9B). Instead, the contact is connected to the impurity diffusion layer (source / drain region 9) between the gate electrodes. Thereby, contact failure can be prevented.
[0047]
According to the semiconductor device manufacturing method of the present embodiment, the gate sidewall insulating film (sidewall) is thinned while preventing deterioration of transistor characteristics due to an increase in the short channel effect, and the source / drain regions and the gate electrode are reduced. The space between can be expanded. In addition, in order to prevent leakage current at the edge of the element isolation region, even if an etching stop film is formed, a contact can be formed on the diffusion layer between the gate electrodes that is narrower than before. Accordingly, the design rule can be reduced, and the semiconductor device can be highly integrated to increase the speed and power consumption.
[0048]
(Embodiment 2)
A method for manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS.
First, as shown in FIG. 4A, the element isolation region 2 is formed on the surface of the silicon substrate 1 in the same manner as in the conventional method. Further, ion implantation of impurities for forming a p well or an n well in the substrate 1 is performed as necessary. A gate oxide film (SiO 2) is formed on the active region separated by the element isolation region 2. ₂ Film) 3 is formed. The thickness of the gate oxide film is 3 nm, for example.
[0049]
A polysilicon layer 4, a laminated film 5 of tungsten nitride and tungsten, and an offset insulating film (silicon nitride film) 6 are laminated thereon. The film thickness of each layer is, for example, 70 nm, 5 nm (tungsten nitride), 60 nm (tungsten), and 100 nm, respectively. After laminating these layers, anisotropic etching is performed using a resist (not shown) as a mask to pattern the gate electrode. Here, the gate line width and the gate interval are, for example, 0.15 μm and 0.18 μm, respectively.
Using the patterned gate electrode as a mask, a relatively low concentration of impurities is ion-implanted into the silicon substrate 1 to form an LDD region 7.
[0050]
Next, as shown in FIG. 4B, a silicon nitride film of, eg, a 70 nm-thickness is deposited on the entire surface, and then etched back to leave the silicon nitride film 8 only on the gate sidewall, thereby forming the sidewall 8. To do. At this time, the thickness of the silicon nitride film remaining on the gate side wall in the direction horizontal to the substrate surface (the thickness of the first sidewall 8) is substantially equal to the thickness when the silicon nitride film is deposited on the entire surface. For example, it is 70 nm. Therefore, the interval between the gate electrodes is 0.04 μm.
In order to form the source / drain regions 9 in the silicon substrate 1, a relatively high concentration of impurities is ion-implanted using the sidewalls 8 as a mask. After ion implantation, source / drain regions 9 are formed by performing lamp annealing at 1000 ° C. for 10 seconds in a nitrogen atmosphere.
[0051]
Next, as shown in FIG. 4C, the offset insulating film 6 made of a silicon nitride film and the sidewall 8 made of a silicon nitride film on the surface of the gate electrode are etched isotropically, for example, 20 nm. This etching is performed under the condition that the etching rate of the silicon nitride film 8 is 5 times or more (etching selectivity 5 times or more) with respect to the element isolation region 2 made of the silicon substrate 1 and the silicon oxide film. Etching conditions can be used.
(Etching conditions)
RF power: 700W
Etching gas: CF _Four / CH ₂ F ₂ / O ₂ / N ₂ = 200/200/300 / 200sccm
Pressure: 130Pa
[0052]
In the method of manufacturing a semiconductor device according to the present embodiment, after the source / drain regions 9 are formed, the silicon nitride film (sidewall) 8 is thinned. Therefore, the source / drain region does not expand as seen when the thin sidewall is formed, and an increase in the short channel effect due to the extension of the source / drain region is prevented. Further, by reducing the thickness of the sidewall 8, a sufficient contact area is secured on the impurity diffusion layer between the gates, and contact failure is prevented.
[0053]
Next, as shown in FIG. 5A, a silicon nitride film 10 is formed as an etching stop film on the entire surface with a film thickness of 20 nm, for example. On the upper layer, as shown in FIG. 5B, a silicon oxide film 11 is deposited as an interlayer insulating film with a film thickness of, for example, 1200 nm, and the step formed on the surface of the silicon substrate 1 is flattened. Further, CMP is performed until the thickness of the silicon oxide film 11 becomes 700 nm, for example, to flatten the surface of the silicon oxide film 11.
Subsequently, after a resist (not shown) is formed on the upper layer of the silicon oxide film 11 by a photolithography process, the silicon oxide film 11 is etched using the resist as a mask. Thereby, the contact hole 12 is formed.
[0054]
This etching is anisotropic etching and is performed under the condition that the etching rate of the silicon oxide film 11 is 20 times that of the silicon nitride film 10 (the etching selectivity of the silicon oxide film 11 is 20). Etching corresponding to the 900 nm-thickness silicon oxide film including over-etching for flattening the surface to be etched is performed on the silicon nitride film 10 by performing, for example, the following etching conditions. .
(Etching conditions)
RF power: 2kW
Etching gas: Ar / O ₂ / C _Four F ₈ = 200/10 / 20sccm
Pressure: 5Pa
[0055]
Next, as shown in FIG. 5C, the etching rate of the silicon nitride film 10 is 10 times that of the silicon substrate 1 (etching selectivity 10) and 7 times that of the silicon oxide film 11 (etching selectivity 7). The silicon nitride film 10 is etched under conditions such that Etching corresponding to the silicon nitride film having a film thickness of 35 nm, including overetching for flattening the surface to be etched, can be performed, for example, under the following conditions.
(Etching conditions)
RF power: 500W
Etching gas: Ar / O ₂ / CHF _Three = 100/10 / 20sccm
Pressure: 5Pa
[0056]
After the contact hole 12 is formed as described above, a titanium layer and a titanium nitride layer serving as an adhesion layer or a barrier layer are formed with a thickness of, for example, 20 nm and 50 nm, respectively, on the entire surface including the inside of the contact hole 12 by a conventional method. Further, a tungsten layer is formed to a thickness of 250 nm so as to fill the contact hole 12. Thereafter, CMP is performed to remove the titanium layer, titanium nitride layer, and tungsten layer on the interlayer insulating film 11, thereby forming a tungsten plug in the contact hole 12.
[0057]
In the manufacturing method of the semiconductor device of this embodiment, as shown in FIG. 4B, after forming the source / drain region 9 in a state where the space between the gate electrodes is 0.04 μm, FIG. ), Isotropic etching of 20 nm is performed, and the space between the gate electrodes is set to 0.08 μm. Therefore, as in the conventional method, even if an etching stop film (silicon nitride film 10) having a thickness of 20 nm is formed, the space between the gate electrodes is filled with the silicon nitride film 10 (see FIG. 9B). Instead, the contact is connected to the impurity diffusion layer (source / drain region 9) between the gate electrodes. Thereby, contact failure can be prevented.
[0058]
As described above, according to the semiconductor device manufacturing method of the present embodiment, the gate sidewall insulating film (sidewall) is thinned while preventing the deterioration of the transistor characteristics due to the increase of the short channel effect. The space between the drain region and the gate electrode can be expanded. In addition, in order to prevent leakage current at the edge of the element isolation region, even if an etching stop film is formed, a contact can be formed on the diffusion layer between the gate electrodes that is narrower than before. Accordingly, the design rule can be reduced, and the semiconductor device can be highly integrated to increase the speed and power consumption.
[0059]
(Embodiment 3)
A method for manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS.
First, as shown in FIG. 6A, the element isolation region 2 is formed on the surface of the silicon substrate 1 in the same manner as in the conventional method. Further, ion implantation of impurities for forming a p well or an n well in the substrate 1 is performed as necessary. A gate oxide film (SiO 2) is formed on the active region separated by the element isolation region 2. ₂ Film) 3 is formed. The thickness of the gate oxide film is 3 nm, for example.
[0060]
A polysilicon layer 4, a laminated film 5 of tungsten nitride and tungsten, and an offset insulating film (silicon nitride film) 6 are laminated thereon. The film thickness of each layer is, for example, 70 nm, 5 nm (tungsten nitride), 60 nm (tungsten), and 100 nm, respectively. After laminating these layers, anisotropic etching is performed using a resist (not shown) as a mask to pattern the gate electrode. Here, the gate line width and the gate interval are, for example, 0.15 μm and 0.18 μm, respectively.
Using the patterned gate electrode as a mask, a relatively low concentration of impurities is ion-implanted into the silicon substrate 1 to form an LDD region 7.
[0061]
Next, as shown in FIG. 6B, a silicon oxide film 15 of, eg, a 70 nm-thickness is deposited on the entire surface, and then etch back is performed to leave the silicon oxide film 15 only on the gate side wall. Form. At this time, the thickness of the silicon oxide film remaining on the gate side wall portion in the direction horizontal to the substrate surface (thickness of the side wall 15) is substantially equal to the thickness when the silicon oxide film is deposited on the entire surface. 70 nm. Therefore, the interval between the gate electrodes is 0.04 μm.
In order to form the source / drain region 9 in the silicon substrate 1, a relatively high concentration of impurities is ion-implanted using the sidewall 15 as a mask. After ion implantation, source / drain regions 9 are formed by performing lamp annealing at 1000 ° C. for 10 seconds in a nitrogen atmosphere.
[0062]
Next, as shown in FIG. 6C, the sidewall 15 made of a silicon oxide film is isotropically etched, for example, 20 nm. This etching is performed under the condition that the etching rate of the silicon oxide film 15 is 5 times or more (etching selection ratio is 5 times or more) with respect to the silicon substrate 1 and the offset insulating film (silicon nitride film) 6 on the gate electrode surface. . This etching is, for example, light etching using a hydrofluoric acid chemical (HF / H ₂ O = 1/400, 80 seconds).
[0063]
Next, as shown in FIG. 7A, a silicon nitride film 10 is formed on the entire surface as an etching stop film with a film thickness of 20 nm, for example.
Subsequently, as shown in FIG. 7B, a silicon oxide film 11 is deposited as an interlayer insulating film with a film thickness of, for example, 1200 nm on the silicon nitride film 10, and the step formed on the surface of the silicon substrate 1 is flattened. Turn into. Further, CMP is performed until the thickness of the silicon oxide film 11 becomes 700 nm, for example, to flatten the surface of the silicon oxide film 11. A resist (not shown) is formed on the silicon oxide film 11 by a photolithography process, and then the silicon oxide film 11 is etched using the resist as a mask. Thereby, the contact hole 12 is formed.
[0064]
This etching is anisotropic etching and is performed under the condition that the etching rate of the silicon oxide film 11 is 20 times that of the silicon nitride film 10 (the etching selectivity of the silicon oxide film 11 is 20). Etching corresponding to the 900 nm-thickness silicon oxide film including over-etching for flattening the surface to be etched is performed on the silicon nitride film 10 by performing, for example, the following etching conditions. .
(Etching conditions)
RF power: 2kW
Etching gas: Ar / O ₂ / C _Four F ₈ = 200/10 / 20sccm
Pressure: 5Pa
[0065]
Next, as shown in FIG. 7C, the etching rate of the silicon nitride film 10 is 10 times that of the silicon substrate 1 (etching selectivity 10) and 7 times that of the silicon oxide film 11 (etching selectivity 7). The silicon nitride film 10 is etched under conditions such that Etching corresponding to the silicon nitride film having a film thickness of 35 nm is performed under the following etching conditions, for example, including overetching for flattening the surface to be etched.
(Etching conditions)
RF power: 500W
Etching gas: Ar / O ₂ / CHF _Three = 100/10 / 20sccm
Pressure: 5Pa
[0066]
After the contact hole 12 is formed as described above, a titanium layer and a titanium nitride layer serving as an adhesion layer or a barrier layer are formed with a thickness of, for example, 20 nm and 50 nm, respectively, on the entire surface including the inside of the contact hole 12 by a conventional method. Further, a tungsten layer is formed to a thickness of 250 nm so as to fill the contact hole 12. Thereafter, CMP is performed to remove the titanium layer, titanium nitride layer, and tungsten layer on the interlayer insulating film 11, thereby forming a tungsten plug in the contact hole 12.
[0067]
In the manufacturing method of the semiconductor device of this embodiment, as shown in FIG. 6B, after forming the source / drain region 9 in a state where the space between the gate electrodes is 0.04 μm, FIG. ), Isotropic etching of 20 nm is performed, and the space between the gate electrodes is set to 0.08 μm. Therefore, as in the conventional method, even if an etching stop film (silicon nitride film 10) having a thickness of 20 nm is formed, the space between the gate electrodes is filled with the silicon nitride film 10 (see FIG. 9B). Instead, the contact is connected to the impurity diffusion layer (source / drain region 9) between the gate electrodes. Thereby, contact failure can be prevented.
[0068]
As described above, according to the semiconductor device manufacturing method of the present embodiment, the gate sidewall insulating film (sidewall) is thinned while preventing the deterioration of the transistor characteristics due to the increase of the short channel effect. The space between the drain region and the gate electrode can be expanded. Also, when an etching stop film is formed for the purpose of preventing leakage current at the end of the element isolation region, a contact can be formed on the diffusion layer between the gate electrodes that is narrower than the conventional one. Accordingly, the design rule can be reduced, and the semiconductor device can be highly integrated to increase the speed and power consumption.
[0069]
Embodiments of the semiconductor device manufacturing method of the present invention are not limited to the above description. For example, in Embodiment 2 or Embodiment 3, the surface of the impurity diffusion layer (source / drain region 9) may be silicided as in Embodiment 1. In this case, the diffusion layer is silicided before the step of thinning the sidewalls by isotropic etching. Thus, when silicidation is performed, the occurrence of crystal defects such as point defects or dislocations due to diffusion of refractory metal or stress is reduced, and an increase in the short channel effect due to crystal defects is prevented.
In addition, various modifications can be made without departing from the scope of the present invention.
[0070]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, the insulating film (side wall) on the gate side wall is made thin while preventing the deterioration of the transistor characteristics due to the increase in the short channel effect, and the space between the source / drain region and the gate electrode is reduced. Can be expanded. Therefore, even when the space between the gates is narrow, it is possible to prevent contact failure or junction leakage and form a contact hole in a self-aligning manner.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS.
FIGS. 3A to 3C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS.
4A to 4C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
5A to 5C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
6A to 6C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to Embodiment 3 of the present invention.
FIGS. 7A to 7C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIGS.
8A to 8C are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor device.
FIGS. 9A and 9B are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor device. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation region, 3 ... Gate oxide film, 4 ... Polysilicon layer, 5 ... Laminated film of tungsten nitride and tungsten, 6 ... Offset insulating film (silicon nitride film), 7 ... LDD region, DESCRIPTION OF SYMBOLS 8 ... Side wall, 9 ... Source / drain region, 10 ... Etching stop film, 11 ... Interlayer insulating film, 12 ... Contact hole, 13 ... Silicon oxide film, 13 '... 2nd side wall, 14 ... Cobalt silicide, 15 ... Silicon oxide film (side wall).

Claims (28)

Forming a conductor layer on the substrate;
Forming an offset insulating film on the conductor layer;
Processing the conductor layer and the offset insulating film into a predetermined pattern to form a gate electrode;
Forming a first sidewall made of a first insulating film on the sidewall of the gate electrode;
Forming a second sidewall made of a second insulating film on the surface of the first sidewall;
Using the second sidewall as a mask, introducing impurities into the substrate to form source / drain regions;
Removing the second sidewall;
Forming a third insulating film on at least the gate electrode and the source / drain regions;
Forming an interlayer insulating film on the third insulating film; and
Etching the interlayer insulating film between the gate electrodes using the third insulating film as an etching stop film, and opening a contact hole in a self-aligning manner;
Removing the etching stop film at the bottom of the contact hole. The method of manufacturing a semiconductor device according to claim 1, wherein the first sidewall is made of a silicon nitride film, and the second sidewall is made of a silicon oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching stop film is made of a silicon nitride film, and the interlayer insulating film is made of a silicon oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an LDD (lightly doped drain) region by introducing an impurity having a lower concentration than the source / drain region into the substrate using the gate electrode as a mask. The step of forming the first sidewall is a step of performing anisotropic etching so that the first insulating film is formed on the entire surface and the first insulating film remains only on the sidewall of the gate electrode. A method of manufacturing a semiconductor device according to claim 1. The step of forming the second sidewall includes the step of forming the second insulating film on the entire surface and performing anisotropic etching so that the second insulating film remains only on the sidewall of the gate electrode. The method of manufacturing a semiconductor device according to claim 1. Forming a conductor layer on the substrate;
Forming an offset insulating film on the conductor layer;
Processing the conductor layer and the offset insulating film into a predetermined pattern to form a gate electrode;
Forming a first sidewall made of a first insulating film on the sidewall of the gate electrode;
Forming a second sidewall made of a second insulating film on the surface of the first sidewall;
Using the second sidewall as a mask, introducing impurities into the substrate to form source / drain regions;
Forming a refractory metal layer on the entire surface;
Performing a heat treatment to form a refractory metal silicide on the surface of the source / drain region;
Removing the unreacted refractory metal layer;
Removing the second sidewall;
Forming a third insulating film on at least the gate electrode and the source / drain regions;
Forming an interlayer insulating film on the third insulating film; and
Etching the interlayer insulating film between the gate electrodes using the third insulating film as an etching stop film, and opening a contact hole in a self-aligning manner;
Removing the etching stop film at the bottom of the contact hole. The semiconductor device manufacturing method according to claim 7, wherein the refractory metal layer contains cobalt, titanium, or nickel. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the first sidewall is made of a silicon nitride film, and the second sidewall is made of a silicon oxide film. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching stop film is made of a silicon nitride film, and the interlayer insulating film is made of a silicon oxide film. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming an LDD region by introducing an impurity having a concentration lower than that of the source / drain region into the substrate using the gate electrode as a mask. The step of forming the first sidewall is a step of performing anisotropic etching so that the first insulating film is formed on the entire surface and the first insulating film remains only on the sidewall of the gate electrode. A method for manufacturing a semiconductor device according to claim 7. The step of forming the second sidewall includes the step of forming the second insulating film on the entire surface and performing anisotropic etching so that the second insulating film remains only on the sidewall of the gate electrode. The method of manufacturing a semiconductor device according to claim 7. Forming a conductor layer on the substrate;
Forming an offset insulating film on the conductor layer;
Processing the conductor layer and the offset insulating film into a predetermined pattern to form a gate electrode;
Forming a sidewall made of a first insulating film on the sidewall of the gate electrode;
Using the sidewall as a mask, introducing impurities into the substrate, and forming source / drain regions;
Removing the surface of the sidewall and exposing at least a portion of the substrate covered by the sidewall;
Forming a second insulating film on at least the gate electrode and the source / drain regions;
Forming an interlayer insulating film on the second insulating film;
Etching the interlayer insulating film between the gate electrodes using the second insulating film as an etching stop film, and opening a contact hole in a self-aligning manner;
Removing the etching stop film at the bottom of the contact hole. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the step of removing the surface of the sidewall is a step of performing isotropic etching on the sidewall. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the sidewall is made of a silicon nitride film. The method of manufacturing a semiconductor device according to claim 14, wherein the sidewall is made of a silicon oxide film. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the etching stop film is made of a silicon nitride film, and the interlayer insulating film is made of a silicon oxide film. 15. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming an LDD region by introducing an impurity having a concentration lower than that of the source / drain region into the substrate using the gate electrode as a mask. The step of forming the side wall is a step of forming a first insulating film on the entire surface and performing anisotropic etching so that the first insulating film remains only on the side wall of the gate electrode. 14. A method for manufacturing a semiconductor device according to 14. Forming a conductor layer on the substrate;
Forming an offset insulating film on the conductor layer;
Processing the conductor layer and the offset insulating film into a predetermined pattern to form a gate electrode;
Forming a sidewall made of a first insulating film on the sidewall of the gate electrode;
Using the sidewall as a mask, introducing impurities into the substrate, and forming source / drain regions;
Forming a refractory metal layer on the entire surface;
Performing a heat treatment to form a refractory metal silicide on the surface of the source / drain region;
Removing the unreacted refractory metal layer;
Removing the surface of the sidewall and exposing at least a portion of the substrate covered by the sidewall;
Forming a second insulating film on at least the gate electrode and the source / drain regions;
Forming an interlayer insulating film on the second insulating film;
Etching the interlayer insulating film between the gate electrodes using the second insulating film as an etching stop film, and opening a contact hole in a self-aligning manner;
Removing the etching stop film at the bottom of the contact hole. The method of manufacturing a semiconductor device according to claim 21, wherein the step of removing the surface of the sidewall is a step of performing isotropic etching on the sidewall. The method of manufacturing a semiconductor device according to claim 21, wherein the refractory metal layer contains cobalt, titanium, or nickel. The method of manufacturing a semiconductor device according to claim 21, wherein the sidewall is made of a silicon nitride film. The method of manufacturing a semiconductor device according to claim 21, wherein the sidewall is made of a silicon oxide film. The method of manufacturing a semiconductor device according to claim 21, wherein the etching stop film is made of a silicon nitride film, and the interlayer insulating film is made of a silicon oxide film. 23. The method of manufacturing a semiconductor device according to claim 21, further comprising a step of forming an LDD region by introducing an impurity having a concentration lower than that of the source / drain region into the substrate using the gate electrode as a mask. The step of forming the side wall is a step of forming a first insulating film on the entire surface and performing anisotropic etching so that the first insulating film remains only on the side wall of the gate electrode. 21. A method of manufacturing a semiconductor device according to 21.

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