JP2004281504A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device capable of preventing the occurrence of a phenomenon (hump characteristics) in which a difference is generated in sub-threshold characteristics by removing a parasitic transistor caused by shapes of a border between an STI and a element region, accompanied by micro-processing and to provide a manufacturing method thereof. <P>SOLUTION: An STI 12 which is an element insulation region by trench isolation is formed on a silicon semiconductor substrate 11. For example, a silicon oxide film is embedded in the STI 12. A gate insulating film extending to an element region 13 surrounded by the STI 12, e.g. a gate oxide film 14, and a gate electrode 15 containing polycrystalline silicon are provided on the substrate 11. In this gate oxide film 14, a portion near the border of the STI 12 and the element region 13 is surely thicker than the element region 13 on the substrate 11. The thicker portion is caused by selectively embedding the polycrystalline silicon film on the difference near the border and being thermally oxidized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an element isolation technology when configuring a semiconductor integrated circuit, and more particularly to a semiconductor device having an STI (Shallow Trench Isolation) and a method of manufacturing the same in a semiconductor integrated circuit requiring miniaturization.
[0002]
[Prior art]
In order to increase the degree of integration of semiconductor integrated circuits, the method of separating elements formed on a semiconductor substrate from each other has shifted from LOCOS isolation (selective oxidation isolation) to trench isolation (trench isolation). ing. In the trench isolation, a shallow trench isolation capable of coping with a micro MOS device is also referred to as STI (Shallow Trench Isolation), and a trench (trench) is formed on a semiconductor substrate other than a device formation region, and the inside of the trench is formed. The device is filled with an insulator, particularly a silicon oxide film, to achieve isolation between elements. Compared to the LOCOS separation method, a separation distance can be obtained deeper in the substrate. For this reason, the separation width can be significantly reduced.
[0003]
3A and 3B are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device having STI in the order of steps.
As shown in FIG. 3A, an oxide film and a silicon nitride film (not shown) are formed on the silicon semiconductor substrate 31, and a mask is applied to the element region through a photolithography process. Thereafter, a trench 32 having a predetermined depth is formed in the element isolation region by anisotropic etching. Next, after an oxidation step for rounding the end of the element region and the bottom of the trench, an oxide film 33 sufficient to fill the trench 32 is formed by a CVD (chemical vapor deposition) method. After that, the oxide film 33 is planarized and removed using a CMP (chemical mechanical polishing) technique until the silicon nitride film mask (not shown) is exposed. After removing the silicon nitride film mask with a chemical solution (hot phosphoric acid or the like), a pre-oxide film 34 is formed by, for example, wet oxidation through chemical solution cleaning (hydrofluoric acid-based cleaning). After the pre-oxide film 34 is formed, a predetermined mask is formed by a photolithography process, and ion implantation for a well, a channel, and the like is performed a predetermined number of times.
[0004]
Thereafter, as shown in FIG. 3B, a gate insulating film (oxide film) 35 is formed after removing the pre-oxide film 34. Next, a gate electrode member, for example, a polysilicon layer is formed, and a gate electrode 36 having a predetermined pattern is formed. Thereafter, although not shown, a structure as a MOS transistor element such as formation of an impurity diffusion region is realized.
[0005]
[Problems to be solved by the invention]
The gate insulating film 35 above the boundary 37 between the STI portion of the oxide film 33 and the channel region below the gate electrode 36 has an insufficient thickness. This is because a step DP occurs due to the removal of the silicon nitride film mask by the above-described chemical solution and the cleaning of the chemical solution before the formation of the gate insulating film. As a result, in the MOS transistor element, transistors having different characteristics become parasitic. That is, a phenomenon (a hump characteristic) in which a step occurs in the sub-threshold characteristic of the MOS transistor element occurs. As a result, the threshold value fluctuates. In addition, it also causes insulation failure and long-term reliability failure. Such problems become more apparent as design rules become smaller.
[0006]
The present invention has been made in view of the above circumstances, and eliminates a parasitic transistor relating to the shape of the boundary between the STI and the element region due to microfabrication, and a phenomenon in which a sub-threshold characteristic has a step (a hump characteristic). It is an object of the present invention to provide a highly-reliable semiconductor device which prevents the occurrence of) and a method of manufacturing the same.
[0007]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a semiconductor substrate having an element isolation region formed by trench element isolation, a gate insulating film provided near the boundary between the element isolation region and the element region on the semiconductor substrate thicker than the element region, A gate electrode on the gate insulating film; and an impurity diffusion region formed on the semiconductor substrate with the gate electrode interposed therebetween.
[0008]
According to the semiconductor device of the present invention as described above, the gate insulating film is provided on the semiconductor substrate near the boundary between the element isolation region and the element region, thicker than the element region. As a result, there is no thin gate insulating film portion that adversely affects the transistor characteristics.
[0009]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove so as to surround an element region in a semiconductor substrate; a step of forming an insulating film on the entire surface of the semiconductor substrate so as to fill the groove; On the other hand, by performing a first planarization process, a step of forming an element isolation region while leaving the insulating film mainly in the groove, a cleaning step including a plurality of chemical solutions, and the element region for the cleaning step Forming a film containing silicon as a main component on the entire surface of the semiconductor substrate so as to fill a step generated near a boundary between the device isolation region and a second flattening process for the film containing silicon as a main component. By leaving a film containing silicon as a main component inside a step mainly generated near the boundary between the element region and the element isolation region, and a step of thermally oxidizing the semiconductor substrate, Characterized by comprising.
[0010]
According to the method of manufacturing a semiconductor device according to the present invention as described above, a step is generated near the boundary between the element region and the element isolation region due to the cleaning process including a plurality of chemical treatments. This step is filled with a film containing silicon as a main component, flattened again, and thermally oxidized. Thus, the insulating film near the boundary between the element region and the element isolation region does not become thin. As a result, the gate insulating film does not become thin near the boundary between the element region and the element isolation region. Therefore, there is no thin gate insulating film that adversely affects the transistor characteristics.
[0011]
As a more preferred embodiment of the method for manufacturing a semiconductor device, at least one of the following features is included.
The method is characterized in that a CMP (Chemical Mechanical Polishing) technique is used as the first and second planarization processing techniques.
Before the step of forming the groove, a mask member for protecting the surface of the element region is formed, and after the first planarization step, the mask member is removed by a cleaning step including the plurality of chemical solutions. It is characterized by being performed.
The step of forming the film containing silicon as a main component includes a step of forming a film made of polycrystalline silicon.
The step of forming the film containing silicon as a main component includes a step of forming a film made of amorphous silicon.
The step of thermally oxidizing the semiconductor substrate mainly includes completely oxidizing the silicon-based film formed so as to fill the inside of a step generated near the boundary between the element region and the element isolation region to a silicon oxide film. It is characterized by doing.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
FIGS. 1A and 1B are a plan view and a BB cross-sectional view of a semiconductor device according to an embodiment of the present invention, respectively, showing one of the MOS transistors. An element isolation region by trench element isolation, that is, an STI portion 12 is formed in a silicon semiconductor substrate 11. The STI section 12 is embedded with, for example, a silicon oxide film. On the substrate 11, a gate insulating film, for example, a gate oxide film 14 extending over the element region 13 surrounded by the STI portion 12, and a gate electrode 15 containing polycrystalline silicon are provided. The thickness of the gate oxide film 14 near the boundary between the STI portion 12 and the element region 13 is surely thicker than that on the element region 13 (14B).
[0013]
Source / drain diffusion regions 15 are formed on substrate 11 with gate electrode 15 therebetween. Since the source / drain diffusion region 16 has an LDD (Lightly Doped Drain) structure, a structure in which a spacer, that is, an insulating sidewall SW of the gate electrode 15 may be provided. Further, when the upper portion of the gate electrode 15 is silicided, such a sidewall SW is indispensable for a self-aligned silicide structure, a so-called salicide structure, in order to prevent a short circuit.
[0014]
According to the above embodiment, with respect to the gate oxide film 14, the vicinity of the boundary between the STI portion 12 and the element region 13 on the substrate 11 is surely thicker than on the element region 13 (14B). As a result, there is no thin gate insulating film portion that adversely affects the transistor characteristics. As a result, it is possible to prevent a phenomenon (a hump characteristic) in which a step is formed in the sub-threshold characteristic of the MOS transistor element. That is, high reliability can be obtained without incurring threshold variation, poor insulation resistance, or long-term reliability failure. Hereinafter, the manufacturing method will be described.
[0015]
FIGS. 2A to 2F are cross-sectional views showing a main part of a method of manufacturing a semiconductor device having an STI according to an embodiment of the present invention in the order of steps. It is for explanation. 1 (b) are denoted by the same reference numerals.
As shown in FIG. 2A, an oxide film and a silicon nitride film (not shown) are formed on the silicon semiconductor substrate 11, and a mask is applied to the element region through a photolithography process. Thereafter, a trench 22 having a predetermined depth is formed in the element isolation region by anisotropic etching. Next, after an oxidation process for rounding the end of the element region 13 and the bottom of the trench 22, an oxide film 23 only to fill the trench 22 is formed by a CVD (chemical vapor deposition) method. A technique using high-density plasma CVD can also be used. Thereafter, the oxide film 23 is flattened and removed using a CMP (chemical mechanical polishing) technique until the silicon nitride film mask (not shown) is exposed. After removing the silicon nitride film mask with a chemical solution (hot phosphoric acid or the like), the STI portion 12 is formed through chemical solution cleaning (hydrofluoric acid-based cleaning). On the element region 13, a base oxide film of the mask and an oxide film 231 in the oxidation step remain. Then, a step 25 occurs near the boundary between the element region 13 and the STI portion 12.
[0016]
Next, as shown in FIG. 2B, a polycrystalline silicon film 24 is formed on the entire surface of the substrate 11 by using the CVD method. This ensures that the step 25 is filled with polycrystalline silicon.
Next, as shown in FIGS. 2C and 2D, the polycrystalline silicon film 24 is planarized and removed by using the CMP technique. The CMP is performed with time control under the condition that a high etching rate can be obtained to some extent (FIG. 2C). Thereafter, the CMP is performed under the condition that the selectivity to the oxide film can be obtained as much as possible even when the etching rate is low. Then, the operation is stopped when the oxide film 23 of the STI portion 12 is exposed (FIG. 2D). Thus, the polycrystalline silicon film 24 is buried only in the step (depot) 25.
[0017]
Next, as shown in FIG. 2E, the entire substrate is thermally oxidized. As the oxidation conditions, heat treatment at an appropriate temperature of 650 ° C. or more is performed in an atmosphere containing oxygen or water vapor. Thereby, the polycrystalline silicon film 24 also becomes a thermal oxide film. As an example of implementation, it is assumed that the depth and width of the step (depot) 25 are about 20 nm, and the polycrystalline silicon 24 is formed so as to fill the step appropriately. As a condition for completely oxidizing this, a heat treatment at 900 ° C. for 30 minutes in an oxidizing atmosphere in which oxygen, water vapor and nitrogen are mixed at almost the same ratio can be mentioned. According to such a heat treatment, in an element region covered with a thin oxide film, polycrystalline silicon buried in a step can be oxidized while suppressing an increase in an oxide film. As a result, the step (depot) 25 is filled with the silicon oxide film, and the thickness of the oxide film near the boundary between the element region and the element isolation region can be made larger than that inside the element region. The oxide film formed through such a process is referred to as a pre-oxide film 26. That is, the step (depot) 25 is reduced, and the vicinity of the boundary between the STI portion 12 and the element region 13 is surely thicker than the element region 13 (26B). After that, a predetermined mask may be formed in a photolithography process, and ion implantation for a well, a channel, and the like may be performed a predetermined number of times.
[0018]
Next, as shown in FIG. 2 (f), a gate oxide film 14 is formed after a cleaning step involving isotropic etchback of the substrate 11, for example, a hydrofluoric acid-based cleaning. In the vicinity of the boundary between the STI section 12 and the element region 13, the gate oxide film 14 is surely thicker than the element region 13 (14B). Next, the gate electrode 15 containing polycrystalline silicon is formed by patterning. Thereafter, although not shown, source / drain diffusion regions are formed by impurity ion implantation accompanying formation of a spacer (sidewall SW) and a photolithography step. After the formation process of the sidewall SW, it is possible to realize a self-aligned silicide (salicide) structure by sputtering and heat-treating a metal member selected from a high melting point metal such as Co, Ti, and Mo. is there.
[0019]
According to the method of the above embodiment, polycrystalline silicon is formed at the step (depot) 25 near the boundary between the element region 13 and the STI portion 12, and the polycrystalline silicon is thermally oxidized to form the portion having the step (depot) 25. Can surely form a thick oxide film (14B). Therefore, the insulating film (oxide film) near the boundary between the element region and the element isolation region does not become thin even after a plurality of subsequent cleaning steps using a chemical solution. As a result, the gate insulating film does not become thin near the boundary between the element region and the element isolation region.
[0020]
The use of the method of the above embodiment also has an advantage that an oxidation step with poor controllability, such as rounding the end of the element region 13 and the bottom of the trench 22, can be shortened as compared with the conventional method. By utilizing the method of the above embodiment, there is no thin gate insulating film portion that adversely affects the transistor characteristics. As a result, it is possible to prevent a phenomenon (a hump characteristic) in which a step is formed in the sub-threshold characteristic of the MOS transistor element. That is, high reliability can be obtained without incurring threshold variation, poor insulation resistance, or long-term reliability failure.
[0021]
As described above, according to the present invention, the concern about the parasitic transistor as described in the conventional example is solved. Also, it greatly contributes to the reduction of the error between the actual transistor size (particularly the gate width) and the design value. As a result, a highly reliable semiconductor device that eliminates a parasitic transistor relating to the shape of the boundary between the STI and the element region due to microfabrication and prevents the occurrence of a phenomenon in which a sub-threshold characteristic has a step (a hump characteristic) is generated. And a method for producing the same.
[Brief description of the drawings]
FIG. 1 is a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a method of manufacturing a semiconductor device having STI according to one embodiment.
FIG. 3 is a sectional view of a conventional method for manufacturing a semiconductor device having STI.
[Explanation of symbols]
11, 31 silicon semiconductor substrate, 12 STI portion, 13 element region, 14, 34 gate oxide film, 15 gate electrode, 16 source / drain diffusion region, 22 trench, 23, 231 oxide film, 24: polycrystalline silicon film, 25: step (depot), 26, 33: pre-oxide film, SW: sidewall.

Claims (7)

A semiconductor substrate having an element isolation region by trench element isolation,
A gate insulating film provided near the boundary between the element isolation region and the element region on the semiconductor substrate so as to be thicker than the element region;
A gate electrode on the gate insulating film;
An impurity diffusion region formed on the semiconductor substrate with the gate electrode interposed therebetween;
A semiconductor device comprising: Forming a groove so as to surround the element region in the semiconductor substrate;
Forming an insulating film on the entire surface of the semiconductor substrate so as to fill the groove,
Performing a first planarization process on the insulating film to form an element isolation region while leaving the insulating film mainly in the trench;
A cleaning process comprising a plurality of chemical treatments;
Forming a film mainly composed of silicon on the entire surface of the semiconductor substrate so as to fill a step generated near a boundary between the element region and the element isolation region for the cleaning step;
By performing a second planarization process on the film containing silicon as a main component, the film containing silicon as a main component is mainly left inside a step generated near a boundary between the element region and the element isolation region. Process and
Thermally oxidizing the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 2, wherein a CMP (Chemical Mechanical Polishing) technique is used as the first and second planarization processes. Before the step of forming the groove, a mask member for protecting the surface of the element region is formed, and after the first planarization step, the mask member is removed by a cleaning step including the plurality of chemical solutions. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the method is performed. 5. The method according to claim 2, wherein the step of forming the film containing silicon as a main component includes the step of forming a film made of polycrystalline silicon. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the film containing silicon as a main component includes a step of forming a film made of amorphous silicon. The step of thermally oxidizing the semiconductor substrate mainly includes completely oxidizing the silicon-based film formed so as to fill the inside of a step generated near the boundary between the element region and the element isolation region to a silicon oxide film. The method for manufacturing a semiconductor device according to claim 2, wherein the method comprises:

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