JP2012182488A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress current leak in an element isolation region.SOLUTION: In a second region 52 in a polycrystalline silicon film 50 for a resistance element 5, ion implantation with dopant is performed. in a second region 62 in a polycrystalline film 60 for a resistance element 6, the ion implantation with nitrogen or the like is performed. The second regions 52 and 62 have crystal defect density higher than that of first regions 51 and 61. In a polycrystalline film 70 for a resistance element 7, the crystal defect density is high in the vicinity of a silicide film 73. A polycrystalline film 80 for a resistance element 8 contacts a substrate 2 through the silicide film in an opening of an insulation film 3 for element isolation. The crystal defect density on a surface of substrate 2S is higher in the vicinity of the silicide film than in the periphery of the silicide film.

Description

  The present invention relates to a semiconductor device capable of reducing current leakage in an element isolation region and a method for manufacturing such a semiconductor device.

  In a semiconductor device, basic elements such as transistors, capacitors, and resistors are connected by wiring. Note that the electrode of the transistor may be used as a wiring as it is. In general, metals such as aluminum and copper, and polycrystalline silicon are frequently used as electrodes and wires of transistors and capacitors. At this time, in the case where a polycrystalline silicon film is used for the electrodes and wirings, the electrical resistance can be reduced by forming a silicide film or a metal film on the entire polycrystalline silicon film.

  A semiconductor film such as a polycrystalline silicon film is also used as a resistance element. At this time, the resistance value of the resistance element is inversely proportional to the cross-sectional area of the polycrystalline silicon film and proportional to the length and impurity (dopant) concentration. For example, when the resistance is increased, the cross-sectional area of the polycrystalline silicon film is made smaller or the length is made longer. Furthermore, the resistance can also be increased by lowering the impurity concentration of the polycrystalline silicon film or using it without introducing impurities into the polycrystalline silicon film.

  A low-resistance polycrystalline silicon film used as an electrode or wiring and a high-resistance polycrystalline silicon film used as a resistance element can be formed from a single polycrystalline silicon film. Here, a conventional method of forming the semiconductor device 1P will be described with reference to FIG.

  First, an element isolation insulating film 3P made of a silicon oxide film is formed using a LOCOS (Local Oxidation of Silicon) method or the like to partition the silicon substrate 2P into an active region and an element isolation region. Thereafter, wells and element isolation implantation regions are formed by ion implantation or the like.

  Next, a gate oxide film is formed in a formation region of a transistor (not shown). Thereafter, an undoped (intrinsic) polycrystalline silicon film is deposited on the entire surface of the substrate 2P with a thickness of 50 nm to 250 nm by LPCVD (low pressure CVD), and the polycrystalline silicon film is patterned by photolithography. To do. At this time, a portion of the polycrystalline silicon film patterned on the element isolation film 3P becomes the resistance element 5P. The resistance element 5P is covered with a resist, an oxide film or the like to protect it from being affected by the transistor manufacturing process.

  Of the patterned polycrystalline silicon film, the portion in the transistor arrangement region becomes the gate electrode of the transistor together with the silicide film. Specifically, a silicide film is formed by forming a metal film of titanium, cobalt, nickel, tungsten, or the like on the exposed surface so as to be in contact with the polycrystalline silicon film and causing a silicidation reaction. Alternatively, a tungsten silicide film or the like is directly deposited so as to be in contact with the polycrystalline silicon film. At this time, the metal film and the silicide film for forming the gate / silicide film are also formed on a resist or the like covering the resistance element 5P.

  Thereafter, by forming a protective film (not shown), metal wiring, or the like, the semiconductor device 1P is completed.

  Note that amorphous (amorphous) silicon may be used instead of polycrystalline silicon.

  As described above, the resistance element 5P is covered with a resist or an oxide film while various processes are performed on the transistor arrangement region. In addition, when processing the transistor arrangement region, the metal film or the silicide film for forming a gate / silicide film is formed on the resist or the like.

  By the way, the diffusion coefficient of metal atoms in a resist or an oxide film shows the same tendency as the diffusion coefficient in silicon (see FIG. 15), and is larger than boron, arsenic, or the like. For this reason, the metal atoms in the gate / silicide film or the metal atoms in the silicide film may enter the resist or the like.

  Metal atoms entering the resist or the like diffuse into the substrate 2P through the polycrystalline silicon film 5P and / or the element isolation insulating film 3P. As a result, as shown in FIG. 16, the metal atoms 11P that have entered the substrate 2P cause a leakage current 12P below the element isolation insulating film 3P, that is, in the element isolation region.

  A metal atom in a metal film (for example, tungsten or aluminum) as a metal gate or a metal wiring (for example, aluminum or copper) can also be the metal atom 11P.

  The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device capable of reducing current leakage in an element isolation region and a method for manufacturing such a semiconductor device.

  A semiconductor device according to one embodiment of the present invention includes an active region disposed in a semiconductor surface layer of a semiconductor substrate, and an element isolation film formed of an insulating film formed on the semiconductor surface layer of the semiconductor substrate so as to partition the active region. And a resistance element made of a semiconductor film disposed on the element isolation film, wherein the resistance element has a first region in a plan view and a second region having a higher density of crystal defects than in the first region. The second region is disposed on the insulating film.

  Further, a method for manufacturing a semiconductor device according to another aspect of the present invention includes: (a) a step of forming an element isolation film made of an insulating film so as to partition an active region on a surface layer of a semiconductor substrate; and (b) Forming a resistance element made of a semiconductor film on the element isolation film, and the step (b) includes (b) -1) crystal defects in a partial region of the semiconductor film in plan view. A step of increasing the density, wherein the partial region of the semiconductor film is a portion of the semiconductor film disposed on the insulating film.

  According to the above aspect, since crystal defects in the second region have a gettering effect, leakage current under the insulating film can be reduced.

  In addition, according to the another aspect, since the crystal defects generated in the step (b) -1) have a gettering effect, a semiconductor device with reduced leakage current under the insulating film can be manufactured. .

1 is a perspective view for explaining a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. It is a perspective view for demonstrating the conventional semiconductor device. It is a graph for demonstrating the diffusion coefficient in silicon | silicone. It is a perspective view for demonstrating the current leak in the conventional semiconductor device.

<Embodiment 1>
FIG. 1 is a perspective view for explaining a semiconductor device 1 according to the first embodiment. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate (hereinafter also simply referred to as “substrate”) 2, a MOSFET 90, an element isolation insulating film (or insulating film) 3, and resistive elements 5, 6, 7, 8,5P. Although illustration in FIG. 1 is omitted, the semiconductor device 1 includes other transistors, capacitors, and the like.

  Specifically, the substrate 2 is made of, for example, p-type silicon. An element isolation insulating film 3 is formed on a surface 2S (hereinafter also referred to as “substrate surface”) 2S of the substrate 2, and the element isolation insulating film 3 partitions the substrate 2 into an active region and an element isolation region. An element isolation implantation region is formed in the substrate surface 2S under the element isolation insulating film 3.

  In the active region, the gate insulating film 92 of the MOSFET 90, the polycrystalline silicon film 93, and the silicide film 94 are formed in this order on the substrate surface 2S. Note that the structure composed of the polycrystalline silicon film 93 and the silicide film 94 corresponds to the gate electrode 95 of the MOSFET 90. A source / drain region 91 of the MOSFET 90 is formed in the substrate surface 2S through a portion of the substrate 2 below the gate insulating film 92, that is, a channel region.

  Next, the resistance elements 5 to 8 and 5P will be described. Each of the resistance elements 5 to 8 and 5P is connected to the gate electrode 95 and the source / drain region 91 of the MOSFET 90 at a portion not shown, or is connected to a transistor or a capacitor not shown. The resistance element 5P is a resistance element similar to the conventional one.

  FIG. 2 is a cross-sectional view for explaining the resistance element 5. FIG. 2 corresponds to a part of a longitudinal section taken along line AA in FIG. The resistive element 5 is formed on the element isolation insulating film 3 (more specifically, formed on the element isolation insulating film 3 so as to face the substrate surface 2S and be in contact with the element isolation insulating film 3). A film (or semiconductor film) 50 is formed. The polycrystalline silicon film 50 is formed in a band shape having a thickness of 50 nm to 250 nm, for example.

In particular, the polycrystalline silicon film 50 of the resistance element 5 includes a first region 51 and a second region 52 having a higher impurity (or dopant) concentration than the first region 51 in a plan view corresponding to the plan view of the substrate surface 2S. Contains. The second region 52 includes, for example, arsenic at a concentration of 5 × 10 ²⁰ / cm ³ . Note that the dopant in the second region 52 may have any conductivity type of P-type / N-type. The impurities in the second region 52 act as crystal defect inducing particles that induce crystal defects 4, and the density of the crystal defects 4 is higher in the second region 52 than in the first region 51 due to the difference in impurity concentration.

  The polycrystalline silicon film 50 includes at least one second region 52 (two cases are shown in FIG. 1), and the second region 52 is, for example, an element in the surface of the polycrystalline silicon film 50. It is formed in a surface far from the isolation insulating film 3. 1 and 2, the second region 52 may be formed so as to be in contact with the element isolation insulating film 3, that is, entirely in the thickness direction, or a part of the band-like width direction. (That is, it may not be full width).

  Next, FIG. 3 shows a cross-sectional view for explaining the resistance element 6. FIG. 3 corresponds to a part of a longitudinal section taken along line BB in FIG. The resistive element 6 is composed of a polycrystalline silicon film 60 similarly to the polycrystalline silicon film 50 of the resistive element 5, and the polycrystalline silicon film 60 of the resistive element 6 is similar to the polycrystalline silicon film 50 in the first region 61 and at least One second region 62 is included.

In particular, the second region 62 of the resistive element 6 is replaced with a dopant included in the second region 52 of the resistive element 5, and particles (elements) that are not easily involved in the conductivity type of the polycrystalline silicon film 60, such as nitrogen, fluorine, At least one kind of particles such as argon and silicon (or semiconductor element) is included as crystal defect inducing particles, and the density of crystal defects 4 is higher in the second region 62 than in the first region 61. The concentration of nitrogen or the like in the second region 62 is, for example, 1 × 10 ^{15 to} 3 × 10 ¹⁵ / cm ³ .

  Next, FIG. 4 shows a cross-sectional view for explaining the structure in the vicinity of the resistance element 7. 4 corresponds to a part of a longitudinal section taken along the line CC in FIG. The resistive element 7 includes a polycrystalline silicon film 70 as in the polycrystalline silicon film 50 of the resistive element 5, and the polycrystalline silicon film 70 of the resistive element 7 includes the first region 71 and at least at least the polycrystalline silicon film 50. One second region 72 is included. The second region 72 has a higher density of crystal defects 4 than the first region 71.

  Regarding the resistance element 7, the semiconductor device 1 further includes a silicide film 73 made of, for example, titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, or the like. The silicide film 73 is disposed so as to face the element isolation insulating film 3 through the polycrystalline silicon film 70 and to be in contact with the second region 72 of the polycrystalline silicon film 70. In other words, the second region 72 of the resistance element 7 is provided between the silicide film 73 and the element isolation insulating film 3.

  Next, FIG. 5 shows a cross-sectional view for explaining the structure in the vicinity of the resistance element 8. FIG. 5 corresponds to a part of a longitudinal section taken along line DD in FIG. In the semiconductor device 1, at least one opening 3K is formed in the element isolation insulating film 3, and the opening 3K penetrates the element isolation insulating film 3 in the thickness direction. An n-type impurity region 22 (having a conductivity type opposite to that of the p-type substrate 2) is formed in the substrate surface 2S located in the opening 3K (in plan view of the substrate surface 2S).

  With respect to the resistance element 8, the semiconductor device 1 further includes a silicide film (or compound film) 23 in contact with the impurity region 22, in other words, in contact with the substrate surface 2S in the opening 3K. Various silicide materials can be applied to the silicide film 23 in the same manner as the silicide film 73 described above.

  In particular, the impurity region 22, more specifically, the region near the silicide film 23 on the substrate surface 2 </ b> S in the opening 3 </ b> K has a higher density of crystal defects 4 than the periphery thereof, and the second region 52 of the resistance element 7 described above. Corresponding to

  A polycrystalline silicon film (or a semiconductor film) 80 constituting the resistance element 8 is formed in contact with the silicide film 23 and the element isolation insulating film 3. A portion of the polycrystalline silicon film 80 that contacts the element isolation insulating film 3 faces the substrate surface 2S through the element isolation insulating film 3. Similar to the polycrystalline silicon film 50 described above, the polycrystalline silicon film 80 is formed in a band shape having a thickness of 50 nm to 250 nm, for example.

  At this time, the resistive element 8 and the substrate 2 can be electrically separated by the impurity region 22. The silicide film 23 functions as a barrier metal and can prevent the polycrystalline silicon film 80 (the silicon atoms) from entering the substrate 2.

  At least one configuration including the opening 3K, the silicide film 23, and the impurity region 22 of the element isolation insulating film 3 is provided for one resistance element 8, in other words, for one polycrystalline silicon film 80. . 1 and 5, the width of the band-like polycrystalline silicon 80 may be formed wider than the opening 3K of the element isolation insulating film 3.

  The resistance values of the resistance elements 5, 6, 7, and 8 can be adjusted and set according to the impurity concentration, cross-sectional area, length, and the like of the polycrystalline silicon films 50, 60, 70, and 80.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to cross-sectional views of FIGS. 6 to 13 in addition to FIGS.

  First, the substrate 2 is prepared, and the element isolation insulating film 3 in contact with the substrate surface 2S is formed by, for example, a LOCOS (Local Oxidation of Silicon) method. At this time, an opening 3K for the resistance element 8 is provided to form the element isolation insulating film 3 (see FIG. 6). Note that the element isolation insulating film 3 may be formed by a trench element isolation method. In such a case, the element isolation insulating film 3 is filled in a trench formed in the substrate 2 (therefore, formed on the substrate surface 2S). ) After the element isolation insulating film 3 is formed, a well and an element isolation implantation region are formed by an ion implantation method or the like.

  Thereafter, as shown in FIG. 7, a resist 122A is formed on the element isolation insulating film 3 by opening the opening 3K. Then, for example, arsenic 22A is ion-implanted using the resist 122A as a mask to form an impurity region 22 in the substrate surface 2S in the opening 3K. Then, the resist 122A is removed. The ion implantation process for forming the impurity region 22 can also serve as a channel doping process, for example.

  Next, as shown in FIG. 8, a metal film 23 </ b> A such as titanium is formed so as to cover the impurity region 22. Subsequently, a silicidation reaction (or alloying reaction) is caused in the metal film 23A and the impurity region 22 to form a silicide film. In general, the silicidation reaction is performed at a temperature lower than that of the heat treatment for activating the dopant, for example. Thereafter, the unreacted portion of the metal film 23A is removed to obtain the silicide film 23 as shown in FIG. Crystal defects 4 are formed in the impurity region 22 during the silicidation reaction, more specifically in the region near the silicide film 23 on the substrate surface 2S in the opening 3K.

  Thereafter, an oxide film for the gate insulating film 92 of the MOSFET 90 (see FIG. 1) is formed.

  Next, as shown in FIG. 10, an intrinsic polycrystalline silicon film 5A that is not doped is deposited to a thickness of 50 nm to 250 nm by, for example, LPCVD (low pressure CVD). At this time, the polycrystalline silicon film 5A is formed over the substrate surface 2S so as to cover the element isolation insulating film 3 and the oxide film for the gate insulating film 92. Then, the polycrystalline silicon film 5A is patterned by a photoengraving method, so that the polycrystalline silicon films 50, 60, 70, 80, the polycrystalline silicon film for the resistance element 5P, and the polycrystalline silicon film for the gate electrode 95 (later polycrystalline silicon film). A crystal silicon film 93 is formed (see FIG. 1).

  Thereafter, silicide regions 73 for the second regions 52 and 62 of the resistance elements 5 and 6 and the resistance element 7 are formed.

Specifically, the second region 52 of the resistance element 5 is formed as follows. As shown in FIG. 11, a resist 152 </ b> A is formed on the polycrystalline silicon film 50 by opening a part for forming the second region 52. Then, for example, arsenic (or crystal defect inducing particles) 52A is ion-implanted into the polycrystalline silicon film 50 using the resist 152A as a mask. Arsenic 52A is ion-implanted, for example, with an acceleration energy of 20 keV or more and a dose of 3 × 10 ¹⁵ / cm ² or more. By this ion implantation, crystal defects 4 are formed in the second region 52 (crystal defect density increases).

  At this time, the ion implantation process of the second region 52 of the resistance element 5 can be performed simultaneously with the ion implantation process for forming the source / drain region 91 of the MOSFET 90. In the ion implantation process for the source / drain region 91, ion implantation for the polycrystalline silicon film 93 of the gate electrode 95 may be performed simultaneously.

The second region 62 of the resistance element 6 is formed as follows. As shown in FIG. 12, a resist 162 </ b> A is formed on the polycrystalline silicon film 60 by opening a part for forming the second region 62. Then, for example, nitrogen (or crystal defect inducing particles) 62A is ion-implanted into the polycrystalline silicon film 60 using the resist 162A as a mask. Nitrogen 62A is ion-implanted, for example, with an acceleration energy of 4 keV or higher and a dose of 2 × 10 ¹⁵ / cm ² or higher. By this ion implantation, crystal defects 4 are formed in the second region 62 (the crystal defect density increases).

  Instead of nitrogen 62A, for example, fluorine may be implanted with an acceleration energy of 5 keV or more, argon may be implanted with an acceleration energy of 2 keV or more, or silicon may be implanted with an acceleration energy of 7 keV or more. A plurality of types of ion species may be implanted. At this time, the larger the atomic weight (the size of the atom) of the ion species, the more crystal defects 4 can be generated at the same dose.

  The silicide film 73 related to the resistance element 7 is formed as follows. As shown in FIG. 13, a resist 173A is formed on the polycrystalline silicon film 70 by opening a portion where the silicide film 73 is to be formed. Then, a metal film 73A such as titanium, cobalt, nickel, tungsten, or the like is formed so as to cover the polycrystalline silicon film 70 exposed in the opening of the resist 173A. Subsequently, a silicidation reaction (or alloying reaction) is caused in the metal film 73A and the polycrystalline silicon film 70 to form a silicide film. Thereafter, unreacted portions of the metal film 73A are removed to obtain a silicide film 73 as shown in FIG. Crystal defects 4 are formed in the second region 72 of the polycrystalline silicon film 70 during the silicidation reaction (the crystal defect density increases). At this time, the formation process of the silicide film 73 can be performed simultaneously with the process for forming the silicide film 94 of the MOSFET 90.

  After the semiconductor device 1 in the state shown in FIG. 1 is obtained, a protective film and metal wiring are formed by a general process.

  According to the semiconductor device 1, the metal atoms 11P (see FIG. 16) in which the crystal defects 4 in the second regions 52, 62, 72 and the impurity region 22 cause the leakage current 12P or the metal atoms that can become the metal atoms 11P are gettered. Since the ringing is performed, the leakage current under the element isolation insulating film 3 can be reduced. Moreover, according to the manufacturing method described above, such a semiconductor device 1 can be manufactured.

At this time, by setting the density of the crystal defects 4 in the second regions 52, 62, 72 and the impurity region 22 to the order of 10 ¹⁵ / cm ³ or more, the gettering effect is more reliably exhibited.

  Further, in the polycrystalline silicon film 50, the interval between the plurality of second regions 52 is shorter than the diffusion length of the metal atom 11P (see FIG. 16) that causes the leakage current 12P (according to the experiment by the inventor, for example, 10 μm or less). It is more preferable to set. According to this interval setting, the metal atoms 11P can be gettered more reliably. Such an interval setting is also applied to each of the second regions 62 and 72 of the polycrystalline silicon films 60 and 70 and the impurity region 22 in the substrate 2.

  Furthermore, the above-described interval setting is also applicable to the adjacent resistance elements 5-8. For example, it is more preferable to set the distance between the second region 52 of the resistive element 5 and the second region 62 of the resistive element 6 to 10 μm or less. For example, when the interval between the second region 52 of the resistive element 5 and the second region 72 of the resistive element 7 is set to 10 μm or less, the second region 62 is not provided between the second regions 52 and 72. It doesn't matter. That is, it is not necessary to arrange the second regions 52, 62, 72 and the impurity region 22 (see FIG. 5) in the arrangement direction of the resistance elements 5 to 8 (lateral direction in FIG. 1) as shown in FIG.

  For example, since the low resistance second region 52 of the resistance element 5 is only formed in a part of the polycrystalline silicon film 50, the resistance element 5 is similar to the conventional resistor element 5P having the same shape. A resistance value is obtained.

  The second regions 52, 62, 72 and the impurity region 22 may be combined. For example, the second regions 52 and 62 can be combined by implanting nitrogen or the like into the second region 52. Alternatively, for example, a silicide film 73 may be formed on the second region 52 or 62. Since the silicidation reaction is generally performed at a lower temperature than the heat treatment for activating the dopant as described above, crystal defects are caused by both the second region 52 or 62 and the silicide film 73. 4 can be generated. Alternatively, for example, the second region 52 or 62 or the silicide film 73 may be provided for the polycrystalline silicon film 80 constituting the resistance element 8.

  In the above description, the case where a plurality of types of resistance elements 5 to 8 are formed on one element isolation insulating film 3 has been described. However, one type of resistance element 5 is formed on one element isolation insulating film 3. 6, 7 or 8 may be formed.

  A plurality of resistance elements 50, 60, 70, 80 may be combined to form one resistance element. For example, it is possible to provide both the second region 52 and the silicide film 73 separately for one polycrystalline silicon film.

  It is also possible to use amorphous silicon or another semiconductor material instead of the polycrystalline silicon films 50, 60, 70, 80. The polycrystalline silicon films 50, 60, 70, and 80 may be formed by heat-treating amorphous silicon.

  In addition, the semiconductor device 1 can cope with the progress of future miniaturization by designing in accordance with a general proportional reduction rule.

  Reference Signs List 1 semiconductor device, 2 semiconductor substrate, 2S substrate surface, 3 element isolation insulating film (insulating film), 3K opening, 4 crystal defect, 5, 6, 7, 8 resistance element, 22 impurity region (second region), 23, 73 Silicide film (compound film), 23A, 73A Metal film, 50, 60, 70, 80 Polycrystalline silicon film (semiconductor film), 51, 61, 71 First region, 52, 62, 72 Second region, 52A Arsenic (Crystal defect induced particles), 62A Nitrogen (Crystal defect induced particles).

Claims (10)

An active region disposed on a semiconductor surface of a semiconductor substrate;
An element isolation film formed on a semiconductor surface layer of the semiconductor substrate so as to partition the active region, and comprising an insulating film;
A resistance element made of a semiconductor film disposed on the element isolation film,
The resistance element includes a first region in plan view and a second region having a higher density of crystal defects than in the first region,
The second region is disposed on the insulating film;
Semiconductor device.   2. The semiconductor device according to claim 1, further comprising a compound film disposed in contact with the second region and made of a compound of a material of the semiconductor film and a metal.   3. The semiconductor device according to claim 1, wherein the second region includes crystal defect inducing particles that induce the crystal defect. 4.   4. The semiconductor device according to claim 3, wherein the crystal defect inducing particles include at least one kind of particles of an element that acts as a dopant for the semiconductor film, a semiconductor element, nitrogen, fluorine, and argon. apparatus.   4. The semiconductor device according to claim 3, wherein the crystal defect inducing particles are made of particles that do not participate in a conductivity type of the semiconductor film.   6. The semiconductor device according to claim 5, wherein the crystal defect inducing particles are made of any one of nitrogen, fluorine, argon, and silicon.   3. The semiconductor device according to claim 2, wherein the compound film is not connected to a wiring.   8. The semiconductor device according to claim 1, wherein the semiconductor film includes one of a polycrystalline semiconductor film and an amorphous semiconductor film. 9. (a) forming a device isolation film made of an insulating film so as to partition an active region on a surface layer of a semiconductor substrate;
(b) forming a resistance element made of a semiconductor film on the element isolation film,
The step (b)
(b) -1) increasing the density of crystal defects in a partial region of the semiconductor film in plan view,
The partial region of the semiconductor film is a portion of the semiconductor film that is disposed on the insulating film.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 9,
The step (b) -1)
(b) -1-1) a step of causing an alloying reaction in the vicinity of the partial region of the semiconductor film, or
(b) -1-2) including a step of performing ion implantation on the partial region of the semiconductor film,
A method for manufacturing a semiconductor device.

Images