TWI292604B - - Google Patents

Description

1292604 V. DESCRIPTION OF THE INVENTION (1) The present invention relates to semiconductor integrated circuit technology, and more particularly to an electrostatic discharge protection structure and a method of fabricating the same, and more particularly to an electrostatic discharge protection structure having a metal contact region and a method of fabricating the same . In the application of integrated circuits (ICs), materials such as conductors, semiconductors, and insulating layers have been widely used. Among them, the above materials can be deposited in layers on the wafer to be fabricated by Thin Film Deposition. The surface is formed to form a semiconductor element such as a transistor or a capacitor. However, in a semiconductor device, an electrostatic discharge (ESD) often intrudes from an input/output pad (I/O pad) of a wafer due to contact with an electrostatic body in a dry environment, causing damage to the integrated circuit. In particular, MOS transistors are extremely sensitive to high voltage discharges because they have a thin gate oxide that is easily ruptured. For example, as shown in FIG. 1, semiconductor devices generally have an internal portion. The circuit component region 30 and an input and output pad 1 electrically connected thereto are provided with an electrostatic discharge protection structure 2 两者 between the two to limit the potential and filter the electrostatic discharge to avoid ESD damage. The ESD protection structure 20 generally includes a gold oxide half (M〇s) transistor, a W_S, a PMOS, or a CMOS transistor, as shown in FIG. 2, in the case of a _s transistor, a gate 21 and a source 22 is grounded. Therefore, in normal operation, the S transistor 25 is not turned on, and in the event of electrostatic discharge, the build-in parastic npn bipolar transistor (BJT) is used. The pre-conduction of the component) protects the internal circuit component region 30, wherein the source N+ doped region 22 forms an emitter

1292604 V. INSTRUCTION DESCRIPTION (2) E, the drain N+ doped region 23 forms the collector C, and the P-type germanium substrate 24 forms the base B. Since the emitter base E, B is grounded, when an electrostatic discharge occurs at the output When the pad 10 is inserted, the 'ESD voltage' will trigger the parasitic bipolar transistor 26, causing the NMOS transistor 25 to enter the snapback region due to voltage breakdown, and thereby conduct the ESD current. However, if the NM0S transistor 25, which is an ESD protection component, cannot enter the jumpback region due to voltage collapse in time, or if a large amount of esd current cannot be conducted in time, the electrostatic discharge will directly invade the internal circuit component region. . °

Therefore, the development of an ESD device that can conduct a large amount of ESD current instantaneously becomes a major issue in the semiconductor device technology. Conventional techniques have been applied to implant N-type or P-type ions in a predetermined location within the substrate to complete the ESD protection component. The present invention, however, proposes a novel technique for forming ESD protection by extending a metal contact region to the source/drain interior without the need to implant heterogeneous ions as conventional techniques to complete the ESD protection device. In order to achieve the above object, the present invention provides a method of fabricating an electrostatic discharge protection structure having a metal contact region, first providing a semiconductor substrate having a first conductivity type. Next, a gate structure composed of a gate electrode, a gate conductive layer and a gate spacer layer is formed on the semiconductor substrate. Next, the semiconductor substrate on both sides of the gate structure forms a source/drain having a first conductivity type. Thereafter, the method further includes the steps of forming a metal telluride on the source/drain surface and the surface of the gate structure as a metal telluride gate and a metal telluride source/drain; forming a residual stop layer on the semiconductor substrate 'Remove part of this etch stop layer to expose this metal stone

1292604 V. Description of the invention (3) a source/drain; a dielectric layer is formed on the etch stop layer and the exposed metal halide source/drain; the dielectric layer and the metal halide source/ The poles are formed to extend into the metal contact area opening window of the source/nopole. Finally, a metal layer is deposited in the open window of the metal contact region to form a metal contact region. The present invention also provides an electrostatic discharge protection structure having a metal contact region, comprising: a semiconductor substrate having a first conductivity type; a gate t structure comprising a gate insulating layer, a gate conductive layer, and a metal telluride a gate and gate spacer layer is disposed on the surface of the semiconductor substrate; a source/drain electrode having a second conductivity type, located in a semiconductor substrate on both sides of the gate structure; a metal telluride source/drainage, Located above the source/drain; and a metal contact region formed by a metal layer extending from the upper surface of the semiconductor substrate on both sides of the gate structure into the source/drain. Embodiments: Please refer to Figures 3A to 3G, which show a cross-sectional view of a manufacturing flow of an embodiment of the present invention. First, according to FIG. 3A, the present embodiment is applicable to a semiconductor substrate, such as a silicon semiconductor material, in the form of expitaxial or germanium on the insulating layer (silic〇n insulatoi· And the like, wherein the substrate 100 is a semiconductor material, and the bean state has both a P type and an N type. In addition, a complementary metal oxide semi-electrolytic crystal (CMOS) is fabricated, and the substrate may also include a p-type well and an N-type. Well or ' = This is exemplified by a P-type germanium substrate, but does not limit the invention. Then set in the active area where the crystal is located, for example, using area oxidation

1292604 V. INSTRUCTIONS (4) A method (L0C0S) or a shallow trench isolation process (STI) to form a field insulator, which is isolated by the field insulating layer, thereby isolating the internal circuit component region 3〇〇, electrostatic discharge protection structure area 2〇〇. Then, according to the conventional integrated circuit process, such as deposition, lithography and etching steps, a gate insulating layer 101, a gate conductive layer (polysilicon gate) 1 0 2, a gate spacer layer 1 〇 4 are formed in the active region. The gate structure g. Then, by using, for example, ion implantation or diffusion, the source of the circuit element region 3/the drain electrode 1 〇5 and the source of the ESD protection structure region 2 are formed at the semiconductor substrate positions on both sides of the gate structure G. The crucible 6 can be formed by, for example, using an ion implantation process to implant an N-type ion such as a phosphorus-containing or arsenic-containing ion to form an N+-type heavily doped region source/drain 1〇6, which is implanted. The dose is verbose "~2E21 atom/cm3, and the energy is 4〇~8〇Kev. Then, using a self-aligned silicidation or SALICIDE program, a metal silicide (si 1 icide) is formed as The metal telluride gate 1〇8 and the metal germanium source/drain 1〇9 of the circuit element region 3〇〇 and the metal telluride source/drain 110 of the electrostatic discharge protection structure region 2, as shown in FIG. 3B The general automatic alignment golding process comprises the following steps: (1) Firstly, a metal layer is comprehensively formed on the surface of the substrate 1 , the source/drain 106, and the gate structure G. The above metal layer can be utilized. For example, physical vapor deposition (hereinafter abbreviated as PVD) or chemical vapor deposition Forming method (hereinafter referred to as CVD method), and the material thereof may be selected from platinum (pt (Ti), nickel (Ni), cobalt (Co), and erbium (Er), and the formed metal The layer thickness is preferably in the range of 5 nm to 30 nm.

1292604

V. INSTRUCTIONS (5) (2) A heat treatment step is performed to cause the metal layer to react with the surface of the polycrystalline stone and the source/drain 1 〇 6 to form a telluride. The heat treatment f step can be carried out, for example, in an atmosphere of argon gas and nitrogen gas in a rapid tempering furnace at a temperature range of 50 0 to 80 ° C and an execution time of 30 seconds to 2 minutes; In the same atmosphere, the temperature range of 25 〇 to 5 〇〇 C and the execution time of 1 〇 minutes to 2 hours in the hot furnace tube are carried out. (3) The other metal layer which has not been reacted into a metal compound is removed, that is, the structure of the present invention as shown in Fig. 3B is completed. The above unreacted metal layer can be removed by using, for example, a mixed solution of sulfuric acid and hydrogen peroxide; in addition, it can be removed by using, for example, a mixed solution of ammonia water, hydrogen peroxide and water. Therefore, the remaining metal layer which has not reacted with Shi Xi is removed, leaving the ceramsite at the surface of the polycrystalline stone gate 1 〇 2 and the source/dipole 106. Further, please refer to FIG. 3C to comprehensively form a stop layer 11 2 to cover the semiconductor substrate 1 , for example, to deposit a tantalum nitride layer or a hafnium oxynitride layer 112 by a chemical vapor deposition process. Then, the etch stop layer 11 2 is etched back by the lithography and etching process to form an opening 丨 14 of the metal bismuth source/drain 11 露出 exposing the electrostatic discharge protection structure region 200, as shown in Fig. 3D. The contact lens (see Fig. 3E) forms an inner dielectric layer (ILD) 116 on the residual stop layer 112. The dielectric layer 116 forms, for example, a borophosphon glass layer having a thickness of about 6,500 to 7,000 Å. Then, referring to FIG. 3F, a metal contact opening window 118 extending into the source/drain 106 of the ESD protection structure region 2 is formed in the dielectric layer 116 and the metal telluride source/nopole 110. And exposing the circuit component area 300

1292604 V. INSTRUCTIONS (6) Openings of metal telluride source/drain 1〇9. For example, a dielectric layer 11 6 and a metal telluride source/drain 11 0 are defined using a lithography and etching process to obtain a metal contact opening window 11 8 and an opening 1 2 0. Finally, referring to FIG. 3G, a metal layer is deposited in the metal contact region opening window 108 to form a contact plug 122 and a metal contact region 124. The metal layer is formed, for example, by a physical vapor deposition process. The present invention also provides an electrostatic discharge protection structure, please refer to the electric discharge protection structure area 2 〇 第 of FIG. 3 g , the electrostatic discharge protection structure has the following

Secondary component. The first component is a semiconductor substrate 丨00 having a first conductivity type. The second component is a gate structure G, which is composed of a gate insulating layer i 〇1, a gate conductive layer 102, a metal germanide gate electrode 〇8, and a gate spacer layer 〇4. 〇 surface. The first component is a source and a pole 106, which has a second conductivity type, located in the semiconductor substrate 1〇〇 on both sides of the gate structure G. The fourth component is a metal telluride source/drain 11 〇 located above the source/drain 丨〇6. The fifth component is a metal contact region 1 24 which is formed of a metal layer extending from the upper surface of the semiconductor substrate on both sides of the gate structure G into the source/dipole 1 〇 6 interior. The method of manufacturing the electrostatic discharge protection structure of the present invention is produced by the method described above, and therefore the material of each element is as described above and will not be described in detail herein. As can be seen from the electrical discharge protection structure of Figure 3G, a large amount of leakage current 126 easily enters the electrostatic discharge protection element via the metal contact region 124.

0503-6985TW(N) ; TSMC20〇l.〇96l ; ycchen.ptd Page 10 1292604 V. Invention description (7) 2〇0, although the efficiency of the electrostatic discharge protection structure is advanced. While the present invention has been defined by the present invention, it is to be understood that the scope of the invention is not limited by the scope of the invention. Protection 0503-6985TWF(N); TSMC2001-0961; ycchen.ptd Page 11 1292604 BRIEF DESCRIPTION OF THE DRAWINGS To make the above and other aspects of the present invention readily apparent, the following description of the preferred embodiments can be The description is as follows: · In conjunction with the drawings, a detailed first drawing shows a schematic diagram of a conventional electrostatic discharge device. The internal circuit element of the side and the structure is shown in Fig. 2. The semiconductor electrostatic discharge protection structure of the middle portion of the embodiment of the present invention is shown in the third embodiment of the present invention. Section of the manufacturing process [symbol description] 1 〇 ~ output into the pad; 'with metal contact 2 0 ~ electrostatic discharge protection structure; 3 0 ~ internal circuit component area; 21 ~ gate; 22 ~ source; 2 3 ~ 汲Extremely; 24~P-type germanium substrate; 25~NMOS transistor; 26~double carrier transistor; 300~circuit element area; 2 0 0~electrostatic discharge protection structure area; 1 (Π~gate insulation layer; 102~ Gate conductive layer; 104~ gate spacer layer;

Claims (1)

1292604 Cliff Mount 91] (U7/<q VI, Patent Application Range/3曰Correct Net 1) A method with a metal connection, including the following steps: ~ Electrostatic discharge provides a first guide to the semiconductor substrate The upper semiconductor substrate; and the gate spacer composed of the gate spacer layer - the gate insulating layer and the gate conductive layer on both sides of the gate structure =, the source of the electric mode / the drain; the μ semiconductor substrate forms a a second electrode is formed on the surface of the germanium source/drainage surface as a metal germanium gate on the surface of the closed-pole structure to form a metal bismuth-depositive electrode and a metal germanide source/germanium protection structure; On the semiconductor substrate, a gentleman's mouth ν, U milk ke, /, 扒郫 扒郫 〜 〜 〜 成 成 成 成 成 成 成 ; ; ; ; ; ; ; ; ; • • • • • • • • • • • • • • • • • • • • Forming a dielectric layer on the slab of the stop layer; and exposing the metal lithium source/the metal contact 内部 between the dielectric layer and the interior of the enthalpy/deuterium Depositing a metal layer in the open window of the metal contact region to form a metal joint The contact zone. The manufacture of the electrostatic discharge protection structure with the metal contact zone described in the section 1 of the section, the step of forming the metal telluride, further includes the following steps: y forming a first metal layer on the surface of the semiconductor substrate and the gate structure; performing a heat treatment step on the germanium semiconductor substrate such that the source / 汲0503_6985TWFl(N); TSMC2001-0961; Daphne (20060913).ptc (4 pages 1292604 VI. The patent application range is extremely 'and the surface portion of the gate structure forms a metal halide; and the other metal layer that is not reacted into the metal halide is removed. 3. If the patent application scope 2 The method for manufacturing an electric discharge protection structure having a metal contact region, wherein the material of the second metal layer is selected from the group consisting of platinum, titanium, nickel, cobalt and rhodium. A method for manufacturing a private electric discharge protection structure having a metal contact region, wherein the second metal layer is formed by an e vapor deposition method or a chemical vapor deposition method. The method for manufacturing an electric discharge protection structure having a metal contact region according to Item 2, wherein the second metal layer is formed to have a monthly thickness of 5 nm to 30 nm. '(3) Thickness 6 · Metal as described in claim 2 The manufacturing method of the electric discharge protection structure of the contact area, wherein the step of removing the unreacted metal is carried out by using a mixture of sulfuric acid and hydrogen peroxide. The product has the metal contact as described in claim 1 The manufacturing method of the electric discharge protection structure, wherein the etching stop sound... The chemical vapor deposition process deposits a tantalum nitride layer or a hafnium oxynitride layer. 8. The method of manufacturing a metal-electric discharge protection (10) according to the invention of claim 3, wherein the dielectric layer has a static concentration of about 650 to 70 Å. Glass layer. The method of manufacturing a metal contact electric discharge protection structure according to the invention of claim 2, wherein the first conductive type is a static type, and the second conductive type is an N type.悲 为 P P P 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 0503-6985TWFCN) ; TSMC2001-0961 ; ycchen.ptd Page 15 1292604 Modified Oxygen _ Case No. 91104749 6. Manufacturing method of the patented range electric discharge protection structure, wherein the first conductivity type is N type, the second The conductivity type is P type. The method for manufacturing an electrostatic discharge protection structure having a metal contact region according to claim 9, wherein the step of forming the metal halide further comprises the steps of: -33- 1 forming a second metal layer a surface of the semiconductor substrate and the gate structure; performing a heat treatment step on the semiconductor substrate such that the source/drain, and the surface portion of the gate structure form a metal halide; and removing unreacted metal Other base metal layers of telluride. 1 2. The method for manufacturing an electrostatic discharge protection structure having a metal contact region according to claim 11, wherein the second metal layer is made of one of flip-flop, titanium, nickel, diamond and tantalum. By. A method of manufacturing an electrostatic discharge protection structure having a metal contact region as described in claim 11, wherein the second metal layer is formed by physical vapor deposition or chemical vapor deposition. A method of manufacturing an electrostatic discharge protection structure having a metal contact region as described in claim 11, wherein the second metal layer is formed to have a thickness of 5 nm to 30 nm. A method of producing an electrostatic discharge protection structure having a metal contact region as described in claim 11, wherein the step of removing the unreacted metal layer is carried out by using a mixture of sulfuric acid and hydrogen peroxide. [6] The method of manufacturing an electrostatic discharge protection structure having a metal contact region according to claim 9, wherein the etch stop layer is utilized 0503-6985TWFKN) ;TSMC2001 -0961 ;Daphne.ptc Page 16 Case No. 91104749 1292604 VI. Patent application scope Chemical vapor deposition process deposition of a tantalum nitride layer or a ruthenium oxynitride layer - 1 7 · Manufacturing of an electric discharge protection structure having a metal contact region as described in claim 9 The method wherein the dielectric layer forms a borophosphorus glass layer of about 6500 to 7 Å. An electrostatic discharge protection structure having a metal contact region, comprising: a semiconductor substrate having a first conductivity type; a gate structure comprising a gate insulating layer, a gate conductive layer, a metal stone a cerium gate and a gate spacer layer, located on the surface of the semiconductor substrate; a source/drain, having a second conductivity type, located in a semiconductor substrate on both sides of the Han gate structure; The / drain is located above the source/drain; and a metal contact region is formed by a metal layer of the semiconductor substrate on both sides of the self-reading gate structure extending into the source/defective interior. An electrostatic discharge protection structure having a metal contact region as described in claim 8 wherein the first conductivity type is a P type and the second conductivity type is an N type. An electrostatic discharge protection structure having a metal contact region as described in claim 8 wherein the first conductivity type is an N type and the second conductivity type is a P type. 0503-6985TWFl(N); TSMC2001-〇961; Daphne.ptc Page 17 1292604 Case No. 91104749 Year ι月 G曰 Revision 1 Chinese Invention Abstract (The name of the invention · Electrostatic discharge protection structure with metal contact area and Manufacturing Method) A metal layer is deposited in the open window to form a metal contact region. (1) The representative figure of this case is ···················································· 0 5 ~ source / drain; 1 0 8 ~ metal telluride gate; 300 101 104 100 106 109 112 122 126 circuit element region gate insulating layer gate spacer semiconductor substrate source / drain;, 11 0 ~ metal Telluride source / bungee; I insect stop layer; 11 6 ~ dielectric layer; contact plug; 124 ~ metal contact area a large amount of leakage current. English abstract (name of invention: 0503-6985TWF1(N); TSMC2001-0961; Daphn e.p t c Page 3