JPH02288341A - Mis-type semiconductor device - Google Patents
Mis-type semiconductor deviceInfo
- Publication number
- JPH02288341A JPH02288341A JP10964789A JP10964789A JPH02288341A JP H02288341 A JPH02288341 A JP H02288341A JP 10964789 A JP10964789 A JP 10964789A JP 10964789 A JP10964789 A JP 10964789A JP H02288341 A JPH02288341 A JP H02288341A
- Authority
- JP
- Japan
- Prior art keywords
- sidewall
- diffusion layer
- impurity diffusion
- type impurity
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010937 tungsten Substances 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- -1 C01Ni Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- SYHGEUNFJIGTRX-UHFFFAOYSA-N methylenedioxypyrovalerone Chemical compound C=1C=C2OCOC2=CC=1C(=O)C(CCC)N1CCCC1 SYHGEUNFJIGTRX-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野ｊ 本発明は、ＭＩＳ型半導体装置の構造に関する。[Detailed description of the invention] [Industrial field of use] The present invention relates to the structure of a MIS type semiconductor device.
〔従来の技術］
半導体装置の微細化、高集積化にともないＭＯ８型トラ
ンジスタも微細化されてきている。しかし、素子寸法を
微細化することによりホットキャリアによる特性劣化と
いう問題が生じてきている。この問題を解決するための
ＬＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ
）という横道が提案されているが、このＬＤＤをさらに
改良した構造が次の文献に掲載されている。 （Ｒ，
ＩＺＡＷＡ、Ｔ、にＵＲＥ、Ｅ、 ＴＡＫＥＤＡ、 ”
ＴＨＥ ＩｕＰＡＣＴ ＯＦ ＧＡＴＥ−ＤＩＩＩＡＩ
Ｎ ０ＶＥＲＬＡＰＰＥＤ ＬＤＤ （ＧＯＬＤ
Ｊ ＦＯＲＤＥＥＰ ＳＵＢ ＭＩＣＲＯＮ Ｖ
ＬＳＩ’Ｓ ” 、 ＩＥＤＭ Ｔｅｃｈ、 Ｄｉｇ−
ｐｐ３８−ｐｐ４１１９〔発明が解決しようとする課題
１
しかし、前述の従来技術では、製造プロセスがかなり複
雑であり、低濃度不純物拡散層の寸法制御性が悪く、ゲ
ート電極の段差が大きいために、平坦性が悪いという課
題を有する。[Prior Art] As semiconductor devices become smaller and more highly integrated, MO8 type transistors are also becoming smaller. However, miniaturization of element dimensions has led to the problem of deterioration of characteristics due to hot carriers. LDD (Lightly Doped Drain) is used to solve this problem.
) has been proposed, and a structure that further improves this LDD is published in the following document. (R,
IZAWA, T, URE, E, TAKEDA,”
THE IuPACT OF GATE-DIIIIAI
N 0VERLAPPED LDD (GOLD
J FORDEEP SUB MICRON V
LSI'S'', IEDM Tech, Dig-
pp38-pp4119 [Problem to be Solved by the Invention 1] However, with the above-mentioned conventional technology, the manufacturing process is quite complicated, the dimensional control of the low concentration impurity diffusion layer is poor, and the step of the gate electrode is large, so it is difficult to achieve a flat surface. It has the problem of poor sex.
そこで本発明はこのような課題を解決するもので、その
目的とするところは、製造プロセスが容易であり、寸法
制御性、平坦性が良好な半導体装置を提供するところに
ある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device that is easy to manufacture and has good dimensional controllability and flatness.
〔課題を解決するための手段］
本発明の半導体装置は、
ｌ）第１導電型半導体基板、ゲート絶縁膜、ゲート電極
から成るＭＩＳ型半導体装置において、前記ゲート電極
が下層筒１の導電体、上層は下層より幅の狭い第２の導
電体であり、前記第２の導電体の側壁には絶縁膜もしく
は第３の導電体のサイドウオールが形成され、前記サイ
ドウオールの端部が前記第１の導電体の端部に一致し。[Means for Solving the Problems] A semiconductor device of the present invention includes l) an MIS type semiconductor device comprising a first conductivity type semiconductor substrate, a gate insulating film, and a gate electrode, wherein the gate electrode is a conductor of the lower cylinder 1; The upper layer is a second conductor having a width narrower than that of the lower layer, an insulating film or a sidewall of a third conductor is formed on the sidewall of the second conductor, and an end of the sidewall is connected to the first conductor. Match the ends of the conductors.
前記第１導電型半導体基板表面に形成された低濃度第２
導電型不純物拡散層が、＠記すイドウオールの直下に位
置することを特徴とする。A second low concentration layer formed on the surface of the first conductivity type semiconductor substrate.
It is characterized in that the conductive type impurity diffusion layer is located directly under the id wall marked with @.
〔実 施 例１ 以下図面を用いて、本発明の実施例を詳細に説明する。[Implementation example 1] Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図（ａ）は本発明による半導体装置を表わす断面図
であり、１０１はＰ型Ｓｉ基板、１０２は素子分離用酸
化膜、１０３はゲート酸化膜、１０４は多結晶Ｓｉ （
１０００〜２０００人）、１０５はＭｏシリサイド （
１５００〜２５００人）、１０７は絶縁膜サイドウオー
ルである。１０６は低濃度Ｎ型不純物拡散層、１０８は
高濃度不純物拡散層であり、図示したように前記低１度
不純物拡散層１０６は、前記ゲート酸化膜１０３をはさ
んで、先端部が前記Ｍｏシリサイド１０５の端部のほぼ
直下にくるように形成されている。FIG. 1(a) is a cross-sectional view showing a semiconductor device according to the present invention, in which 101 is a P-type Si substrate, 102 is an oxide film for element isolation, 103 is a gate oxide film, and 104 is a polycrystalline Si (
1000-2000 people), 105 is Mo silicide (
1500 to 2500 people), 107 is an insulating film side wall. 106 is a low concentration N-type impurity diffusion layer, 108 is a high concentration impurity diffusion layer, and as shown in the figure, the low 1 degree impurity diffusion layer 106 is sandwiched between the gate oxide film 103 and the tip thereof is formed of the Mo silicide. It is formed so as to be located almost directly below the end of 105.
第１図（ｂ）は本発明の伯の実施例を表わす断面図であ
り、ここでは第１図（ａ）で用いた絶縁膜サイドウオー
ルの代わりにダンゲステンサイドウオール１０７′が用
いられている。FIG. 1(b) is a cross-sectional view showing an embodiment of the present invention, in which a Dungesten sidewall 107' is used in place of the insulating film sidewall used in FIG. 1(a). .
次に本発明の製造方法を第２図（ａ）〜 により説明す
る。Next, the manufacturing method of the present invention will be explained with reference to FIGS.
工程（１）・・・第２図（ａ）
Ｐ型Ｓｉ基板１０１上にＬＯＣＯ５法で素子分離用酸化
膜１０２を２０００〜７０００人形成した後に、ゲート
酸化膜１０３を熱酸化法により１００〜３００人形成し
、さらに化学的気相成長法により全面に多結晶５ｉ１０
４を１０００〜２０００人形成する。全面にリンあるい
はＡｓ等のＮ型不純物を拡散法またはイオン打込法にて
注入した後に、スパッタ法でＭｏシリサイド１０５を１
５００〜２５００人形成する。Step (1)...FIG. 2(a) After forming an oxide film 102 for element isolation of 2,000 to 7,000 layers on a P-type Si substrate 101 by the LOCO5 method, a gate oxide film 103 of 100 to 300 layers is formed by a thermal oxidation method. Polycrystalline 5i10 is formed on the entire surface by chemical vapor deposition.
Form 4 of 1000 to 2000 people. After implanting N-type impurities such as phosphorus or As into the entire surface by diffusion or ion implantation, 10% of Mo silicide 105 is added by sputtering.
Form 500 to 2,500 people.
工程（２）・・・第２図（ｂ）
レジストパターンを用いて、前記Ｍｏシリサイド１０５
の一部をエツチング除去し、レジストパターン除去後、
＠記ＭＯシリサイドパターンをマスクにリン１０６′を
ＤＯ３Ｅ量１０′２〜１０１０１１Ｃ”、エネルギー１
００〜２００ｋｅＶでイオン注入することで前記多結晶
５ｉ１０４を通過し、低濃度Ｎ型不純物拡散層１０６を
前記基板１０１表面に形成する。Step (2)...FIG. 2(b) Using the resist pattern, the Mo silicide 105 is
After removing a part of the resist pattern by etching,
@ Using the MO silicide pattern as a mask, add phosphorus 106' to DO3E amount 10'2~101011C'', energy 1
By implanting ions at 00 to 200 keV, the ions pass through the polycrystal 5i 104 and form a low concentration N-type impurity diffusion layer 106 on the surface of the substrate 101.
工程（３）・・・第２図（ｃ）
全面に化学的気相成長法により絶縁膜（酸化膜または窒
化膜）またはタングステンを２０００〜６０００人形成
した後に全面リアクティブイオンでエツチングし、絶縁
膜サイドウオール１０７またはタングステンサイドウオ
ール１０７′を形成する。Step (3)...Figure 2(c) After forming 2,000 to 6,000 insulating films (oxide films or nitride films) or tungsten on the entire surface by chemical vapor deposition, the entire surface is etched with reactive ions to form the insulation. A membrane sidewall 107 or tungsten sidewall 107' is formed.
工程（４）・・・第２図（ｄ）
前記Ｍｏシリサイド１０５及び絶縁膜サイドウオール１
０７（又はタングステンサイドウオール１０７′）をマ
スクにＡｓ １０８゛を６０〜１２０ｋｅＶのエネルギ
ー ＋ＱＩＳ程度のＤＯ５Ｅｉｌでイオン注入し、電気
炉、またはハロゲンランプでアニールし、高濃度Ｎ型不
純物拡散層１０８を形成する０以上実施例に基づき本発
明を説明してきたが、本発明は実施例に限定されるもの
ではなく、発明の主旨を逸脱しない範囲で種々変更可能
なことは言うまでもない。Step (4)...FIG. 2(d) Mo silicide 105 and insulating film sidewall 1
Using 07 (or tungsten sidewall 107') as a mask, As 108'' is ion-implanted with an energy of 60 to 120 keV and DO5Eil of approximately QIS, and annealed in an electric furnace or halogen lamp to form a high concentration N-type impurity diffusion layer 108. Although the present invention has been described based on zero or more examples, it goes without saying that the present invention is not limited to the examples and can be modified in various ways without departing from the gist of the invention.
例えばゲート電極に用いた導電体は多結晶Ｓｉ及びＭｏ
シリサイドであるが、これらはＣ０１Ｎｉ、Ｐｔ、Ｗ、
Ｔｉ、Ｔａ等の高融点金属もしくはそのシリサイドであ
ってもよいし、サイドウオールとして用いたＷの代わり
に上記の材料を用いてもかまわない。For example, the conductor used for the gate electrode is polycrystalline Si and Mo.
These are silicides such as C01Ni, Pt, W,
It may be a high melting point metal such as Ti or Ta or its silicide, or the above materials may be used instead of W used as the sidewall.
［発明の効果］
本発明によれば、製造プロセスが容易で＄１目Ｊ口性の
よいＧＯＬＤ構造の半導体装置を提供できるという効果
を有する。[Effects of the Invention] According to the present invention, it is possible to provide a semiconductor device having a GOLD structure that has an easy manufacturing process and good quality.
具体的には、 １）低濃度不純物拡散層の寸法制御性が良い。in particular, 1) Good dimensional controllability of the low concentration impurity diffusion layer.
２）ゲート電極の段差が小さく平坦性が良い。2) The gate electrode has small steps and good flatness.
０７′ ０８ ・ ０８′ 絶縁膜サイドウオール タングステンサイドウオール ・高濃度Ｎ型不純物拡散層 ・ Ａｓ 以上07' 08・ 08' Insulating film side wall tungsten sidewall ・High concentration N-type impurity diffusion layer ・As that's all
第１図（ａ）（ｂ）は本発明の構造を表わす断面図。
第２図（ａ）〜（ｄ）は本発明の製造方法を表わす断面
図。FIGS. 1(a) and 1(b) are cross-sectional views showing the structure of the present invention. FIGS. 2(a) to 2(d) are cross-sectional views showing the manufacturing method of the present invention.
Claims (1)
極から成るＭＩＳ型半導体装置において、前記ゲート電
極が下層第１の導電体、上層は下層より幅の狭い第２の
導電体であり、前記第２の導電体の側壁には絶縁膜もし
くは第３の導電体のサイドウォールが形成され、前記サ
イドウォールの端部が前記第１の導電体の端部に一致し
、 前記第１導電型半導体基板表面に形成された低濃度第２
導電型不純物拡散層が、前記サイドウォールの直下に位
置することを特徴とするＭＩＳ型半導体装置。(1) In an MIS type semiconductor device comprising a first conductivity type semiconductor substrate, a gate insulating film, and a gate electrode, the gate electrode is a lower layer first conductor, and the upper layer is a second conductor narrower than the lower layer, An insulating film or a sidewall of a third conductor is formed on the sidewall of the second conductor, an end of the sidewall matches an end of the first conductor, and the first conductor is of the first conductivity type. A low concentration second layer formed on the surface of the semiconductor substrate
A MIS type semiconductor device, wherein a conductive type impurity diffusion layer is located directly under the sidewall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10964789A JPH02288341A (en) | 1989-04-28 | 1989-04-28 | Mis-type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10964789A JPH02288341A (en) | 1989-04-28 | 1989-04-28 | Mis-type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02288341A true JPH02288341A (en) | 1990-11-28 |
Family
ID=14515590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10964789A Pending JPH02288341A (en) | 1989-04-28 | 1989-04-28 | Mis-type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02288341A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5600153A (en) * | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
| US5804838A (en) * | 1995-05-26 | 1998-09-08 | Micron Technology, Inc. | Thin film transistors |
| US6204521B1 (en) | 1998-08-28 | 2001-03-20 | Micron Technology, Inc. | Thin film transistors |
| JP2007524984A (en) * | 2003-01-15 | 2007-08-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Low GIDLMOSFET structure and manufacturing method |
-
1989
- 1989-04-28 JP JP10964789A patent/JPH02288341A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5600153A (en) * | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
| US5658807A (en) * | 1994-10-07 | 1997-08-19 | Micron Technology, Inc. | Methods of forming conductive polysilicon lines and bottom gated thin film transistors |
| US5670794A (en) * | 1994-10-07 | 1997-09-23 | Micron Technology, Inc. | Thin film transistors |
| US5985702A (en) * | 1994-10-07 | 1999-11-16 | Micron Technology, Inc, | Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors |
| US5804838A (en) * | 1995-05-26 | 1998-09-08 | Micron Technology, Inc. | Thin film transistors |
| US6204521B1 (en) | 1998-08-28 | 2001-03-20 | Micron Technology, Inc. | Thin film transistors |
| JP2007524984A (en) * | 2003-01-15 | 2007-08-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Low GIDLMOSFET structure and manufacturing method |
| JP4678875B2 (en) * | 2003-01-15 | 2011-04-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | MOSFET device with low gate induced drain leakage (GIDL) current |
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