JPH11297985A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise the withstand voltage of a source-drain junction without victimizing the element isolation characteristics, by forming the sourcedrain region and source-drain ends isolated from an element isolation region, element isolation region ends and channel region beneath a gate electrode. SOLUTION: After forming a gate oxide film 4 and gate electrodes 5, an impurity is introduced to form low-concn. impurity diffusion regions 6, an inter- layer film 7 for insulating a substrate from wirings is formed, contact regions 8 are formed, an impurity ion is implanted through contact holes to form high- concn. impurity diffusion regions 9, thus forming a structure, with high-concn. impurity diffusion regions 9 forcedly isolated from the element isolation regions. A structure relaxing the element field concn. on the boundary between the element isolation and source-drain or between the channel region and source- drain region can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming a high breakdown voltage element in a semiconductor device.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a main sectional process and an example of a structure of a conventionally known MOS transistor. As shown in FIG. 2A, a well (FIG. 2A) 1 and an element isolation region LOCOS (FIG. 2A) are formed on a silicon substrate of the first conductivity type.
2) is formed. At this time, the element isolation region LOCOS
Below the first to prevent inversion of the parasitic MOSFET.
Conductive impurities (FIG. 2A) 3 are introduced. Next, a gate electrode (FIG. 2 (a) 5) is formed via a gate insulating oxide film (FIG. 2 (a) 4) through a first conductivity type impurity implantation step of adjusting the threshold value of the transistor. .

Next, as shown in FIG. 2B, after forming a low-concentration impurity diffusion region of a second conductivity type (FIG. 2B) 6, a spacer (FIG. 2B) 10 is formed. , A source-drain high-concentration impurity diffusion region of the second conductivity type (FIG. 2)
(B) 9) is formed in a self-aligned manner.

Next, as shown in FIG. 2C, an insulating oxide film (FIG. 2C) is used to insulate the first metal wiring layer.
7) is deposited, a contact (FIG. 2C) 8 is opened by a photolithography technique and an etching technique, a metal film is deposited by sputter deposition or the like, and patterning is performed to form a wiring layer.

[0005]

In general, the junction withstand voltage of the source / drain is determined by the impurity in the high-concentration impurity diffusion region of the second conductivity type forming the source and drain, the impurity in the well of the first conductivity type, and the gate electrode. It is determined by the impurity concentration distribution in the lower channel portion and the impurity in the element isolation region and the like, and the structure having a higher electric field concentration has a lower breakdown voltage. In a miniaturized semiconductor device, the concentration of a channel region increases as the gate insulating oxide film becomes thinner, and the electric field strength of the source / drain region and the channel region increases. The same applies to the element isolation region. In order to improve the element isolation capability, the impurity concentration of the first conductivity type also needs to be increased. Therefore, at the boundary between the element active region and the element isolation region,
The electric field strength increases. As a result, the junction withstand voltage of the source / drain decreases. In general, there is no problem because the power supply voltage of the circuit is reduced at the same time as the miniaturization of elements. However, in actuality, in circuits such as flash memories and LCD driving ICs, the elements are miniaturized and external input Even when the output voltage is lowered, the output operates at a voltage higher than the power supply voltage due to internal boosting or the like, which is a barrier to miniaturization of elements in the region.

Therefore, in order to miniaturize a region requiring a high withstand voltage by the conventional technique, it is necessary to reduce the device isolation capability and the high withstand voltage of the source / drain, and the miniaturization of the transistor and the high withstand voltage of the source / drain. Conflicting situations arise between.

That is, in order to improve the element isolation capability, it is necessary to increase the impurity concentration of the first conductivity type below the element isolation region LOCOS, and electric field concentration occurs at the boundary between the source / drain region and the element isolation region. As a result, the junction withstand voltage of the source / drain decreases. On the other hand, if an attempt is made to increase the withstand voltage of the source / drain, the element isolation capability is reduced, and it is necessary to widen the element isolation region in design, and it is impossible to achieve miniaturization.

In addition, with the miniaturization of elements, a high driving capability of a transistor is required, and when the gate insulating oxide film is thinned, it is necessary to increase the impurity concentration of the first conductivity type in the channel region. Decrease. On the other hand, if the impurity concentration in the channel region is reduced in order to prevent a decrease in the junction withstand voltage of the source / drain, the MOS
The threshold value of the FET is reduced, and the operation as an element is lost.

Therefore, the present invention solves such a problem, and an object thereof is to reduce the size of a MOSF to be miniaturized.
An object of the present invention is to provide a structure of a semiconductor device and a method of manufacturing the same, which increase the junction breakdown voltage of the source / drain without sacrificing the ET characteristics and the element isolation characteristics.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device having a structure in which a source-drain region and a source-drain end are formed in an element isolation region, an element isolation region end, and a region under a gate electrode. It is characterized by a structure formed to be isolated from the channel region.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: a) forming an element isolation region and an element active region on a silicon substrate of a first conductivity type; Forming at least below the element isolation region; c) introducing an impurity of a first conductivity type into a device active region for adjusting a threshold value of the device; d) over the element active region. Forming a gate insulating oxide film and a gate electrode; and e) forming a second conductivity type low concentration impurity diffusion region on the surface of the silicon substrate and in the active region of the device using the gate electrode as a mask. f) a step of forming an insulating interlayer film between the element active region and the element isolation region and the first wiring layer; and g) a step of forming a contact for making connection between the element active region and the first wiring layer. H) in said step That the opening, the second conductivity type impurity is introduced by ion implantation, by subsequent heat treatment, characterized by forming a high concentration impurity diffusion region in the silicon substrate.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. However, the embodiments to be described are merely specific examples when implementing the present invention, and do not specify the present invention itself.

The following description is based on an N-type MOSFET for high breakdown voltage.
It will be described with T.

1. As starting material, crystal orientation <100
> Prepare a P-type silicon substrate of 10 Ω · cm.

2. An oxide film having a thickness of 300 Å is formed on a silicon substrate at a temperature of 1100 ° C. and an oxygen partial pressure of 95%. Thereafter, B ^{+ is} passed through this film to 60
Implanted with KeV, 8.0 × 10 ¹² atoms / cm ² ,
Annealing is performed at 1100 ° C. in a nitrogen atmosphere for 4 hours to push impurities. Thereby, P on the surface of the silicon substrate
A well (FIG. 3A) 1 having a mold impurity concentration of about 3 × 10 ¹⁶ is formed. Next, the above-mentioned silicon oxide film is removed with diluted hydrofluoric acid, and
Oxidize the silicon substrate at 50 ° C and 95% oxygen atmosphere,
A silicon oxide film of 00 angstroms is formed, and a nitride oxide film is deposited by 1600 angstroms by LPCVD (low pressure chemical vapor deposition), and the nitrided oxide film is opened by photolithography and an etching technique. At this time, the underlying silicon oxide film is left. Next, with the photoresist remaining, B ^{+ is set} to 30 KeV and 5.0 × 10 ¹³ atoms / c to improve the element isolation ability.
Implant at m ² and strip the photoresist. Next, a silicon oxide film is formed at 950 ° C. in an atmosphere of 95% water vapor at 950 ° C. in an atmosphere of water vapor at 950 ° C. using a silicon oxide film having a thickness of 5000 Å, and the nitrided oxide film is removed with hot phosphoric acid. , And furthermore, with diluted hydrofluoric acid,
The 200 angstrom silicon oxide film under the nitrided oxide film is removed. In this way, LOCOS (FIG. 3A) 2 serving as an element isolation region is formed.

3. A 250 Å silicon oxide film serving as a sacrificial oxide film is formed at a temperature of 850 ° C. and in a 95% steam atmosphere. Through this silicon oxide film, B
F ²⁺ at 40 KeV, 3.0 × 10 ¹² atoms / cm
^Then , the threshold value of the NMOSFET is adjusted.
Thereafter, the sacrificial oxide film of 250 Å is removed by using diluted hydrofluoric acid, and a gate oxide film of 200 Å (FIG. 3A) 4 is formed again at a temperature of 850 ° C. and a 95% steam atmosphere. . Further, 1500 Å of polycrystalline polysilicon is deposited in advance while phosphorus is vapor-phase diffused, and tungsten silicide is
Sputter coat 500 Angstrom. And
The gate electrode (Fig. 3)
(A) Form 5). The process steps so far generally correspond to normal steps.

4. Next, phosphorus BF ²⁺ was added to 40 KeV,
Impurity is introduced at 3.0 × 10 ¹² atoms / cm ² to form a low-concentration impurity diffusion region (6 in FIG. 3B). Generally, here, an N-type impurity is implanted in the order of 10 ¹⁵ atoms / cm ² to form a highly-diffused source / drain region or to form a sidewall spacer or the like, and then add an impurity. So again, 10 ¹⁵ at
om / cm ² , and a concentration of 2
Although a source / drain region having a double structure is formed, in the present invention, high-concentration impurities are not introduced at this time.

5. Next, a silicon oxide film in which impurities are not diffused is deposited to a thickness of 1000 Å by LPCVD, and furthermore, boron and silicate glass (B
(PSG) layer deposited at 8000 Å, 850 Å
Annealing in a nitrogen atmosphere at about 30 ° C. for about 30 minutes, followed by baking, and an interlayer film for insulating between the substrate and the wiring (FIG. 3C)
To form Next, a contact region (FIG. 3C) 8 is formed by photolithography and an etching technique, and the photoresist is stripped. Next, As is passed through the contact hole formed above.
⁺ Ions are implanted at 50 KeV and 2.0 × 10 ¹⁵ atoms / cm ² , and an annealing treatment is performed in an electric furnace at 1000 ° C. for about 30 seconds to activate the impurities, thereby forming a high-concentration impurity diffusion region (FIG. 3C). 9) is formed. Thus, the high-concentration impurity diffusion region is forcibly separated from the element isolation region and the channel region.

[7] Subsequent steps generally correspond to ordinary steps. Sputter-coat 500 Angstrom Ti layer and 1000 Angstrom TiN layer, deposit tungsten, etch back all over, bury tungsten in contact holes, sputter deposit Al alloy and TiN layer, pattern wiring by photolithography and etching technology .

In this manner, the device isolation and the source / drain boundary, or
A semiconductor device having a structure for alleviating electric field concentration at the boundary between the channel region and the source / drain can be realized.

[0021]

As described above, according to the first aspect, the electric field concentration at the end of the source / drain region can be reduced, and the withstand voltage of the source / drain can be easily increased. At the same time, the impurity introduction for preventing the inversion of the parasitic MOSFET in the element isolation region can be performed independently of the increase in the breakdown voltage of the source / drain, so that the element isolation ability can be easily improved. Further, as the device becomes finer, the impurity concentration of the channel region increases due to the thinner gate insulating oxide film. This also has the effect that it can be performed independently of increasing the withstand voltage of the source / drain.

According to claim 2, not only can the structure described in claim 1 be realized, but also in terms of the number of manufacturing steps,
There is no increase, but rather the number of steps for forming the sidewall spacers can be reduced, which has the effect of simplifying the steps.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a sectional view of a main process of a conventional semiconductor device.

FIG. 3 is a sectional view of a main step of the semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Well area of 1st conductivity type 2 ... Element isolation area, LOCOS 3 ... Low concentration impurity diffusion area for improvement of element isolation of 1st conductivity type 4 ... Gate insulating oxide film 5 ... Gate Electrode 6: low-concentration impurity diffusion region of second conductivity type 7: interlayer insulating oxide film 8: contact opening 9: high-concentration impurity diffusion region 10: sidewall spacer

Claims (2)

[Claims] 1. A semiconductor device having a structure in which a source / drain region and a source / drain end are formed so as to be isolated from an element isolation region, an end of the element isolation region, and a channel region below a gate electrode. A) forming an element isolation region and an element active region on a first conductivity type silicon substrate; and b) forming a first conductivity type impurity at least below the element isolation region. C) a step of introducing a first conductivity type impurity for adjusting a threshold value of the element into the element active region; and d) a step of forming a gate insulating oxide film and a gate electrode on the element active region. E) forming a second-conductivity-type low-concentration impurity diffusion region on the surface of the silicon substrate and in the active region of the element using the gate electrode as a mask; f) the active region and the isolation region of the element; Forming an insulating interlayer film between the first wiring layers; g) forming a contact for making a connection between the element active region and the first wiring layers; and h) forming a second conductive layer through the opening formed by the above-described step. Implantation of mold impurities More introduced by subsequent heat treatment, a method of manufacturing a semiconductor device comprising the steps of forming a high-concentration impurity diffusion region in the silicon substrate.