JP2925868B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an LDD structure of a MOS transistor which allows a device to be downsized.

[0002]

2. Description of the Related Art In a semiconductor device, a low concentration impurity is diffused into a silicon substrate to increase the breakdown voltage of an element.
A D (Lightly Doped Drain) structure may be formed. A semiconductor device having an LDD structure has been conventionally manufactured as follows.

FIG. 6 shows a part of a manufacturing process of a MOSFET (MOS field effect transistor). After the p-type silicon substrate 2 is thermally oxidized to form a silicon oxide film, LOC
The silicon surface is selectively oxidized according to the element isolation by the OS method to form the element isolation film 10 and the element formation region. The silicon surface of the element forming region 12 is thermally oxidized to form a gate oxide film 14 having a thickness of about 150 Å to 250 Å.

Next, CVD (Chemical Vapor Depressio)
A polysilicon layer is deposited on the entire surface by the method n).
The gate electrode 24 is obtained by etching the polysilicon layer by RIE (Reactive Ion Etching) (FIG. 6A).

From this state, arsenic is added to the p-type silicon substrate 2 at 40 KeV to 70 KeV at 2 × 10 ¹³ / cm ^{2 to} 3 arsenic.
X 10 ¹³ ions / cm ² are implanted and diffused to form a low-concentration n-type impurity diffusion layer 26 in the p-type silicon substrate 2 (FIG. 6).
B).

When the LDD structure is provided as described above,
The sidewall 30 is formed using a silicon nitride film.
Further, arsenic is ion-implanted and diffused into the p-type silicon substrate 2, and the high-concentration n-type impurity diffusion layer 32 is diffused into the p-type silicon substrate 2.
Is formed (FIG. 6C).

After that, an interlayer insulating film is provided, an Al wiring is formed, and a desired MOSFET is covered with a passivation film.
Get.

[0008]

However, the conventional method for manufacturing a semiconductor device as described above has the following problems.

In order to increase the degree of integration of a semiconductor device, it is necessary to reduce the size of each semiconductor element. In this case, the size of the semiconductor element must be reduced uniformly in the horizontal and vertical directions. That is, when the element is reduced in the horizontal direction (the horizontal direction in FIG. 6), it is necessary to reduce the element in the vertical direction (the vertical direction in FIG. 6) at the same rate. Therefore, the gate oxide film 14 is formed thin.

Therefore, in the ion implantation for forming the low-concentration n-type impurity diffusion layer 26, it is necessary to set the arsenic energy low and control the arsenic implantation range shallowly. However, the energy level of impurities such as arsenic is 1
It is difficult to set the thickness to 0 KeV or less, which makes it impossible to reduce the thickness of the gate oxide film 14 to a predetermined thickness or less, which limits the miniaturization of the semiconductor element.

An object of the present invention is to solve the above-mentioned problems and form an LDD structure by thermal diffusion, thereby miniaturizing a semiconductor device.

[0012]

According to the present invention, there is provided a semiconductor device comprising:
The manufacturing method is such that the surface of the silicon substrate of the first conductivity type is
ONO which has the property that the implanted ions are difficult to permeate
ONO film forming step of forming a film , conducting on the ONO film
Conductive film formation step of forming a conductive film, and the ONO film,
In the portion where the conductive film is not provided on the upper portion, the second conductive type
Ion implantation step to implant ON, implanted into ONO film
Heat treatment of the ions of the second conductivity type
A second conductive type region formed by diffusing into a silicon substrate;
Forming a two-conductivity type region.
You.

[0013]

According to a first aspect of the present invention, there is provided an ONO film forming step.
In the pump, ions pass through the surface of the silicon substrate
An ONO film with stiffness is formed, and an ion implantation step is performed.
Ion of the second conductivity type from above the silicon substrate
Type.

Thus, the implanted ions are transferred to the silicon substrate
Instead, it is cut off and held at the ONO film.

Next, in the second conductivity type region forming step,
Then, the ions held in the ONO film are silicified by heat treatment.
Diffuses to the control board. As a result, a shallow region of the second conductivity type is formed on the surface of the silicon substrate.

Therefore, even if the energy of the implanted ions is relatively large as compared with the element size, the second conductivity type region can be formed shallowly on the surface of the silicon substrate.

The nitride film of the ONO film is made of silicon oxide.
Ions are less likely to permeate than the activated film. This allows injection
Ions are reliably blocked and retained at the insulating film portion.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a MOSFET according to an embodiment of the present invention will be described with reference to the drawings.

First, as shown in FIG. 1A, a p-type silicon substrate 2 is thermally oxidized at 900 ° C. to 1000 ° C. to form a silicon oxide film 4 having a thickness of about 200 Å to 400 Å on the upper surface. According to element isolation by the LOCOS method, the silicon surface is selectively oxidized using a silicon nitride film (not shown) to form the element isolation film 10 and the element formation region 12 of FIG. 1B. The film thickness of the element isolation film 10 is formed in the range of 3000 Å to 6000 Å.

When the device isolation is completed, an ONO film is formed next to form a gate insulating film. In order to form the ONO film, first, the silicon surface of the element formation region 12 is heated to 900 ° C.
Thermal oxidation is performed at 1000 ° C. to form a silicon oxide film having a thickness of 100 Å. Subsequently, a nitride film having a thickness of 80 angstroms and a nitrogen oxide film having a thickness of 20 angstroms are sequentially formed on the silicon oxide film. Thus, an ONO film 20 having a three-layer structure of a silicon oxide film, a nitride film, and a nitrogen oxide film is formed, and functions as a gate insulating film (FIG. 1C).

When the formation of the gate insulating film is completed, the CVD method based on the thermal decomposition of silane (SiH ₄ ) is used, as shown in FIG.
1000 angstrom thick on the entire surface of the structure
Deposit 3000 Å of polysilicon layer 22 (FIG. 2A). The polysilicon layer 22 is doped with not less than 10 ²⁰ phosphorus / cm ³ by ion implantation to form an n ⁺ polysilicon layer.

Thereafter, the polysilicon layer 22 is etched into a shape of a gate electrode by RIE using a resist (not shown) as a mask to obtain a gate electrode 24 shown in FIG. 2B.

Next, using this gate electrode 24 as a mask,
Arsenic is applied to the ONO film 20 from the direction of the arrow Y1 at 12 KeV for 3 ×.
10 ¹³ ions / cm ² are implanted. Since the energy level of arsenic is low, arsenic is not implanted into p-type silicon substrate 2. Thereafter, heat treatment is performed at 900 ° C. for 30 minutes. As a result, the arsenic ions implanted in the ONO film 20 diffuse into the p-type silicon substrate 2 (solid-phase diffusion), forming a low-concentration n-type impurity diffusion layer 26 (FIG. 2C).

Further, as shown in FIG. 3A, a silicon nitride film 28 having a thickness of 2000 Å to 3000 Å is formed by the CVD method. Subsequently, the silicon nitride film 28 is etched by RIE using the resist pattern as a mask, and the silicon nitride film sidewalls are etched.
Form 30 (FIG. 3B). Thereafter, the p-type silicon substrate 2
Then, arsenic is ion-implanted and diffused at 10 ¹⁵ to 10 ¹⁶ ions / cm ² at 50 KeV. Thereby, as shown in FIG. 3C,
A high-concentration n-type impurity diffusion layer 32 is formed on a p-type silicon substrate 2. Since the surface of the p-type silicon substrate 2 becomes an amorphous layer at the time of ion implantation, it is annealed at 900 ° C. to 1000 ° C. to return to a silicon crystal.

Thereafter, in order to provide Al wiring between the elements,
First, the entire surface of the wafer is covered with an interlayer insulating film 34 (FIG. 4A). The interlayer insulating film 34 is made of PSG (Phospho-Silica) by a CVD method.
using te Glass)
Formed to 4000 angstroms. 1000 ° C. to 11 ° C. to improve the lithography accuracy at the time of Al wiring
The PSG is reflowed at 00 ° C. to flatten the wafer surface.

When the reflow of the PSG is completed, mask alignment is performed, and patterning is performed so that holes are formed in the resist only at the wiring outlet. Next, the interlayer insulating film 34 is etched and removed by RIE using a resist as a mask, and a contact hole as an opening for taking out a wiring is formed.
35 is provided (FIG. 4B).

Thereafter, an Al-Si (Si content: 1% or less) alloy is sputtered on the entire surface to form an Al wiring 36 having a film thickness of 5000 Å to 10000 Å. Again, mask alignment and etching by RIE are performed to form a wiring pattern (FIG. 5A).
After the wafer is heat-treated (sintered) at 450 ° C. for 30 minutes in a forming gas, it is covered with a passivation film 38 to protect the Al wiring 36 (FIG. 5B). Through the above steps, a MOSFET is manufactured.

Although a MOSFET is formed in this embodiment, a semiconductor device having a MOSFET may be formed.

The energy and impurity concentration of impurities at the time of ion implantation, the thickness of the ONO film 20, and the heat treatment temperature and time at the time of solid phase diffusion are not limited to the above embodiment.

[0030]

According to the first aspect of the present invention, an ONO film is formed.
In the step, ions permeate the surface of the silicon substrate
Forming an ONO film that is difficult to perform
At the step, the second
Two-conductivity type ions are blocked and held at the ONO film,
It is held by the ONO film in the two-conductivity region forming step.
Ions diffused into the silicon substrate by heat treatment
The shallow region of the second conductivity type is formed on the surface of the silicon substrate
Is done.

Therefore, even if the energy of the implanted ions is relatively large compared to the element size, the second conductivity type region can be formed shallowly on the surface of the silicon substrate.

Further , the ONO film has a larger thickness than the silicon oxide film.
Since the ions are difficult to permeate, the implanted ions are
Shut off and hold in minutes.

Further, the ONO film is compared with the silicon oxide film.
It can be formed thin. Therefore, the small size of the element
Can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is another diagram showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is still another view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is still another view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention.

FIG. 5 is still another view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device according to a conventional method.

[Explanation of symbols]

 2 p-type silicon substrate 20 ONO film 24 gate electrode 26 low-concentration n-type impurity diffusion layer

Claims (1)

(57) [Claims] 1. The method according to claim 1, wherein the surface of the silicon substrate of the first conductivity type is
ONO which has the property that the implanted ions are difficult to permeate
Forming an ONO film; forming a conductive film on the ONO film; forming a conductive film on the ONO film;
Implanting ions of the second conductivity type into the ONO film by heat treatment.
Diffuses into the silicon substrate of the first conductivity type
Forming a second conductivity type region for forming a region.
A method for manufacturing a semiconductor device, comprising: