JP4146121B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a MOS structure field effect semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device constituting a semiconductor integrated circuit such as a voltage regulator, a switching regulator, a voltage detector, etc. It relates to a manufacturing method. In addition, the present invention relates to a semiconductor integrated circuit device through which a plurality of voltages are input and output and a manufacturing method thereof.
[0002]
[Prior art]
  Conventionally, multiple power supply voltages are applied to a single semiconductor device.AdditionOr multiple output voltageOutputThings have been done. This creates another semiconductor device with different processes on the same substrateWhenNecessary. This complicates the device configuration and process flow of the semiconductor device, increases the number of management elements and the number of processes, and causes adverse effects such as an increase in production TAT (Turn Around Time) and an increase in production cost.
[0003]
  In order to eliminate such harmful effects, it is well known to use a manufacturing method such as dual gate and application of a channel stopper to a high voltage element.
[0004]
  This manufacturing method is based on the drawings below.ZAnd explain.
[0005]
  9 to 11 are schematic sectional views in order of manufacturing steps of a conventional method for manufacturing a semiconductor device.
[0006]
  Pwell 2 and Nwell 16 are formed in the vicinity of the surface of the P-type semiconductor substrate 1 (hereinafter referred to as Psub1) using a photo process, an ion implantation process, and a thermal diffusion process, and then a thick oxide film 19 for element isolation, an N-type channel stopper 15 and P The mold channel stopper 14 is formed using a LOCOS method, an ion implantation process, a photo process, etc., the oxide film 20 is formed using thermal oxidation, and the photoresist 5 is formed on the channel region of a region that will be a high voltage driving element in the future. Then, a thin oxide film in other regions is removed by wet etching. Thus, the structure of FIG. 9 is obtained. Subsequently, after removing the photoresist 5, a high voltage thick gate oxide film 22 and a low voltage thin gate oxide film 23 are formed again by thermal oxidation. Thus, the structure of FIG. 10 is obtained.
[0007]
  Here, the thickness of the gate oxide film is set so that the electric field applied to the gate oxide film does not exceed 4 MV / cm.
[0008]
  Next, a Poly-Si gate 3 is formed using a CVD process, a photo process, an etching process, etc., and an N + source 11, an N + drain 10, a P + source 18, and a P + drain 17 are formed in each element as a photo process and an ion, respectively. It is formed using an implantation process or the like. Thus, the structure of FIG. 11 is obtained.
[0009]
  Thereafter, although not shown, an interlayer insulating film, a contact hole, a metal wiring, an external connection PAD, and a protective film are formed using a normal semiconductor manufacturing process. Thus, the conventional semiconductor device is completed.
[0010]
  Furthermore, as a semiconductor device using the Dual Gate process, there is a single poly structure nonvolatile memory element.
[0011]
  This manufacturing method will be described below.
[0012]
  FIG. 18 is a schematic cross-sectional view of a conventional semiconductor device.
[0013]
  After the Pwell 202 is formed near the surface of the semiconductor substrate 201 using a photo process, an ion implantation process, and a thermal diffusion process, an element isolation oxide film 205 and a channel stopper 209 are formed using a LOCOS method, an ion implantation process, a photo process, and the like. Then, the tunnel drain region 204 is formed using a photo process and an ion implantation process, the gate oxide film 206 is formed using thermal oxidation, and a photoresist is formed on a channel region other than a region that will become the tunnel oxide film 207 in the future. Then, the gate oxide film in the region that will become the tunnel oxide film 207 in the future is removed by wet etching. Subsequently, after removing the photoresist, a tunnel oxide film 207 is formed again by thermal oxidation. Next, the select gate electrode 213 and the floating gate electrode 208 are formed using a CVD process, a photo process, an etching process, etc., and the N + regions 203 are ionized in a self-aligned manner on the select gate electrode 213 and the floating gate electrode 208, respectively. It is formed using an implantation process or the like. Thus, the structure of FIG. 18 is obtained.
[0014]
  Thereafter, although not shown, an interlayer insulating film, a contact hole, a metal wiring, an external connection PAD, and a protective film are formed using a normal semiconductor manufacturing process. Thus, the conventional semiconductor device is completed.
[0015]
[Problems to be solved by the invention]
  However, in the conventional semiconductor device, the low voltage element has the following structural problems because the channel stopper formed by the LOCOS method and the ion implantation process is used for the source and drain.
[0016]
  As shown in FIGS. 9 to 11, the high-voltage elements 23 and 24 use the source and drain formed by the LOCOS method and the ion implantation process, and thus have the disadvantage that the element size is structurally increased. Was.
[0017]
  Here, the LOCOS method and the ion implantation process will be described. In general, in the LOCOS method, a nitride film having a high heat-resistant oxidation masking property is formed in a region that will become an active region in the future by using a photo process and an etching process, and an N-type channel stopper and a P-type channel stopper in the future. After forming the impurity regions of the p-type and p-type using the photo process and the ion implantation process, the element isolation thick oxide film and the n-type channel stopper and the p-type channel stopper are thermally oxidized and thermally diffused (for example, 1100 degrees, This is a manufacturing method in which the element isolation region and the active region are formed by removing the vaginalized film and the oxide film on the active region.
[0018]
  As described above, when the N-type channel stopper and the P-type channel stopper formed by such a LOCOS method or the like are also used for the source and drain of a high-voltage element, it is difficult to reduce the size of the element structure. As shown in FIG. 11, a thick oxide film 19 that also serves as an element isolation region is required on both sides of the high-voltage thick gate oxide film 22, and the element size including the channel region, the source region, and the drain region is increased. It was difficult to suppress.
[0019]
  Further, in the conventional semiconductor device and the manufacturing method of the semiconductor device, two types of gate oxide films are required according to the applied voltage, and the following manufacturing problems are involved.
[0020]
  Since the high-voltage thick gate oxide film 22 is formed by two thermal oxidation processes, as shown in FIGS. 9 to 11, the variation in film thickness increases. This is because hydrogen peroxide containing ammonia is generally used in the pre-cleaning step of the second thermal oxidation step, and this cleaning solution partially etches and removes the oxide film surface when cleaning the oxide film surface. Therefore, the etching amount varies depending on the state of the cleaning solution, and the underlying oxide film thickness before the second thermal oxidation varies. As a result, the film thickness variation of the high-voltage thick gate oxide film 22 increases. That is. Such a variation causes the threshold voltage and drive current value of the high-voltage element to vary, degrading the characteristics of the semiconductor integrated circuit device, making it difficult to improve the accuracy of the characteristics of the semiconductor integrated circuit device. It was something to be made.
[0021]
  In addition, the nonvolatile memory element has a problem that the controllability of the film thickness is poor in the thick gate oxide film because of the structure in which the tunnel oxide film and the gate oxide film have different thicknesses. .
[0022]
[Means for Solving the Problems]
  Therefore, the present invention uses the following means in order to solve the above problems.Of the first conductivity typeA first step of forming a polycrystalline silicon gate in the vicinity of the semiconductor substrate surface via a gate insulating film;The surface of the semiconductor substrate in the internal region in the region in the gate electrode in the vicinity of the region where the gate electrode is in contact with the gate oxide film, and in the internal region of the semiconductor substrate outside the both ends of the gate electrode From the surface of the semiconductor substrate in the first impurity region formed in a later step so that the depth is less than or equal to the junction depth from the surface of the semiconductor substrate.A second step of implanting oxygen ions to form an oxygen ion implanted region; and annealing the oxygen ion implanted region at a high temperatureForming an oxide film in an internal region of the semiconductor substrate, and making the region in the gate electrode and the gate oxide film the same oxide filmIn a third step and in self-alignment with the gate electrodeThe second conductivity type impurity is introduced, the second conductivity type first impurity region is embedded, and the oxide film formed in the inner region of the semiconductor substrate is buried below the first impurity region. Shallow than the depth of the oxide film formed in the internal region of the semiconductor substrateA fourth step of forming and spaced from the gate electrodeSecond conductivity typeImpurities are introduced and high concentrationOf the second conductivity typeA fifth step of forming a second impurity region;The manufacturing method of the semiconductor device which has this.
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[0025]
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[0027]
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[0028]
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[0029]
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[0030]
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[0031]
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[0032]
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[0033]
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[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
  As described so far, in the present invention, the oxygen ion implantation process and the annealing process are applied to the method of manufacturing a semiconductor device, and therefore, the miniaturization and high accuracy of the high voltage element are promoted.
[0035]
  Embodiments of the present invention will be described below with reference to the drawings.
[0036]
  This embodiment shows a case where the present invention is applied to a high-voltage N-type MOSFET device and a low-voltage N-type MOSFET device formed on the same semiconductor substrate. The manufacturing method of this example is shown in FIG. First, as shown in FIGS. 1 to 4, Pwell 2, element isolation thick oxide film 19, and polycrystalline silicon gate electrode 3 are provided on Psub 1 using a conventional integrated circuit manufacturing method.
[0037]
  The detailed manufacturing method is as follows. Boron ions are implanted in the vicinity of the surface of Psub1 and annealed at 1000 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute boron ions, and an impurity concentration of 1 × 10¹⁶cm^-3About Pwell2 is formed. Subsequently, B + ions are implanted into a region patterned with a nitride film or the like, and a P-type channel stopper 14 and a field insulating film 26 are formed by a LOCOS method.
[0038]
  Thereafter, ion implantation for controlling the threshold voltage into a desired channel region, formation of a gate oxide film 4 having a thickness of 10 to 30 nm by a thermal oxidation method, and a polysilicon film having a thickness of 100 to 500 nm by a low pressure CVD method or the like. A polysilicon film is formed by forming and ion implantation. Here, a tungsten silicide film having a thickness of about 100 to 200 nm is formed on the polysilicon film by sputtering or the like, and an oxide film having a thickness of about 100 to 300 nm is formed on the tungsten silicide film by low pressure CVD or the like. Sometimes it is done. Then, the poly-Si gate 3 is formed by patterning the polysilicon film. Here, there is a case where an oxide film is formed to a thickness of about 10 to 50 nm on the upper portion of the gate electrode 3, the side wall portion, the semiconductor substrate surface portion or the like by using a thermal oxidation method or a low pressure CVD method. The structure shown in FIG. 1 is obtained through the steps up to here.
[0039]
  Thereafter, as shown in FIG. 2, oxygen ion implantation is performed in the region near the gate oxide film 4 of the Poly-Si gate 3 in the region that will be a high-voltage element in the future and outside the both end portions of the Poly-Si gate 3. Then, oxygen ions are selectively implanted into the Pwell 2 using the photoresist 5 to form an O ion implantation region 21. The acceleration energy of oxygen ion implantation here is set so that an oxygen ion concentration peak occurs in a region near the gate oxide film 4 of the Poly-Si gate 3. Further, the thickness of the Poly-Si gate 3 is such that the depth of the O ion implantation region 21 in the Pwell 2 from the vicinity of the Pwell 2 surface is less than or equal to the junction depth from the vicinity of the Pwell 2 surface of the N-region 6 to be formed in the future. It is desirable to set so as to be formed.
[0040]
  Thereafter, an annealing process at a high temperature is performed. At this time, the O ion implantation region 21 in the Poly-Si gate 3 and the gate oxide film 4 become the same oxide film by annealing and a thick oxide film 20 is formed, and the O ion implantation region 21 in the Pwell 2 becomes an oxide film. An oxide film 7 embedded in Pwell 2 is formed.
[0041]
  On the other hand, an oxide film is not newly formed in the low voltage element region where oxygen ions are not implanted.
[0042]
  Then, N-regions 6 are formed shallower than the oxide film 7 by implanting N-type impurities into the Poly-Si gate 3 in a self-aligned manner. Further, the N− region 6 is simultaneously formed in the low voltage element region. However, it is also possible to separate the N− region 6 concentration between the high voltage element and the low voltage element by using another mask. Thus, the structure of FIG. 3 is obtained.
[0043]
  Next, the N + region 8 is formed by ion implantation of N-type impurities at a high concentration. The N + region 8 is simultaneously formed in both the high voltage element and the low voltage element. All impurity regions have an impurity concentration of 1 × 10²¹cm^-3To the extent. Thus, the structure of FIG. 4 is obtained.
[0044]
  Finally, although not shown, a phosphorus glass layer is formed as an interlayer insulator as in the case of manufacturing a conventional integrated circuit. For example, a low pressure CVD method may be used to form the phosphorus glass layer. As a material gas, monosilane SiH₄And oxygen O₂And phosphine PH₃Obtained by reacting at 450.
[0045]
  Thereafter, a hole for forming an electrode is formed in the interlayer insulating film to form an aluminum electrode. Thus, a high-voltage N-type MOSFET device and a low-voltage N-type MOSFET device are completed on the same semiconductor substrate.
[0046]
  The semiconductor device thus obtained (Fig.5) Has an oxide film 7 buried under the N-region 6 of the high-voltage element. Therefore, even if a high voltage is applied to the drain, the depletion layer spreads downward in the N-region 6 used as the drain. Therefore, the short channel effect that hinders the short channel and high voltage driving of the transistor is suppressed, and a small high voltage driving element can be realized.
[0047]
  Furthermore, if the oxygen ion implantation process is made highly precise, a thick gate oxide film with little variation in film thickness can be formed even when a dual gate is used, and high precision of the semiconductor device can be realized.
[0048]
  Further, FIGS. 6 to 8 show sectional views in order of manufacturing steps of the semiconductor device when the oxygen ion implantation position is set in the vicinity of the gate oxide film 4 of Pwell 2.
[0049]
  In this case, the semiconductor device of the present invention can be formed using a process similar to the process described in the description of FIGS. However, regarding the setting of the oxygen ion implantation energy, it is necessary to set the oxygen ion concentration peak in the vicinity of the gate oxide film 4 in the Pwell 2.
[0050]
  Up to this point, an N-type MOSFET device has been described, but a P-type MOSFET device can also be formed by a similar manufacturing method with the conductivity type reversed.
[0051]
  Further, a complementary MOSFET device (CMOS device) can also be formed by combining an N-type MOSFET device manufacturing method and a P-type MOSFET device manufacturing method.
[0052]
  In the present invention, the oxygen ion implantation process and the annealing process are applied to a method of manufacturing a semiconductor device. So far, the downsizing and high accuracy of the high voltage element have been described. After that, an embodiment in which the present invention is applied to element isolation will be described.
[0053]
  Embodiments of the present invention will be described below with reference to the drawings.
[0054]
  In this embodiment, a case is shown in which the present invention is used for an element isolation element that separates an N-type MOSFET device and a P-type MOSFET device formed on the same semiconductor substrate. The manufacturing method of this example is shown in FIGS. First, as shown in FIG. 12, Pwell 101 and Nwell 102 are provided on a P-type semiconductor substrate 100 using a conventional integrated circuit manufacturing method.
[0055]
  The detailed manufacturing method is as follows. Boron ions and phosphorus ions are selectively implanted in the vicinity of the surface of the P-type semiconductor substrate 100 and annealed at 1000 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute boron ions and phosphorus ions.¹⁶cm^-3About Pwell 101 and Nwell 102 are formed. Further, an implantation oxide film 113 is formed near the surface of the semiconductor substrate 100.
[0056]
  Thereafter, oxygen ions are selectively implanted into the Pwell 101 and the Nwell 102 near the surface of the element isolation oxide film 111 in the future using the photoresist 109 to form an O ion implantation region 110. To do. The acceleration energy of oxygen ion implantation here is set so that an oxygen ion concentration peak occurs in a region near the surface of Pwell 101 and Nwell 102. Here, the O ion implantation region 110 is desirably set so that most (about 3 sigma) O ions exist in the Pwell 101 and the Nwell 102.
[0057]
  Thereafter, an annealing process at a high temperature is performed as shown in FIG. At this time, the O ion implantation region 110 and the implantation oxide film 113 in the Pwell 101 and Nwell 102 become the same oxide film by annealing, and the O ion implantation region 110 in the Pwell 101 and Nwell 102 becomes an oxide film and is embedded in the surface of the Pwell 101 and Nwell 102. The element isolation oxide film 111 is formed. On the other hand, no new oxide film is formed in the region covered with the photoresist 109 not implanted with oxygen ions.
[0058]
  After that, as shown in FIG. 14, gate oxide film 112 having a thickness of 10 to 30 nm is formed by ion implantation for controlling the threshold voltage into a desired channel region and thermal oxidation after removing implant oxide film 113. Then, a polysilicon film having a thickness of 100 to 500 nm is formed by a low pressure CVD method or the like, and a high impurity concentration polysilicon film is formed by ion implantation or the like. Here, the formation of a tungsten silicide film having a thickness of about 100 to 200 nm by sputtering or the like on the high impurity concentration polysilicon film, and the oxidation of about 100 to 300 nm by the reduced pressure CVD method or the like on the tungsten silicide film. In some cases, a film is formed. Then, the gate electrode 106 is formed by patterning the polysilicon film. Here, there is a case where an oxide film is formed to a thickness of about 10 to 50 nm on the upper portion of the gate electrode 106, the side wall portion, the surface portion of the semiconductor substrate, etc. by using a thermal oxidation method or a low pressure CVD method. Thereafter, ion implantation is performed in a self-alignment manner on the gate electrode 106, the element isolation oxide film 111, and the photoresist, respectively, so that the P + source region 105, the P + drain region 104, the P + channel stopper 107, and the N + source region 103. , N + drain region 114 and N + channel stopper 108 are selectively formed. The structure shown in FIG. 14 is obtained through the steps up to here.
[0059]
  In this way, a semiconductor device composed of an N-type MOSFET device and a P-type MOSFET device formed on the same semiconductor substrate and an element isolation element that separates each of them is an element isolation by a LOCOS method that has been generally used conventionally. Therefore, the element isolation region can be easily reduced in size.
[0060]
  In the LOCOS method, a film such as Si3N4 having excellent oxidation resistance is selectively formed on a base oxide film, thermally oxidized at a high temperature of about 1000 ° C. to 1100 ° C., and then the oxide resistance film is removed to separate elements. This is a manufacturing method for forming an oxide region for an active region and an active region, but in this case, an end portion of the oxide film for element isolation is formed as a smoothly thinned region called a bird's beak due to oxygen wraparound, This has been an adverse effect on the miniaturization of the element isolation region.
[0061]
  However, according to the present invention, oxygen for supplying an oxide film for element isolation in the future can be supplied by ion implantation, so that the active region is not oxidized by the oxygen wraparound. For this reason, the active region and the element isolation region are steeply divided, and the element isolation region can be easily downsized.
[0062]
  Furthermore, the steep step originally causes a problem in the flattening of the wiring layer and interlayer film to be formed thereafter, but in the present invention, since the steep step is embedded in the semiconductor substrate, There is no step at the top that would be harmful to this process. For this reason, the process increase for planarization is not brought about in the subsequent process.
[0063]
  Although the steps after FIG. 14 are not shown, an interlayer film is formed on the surface portion, a contact region is formed, a metal wiring is formed, a protective film is then formed, and a window for electrical connection is opened. The semiconductor device is completed.
[0064]
  In the following description, since the oxygen ion implantation process and the annealing process are applied to the method for manufacturing a nonvolatile memory type semiconductor device, the nonvolatile memory element is promoted to be downsized and highly accurate.
[0065]
  Embodiments of the present invention will be described below with reference to the drawings.
[0066]
  This embodiment shows a case where the present invention is applied to an analog / digital signal control MOSFET device and a nonvolatile memory MOSFET device formed on the same semiconductor substrate. The manufacturing method of the present embodiment is shown in FIGS. First, as shown in FIG. 15, a Pwell 202, an element isolation oxide film 205, a channel stopper 209, a tunnel oxide film 207, a select gate electrode 213, a floating structure are formed on a semiconductor substrate 201 using a conventional integrated circuit manufacturing method. A gate electrode 208, a tunnel drain 204, a photoresist 210 for O ion implantation, and an oxygen ion implantation region 211 are provided.
[0067]
  The detailed manufacturing method is as follows. Boron ions are implanted in the vicinity of the surface of the semiconductor substrate 201 and annealed at 1000 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute boron ions.¹⁶cm^-3About Pwell 202 is formed. Subsequently, B + ions are implanted into a region patterned with a nitride film or the like, and a channel stopper 209 and an element isolation oxide film 205 are formed by LOCOS.
[0068]
  Thereafter, phosphorus or arsenic ions for forming a tunnel drain into a desired region, formation of a tunnel oxide film 207 having a thickness of 5 to 12 nm by a thermal oxidation method (dilution wet), and a thickness of 100 to 500 nm by a low pressure CVD method or the like. The polysilicon film is formed, and the polysilicon film having conductivity such as ion implantation is formed. Here, a tungsten silicide film having a thickness of about 100 to 200 nm is formed on the polysilicon film by sputtering or the like, and an oxide film having a thickness of about 100 to 300 nm is formed on the tungsten silicide film by low pressure CVD or the like. Sometimes it is done. Then, the select gate electrode 213 and the floating gate electrode 208 are formed by patterning the polysilicon film. Here, there are cases where an oxide film of about 10 to 50 nm is formed on the select gate electrode 213 and the floating gate electrode 208, on the side walls, on the surface of the semiconductor substrate, etc. by using a thermal oxidation method or a low pressure CVD method. Thereafter, oxygen ion implantation is performed in the future in a region where a tunnel oxide film is not required (a region where no tunnel current flows), a region in the vicinity of the tunnel oxide film 207 in the floating gate electrode 208, and the select gate electrode 213. Then, oxygen ions are selectively ion-implanted into the Pwell 202 outside the both end portions of the floating gate electrode 208 by using a photoresist 210 to form an O ion implantation region 211. Here, the acceleration energy of oxygen ion implantation is set so that an oxygen ion concentration peak occurs in the region of the select gate electrode 213 and the floating gate electrode 208 in the vicinity of the tunnel oxide film 207. Further, the thickness of the select gate electrode 213 and the floating gate electrode 208 is such that the depth of the O ion implantation region 211 in the Pwell 202 from the vicinity of the surface of the Pwell 202 is the same as the junction depth from the vicinity of the surface of the Pwell 202 of the N + region 203 to be formed in the future. It is desirable to set so as to be formed to a degree or less. The structure shown in FIG. 1 is obtained through the steps up to here.
[0069]
  Thereafter, as shown in FIG. 16, an annealing process at a high temperature is performed. At this time, the O ion implantation region 211 and the tunnel oxide film 207 in the select gate electrode 213 and the floating gate electrode 208 become the same oxide film by annealing, and the oxide film 212 is formed, and the O ion implantation region 211 in the Pwell 202 is formed. As a result, an oxide film 212 embedded in the Pwell 202 is formed.
[0070]
  On the other hand, no new oxide film is formed in the tunnel oxide film 207 region where oxygen ions are not implanted. N-type impurities are ion-implanted into the select gate electrode 213 and the floating gate electrode 208 in a self-aligned manner to form the N + region 203 shallower than the depth of the oxide film 212. Here, the N + region 203 is simultaneously formed in both the analog and digital signal control MOSFET device (not shown here) and the nonvolatile memory MOSFET device element. Thus, the structure of FIG. 16 is obtained.
[0071]
  Next, as described in FIG. 17, the N + region 203 is simultaneously formed in both the high voltage element and the low voltage element. All impurity regions have an impurity concentration of 1 × 10²¹cm^-3To the extent. Thus, the structure of FIG. 17 is obtained.
[0072]
  Finally, although not shown, a phosphorus glass layer is formed as an interlayer insulator as in the case of manufacturing a conventional integrated circuit. For example, a low pressure CVD method may be used to form the phosphorus glass layer. As a material gas, monosilane SiH₄And oxygen O₂And phosphine PH₃Obtained by reacting at 450.
[0073]
  Thereafter, a hole for forming an electrode is formed in the interlayer insulating film to form an aluminum electrode. Thus, analog and digital signal control MOSFET devices and nonvolatile memory MOSFET devices are completed on the same semiconductor substrate.
[0074]
  The memory element (FIG. 17) thus obtained is compared with the conventional nonvolatile memory cell (FIG. 18) in the region 214 through which the tunnel current flows, the region between the floating gate electrode 208 and the tunnel drain 204 (tunnel oxidation for the control gate). Since the oxide film 212 is buried under the select gate electrode 213 and the floating gate electrode 208 other than the film 216), the oxide film 212 is sufficiently thick even when a voltage is applied to the tunnel drain 204, and a tunnel current is not generated. A small nonvolatile memory element can be realized. Furthermore, if the oxygen ion implantation process is made more precise, a thick gate oxide film with little variation in film thickness can be formed even when the Dual Gate process is used for a memory element, and the tunnel oxide film that is not oxygen-implanted maintains high quality. Therefore, high accuracy of the semiconductor device can be realized.
[0076]
【The invention's effect】
  According to the present invention, it is possible to fabricate a MOSFET with excellent cost performance. In particular, the present invention is an effective method for diversifying operating voltages, driving higher voltages, miniaturizing and flattening element isolation regions, and increasing the accuracy of nonvolatile memory elements, which are expected to develop in the future.
[0077]
  Although the present invention has been described mainly with respect to silicon-based semiconductor devices, it is obvious that the present invention can also be applied to semiconductor devices using other materials such as germanium, silicon carbide, and gallium arsenide. Furthermore, in the present invention, reducing the resistance of the gate electrode also plays an important role. In addition to the silicon gate mainly described in the present invention, a material that can be oxidized by oxygen ion implantation and annealing is used as the gate electrode. Also good. In the embodiment, the manufacturing process of an NMOSFET on a P-type semiconductor substrate has been described. However, for manufacturing a thin film transistor (TFT) using a polycrystalline or single crystal semiconductor film formed on an insulating substrate such as quartz or sapphire. It will also be apparent that the present invention can be applied.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view in order of manufacturing steps of a method for manufacturing a semiconductor device of the present invention.
FIG. 2 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a schematic cross-sectional view of a semiconductor device of the present invention.
FIG. 6 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 7 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
8 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention. FIG.
FIG. 9 is a schematic cross-sectional view in order of the manufacturing process of a conventional method of manufacturing a semiconductor device.
FIG. 10 is a schematic cross-sectional view in order of the manufacturing process of a conventional method for manufacturing a semiconductor device.
FIG. 11 is a schematic cross-sectional view in order of the manufacturing process of the conventional method for manufacturing a semiconductor device.
FIG. 12 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 13 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 14 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
15 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention. FIG.
FIG. 16 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 17 is a schematic cross-sectional view in order of the manufacturing process of the method for manufacturing a semiconductor device of the present invention.
FIG. 18 is a schematic cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
  1 Psub
  2 Pwell
  3 Poly-Si gate
  4 Gate oxide film
  5 photoresist
  6 N-region
  7 Oxide film
  8 N + region
  9 Depletion layer
10 N + drain
11 N + source
12 N-drain
13 N-source
14 P-type channel stopper
15 N-type channel stopper
16 Nwell
17 P + drain
18 P + source
19 Thick oxide film
20 Oxide film
21 O ion implantation region
22 Thick gate oxide film for high voltage
23 Thin gate oxide film for low voltage
24 High voltage element
25 Low voltage device
26 Field insulating film
27 Gate oxide film (silicon oxide)
100 P-type semiconductor substrate
101 Pwell
102 Nwell
103 N + source region
104 P + drain region
105 P + source region
106 Gate electrode
107 P + channel stopper
108 N + channel stopper
109 photoresist
1100 ion implantation region
111 Oxide film for element isolation
112 Gate oxide film
113 Implant oxide film
114 N + drain region
201 Semiconductor substrate
202 Pwell
203 N + region
204 Tunnel drain
205 Oxide film for element isolation
206 Gate oxide film
207 Tunnel oxide film
208 floating gate
209 Channel stopper
210 photoresist
211 Oxygen ion implantation region
212 Oxide film
213 Select gate
214 Area where tunnel current flows
215 Tunnel oxide film for control gate

Claims (1)

A first step of forming a gate electrode made of polycrystalline silicon via a gate oxide film above the surface of a first conductivity type semiconductor substrate; and in the gate electrode in the vicinity of a region where the gate electrode is in contact with the gate oxide film The depth of the internal region from the surface of the semiconductor substrate in the region outside and the internal region of the semiconductor substrate outside the both end portions of the gate electrode is a first impurity formed in a later step A second step of ion-implanting oxygen ions to form an oxygen ion-implanted region so that the region is less than or equal to the junction depth from the surface of the semiconductor substrate; and high-temperature annealing the oxygen ion-implanted region by, thereby forming an oxide film on the inner region of the semiconductor substrate, a third step of the said gate oxide film and the region in the gate electrode and the same oxide film, said gate electrode The oxidation of the first impurity region of a second conductivity type by introducing a self-alignment manner impurity of the second conductivity type, formed in the inner region of the semiconductor substrate below the first impurity region with respect to as the film is embedded, the fourth step of forming shallower than the depth of the oxide film, high doped with an impurity of a second conductivity type at a the gate electrode and the spacing formed inside a region of said semiconductor substrate And a fifth step of forming a second impurity region of the second conductivity type at a concentration.

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