JPH113996A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the short channel effect of a P-channel transistor having a buried channel, by a method wherein a semiconductor device is formed into a constitution, wherein the surface layer of a semiconductor substrate which is located under and electrode comprises a second nitrogen-containing impurity diffused layer containing first conductivity type impurities higher than that of impurities being contained in the substrate. SOLUTION: The threshold voltage of a P-channel transistor is controlled, and boron ions are implanted in the entire surface of the surface layer is a semiconductor substrate 1 at a prescribed dose via a sacrifice oxide film 6 to form a boron-containing impurity diffused layer 8 in the surface layer in the substrate 1. As a result, the junction depth between the surface layer and the layer 8 can be made shallow in comparison with the case where nitrogen ions are not implanted in the region to be formed with a buried channel of the transistor. That is, in the P-channel transistor to be formed with the buried channel, and the short channel effect of the transistor can be reduced by making shallow the channel region, resulting in the good electrical characteristics of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of manufacturing a CMOS semiconductor device using a common N-type polysilicon gate electrode as a gate electrode for both a P-channel MOSFET and an N-channel MOSFET. It is related to.

[0002]

2. Description of the Related Art In a CMOS semiconductor device, an N-type polysilicon gate electrode is commonly used as a gate electrode for a P-channel MOSFET and an N-channel MOSFET.
In this case, when a P-channel MOSFET is formed on an N-type substrate, the work function difference between the N-type substrate and the N-type polysilicon gate electrode is reduced, and the threshold value increases in the negative direction.

For this reason, in order to make the threshold value of the P-channel type MOSFET equal to the absolute value of the threshold value of the N-channel type MOSFET, the substrate surface is ion-implanted with an impurity of a conductivity type opposite to that of the substrate to reduce the absolute value of the threshold value. Need to be smaller. As a result, in a P-channel MOSFET using an N-type polysilicon gate electrode as an electrode, a very shallow pn junction is formed in the channel region, and the channel becomes a buried channel in which the channel is buried not in the substrate surface but inside the substrate.

The buried channel type device has an advantage that the mobility of carriers is larger than that of a surface channel type device, but has a serious disadvantage that a short channel effect is easily generated.

In order to solve this problem, Japanese Patent Laid-Open No. 7-161978
In the publication, an impurity is ion-implanted into an insulating film, and the impurity is introduced into the semiconductor substrate by thermal diffusion from the insulating film, whereby a buried channel region is formed at a shallow location near the surface of the semiconductor substrate. By doing so, a method for reducing the short channel effect of a P-type transistor having a buried channel has been proposed.

[0006]

In Japanese Patent Application Laid-Open No. 7-161978, ions are implanted so as to have a concentration peak in an insulating film of 15 to 30 nm. It is difficult to perform the implantation, and the thickness of the insulating film varies between wafer surfaces or between lots due to manufacturing variations, resulting in a variation in the concentration of impurities introduced into the semiconductor substrate. There is a problem that the variation in characteristics is increased.

An object of the present invention is to provide a manufacturing method for reducing the short channel effect of a P-type transistor having a buried channel without increasing the variation in the characteristics of a semiconductor device.

[0008]

In order to solve the above-mentioned problems, the present invention is as follows. Impurities such as B (boron) are ion-implanted on the semiconductor substrate to control the threshold voltage of the transistor and to form a buried channel of the P-type transistor. Before the ion implantation, nitrogen is implanted on the semiconductor substrate. Is ion-implanted to make the substrate surface amorphous.

The semiconductor device of the present invention is characterized in that an electrode formed on a first conductivity type semiconductor substrate containing either a P-type or an N-type impurity via an insulating film. And a pair of first and second impurities containing impurities of a conductivity type opposite to the first conductivity type in the semiconductor substrate on both sides of the electrode.
A surface layer of the semiconductor substrate below the electrode, wherein the surface layer of the semiconductor substrate below the electrode contains an impurity of the first conductivity type higher in concentration than the impurity contained in the semiconductor substrate. An impurity diffusion layer;
Is characterized in that nitrogen is mixed in the impurity diffusion layer.

The method of manufacturing a semiconductor device according to the present invention is characterized in that nitrogen ions are introduced into a surface layer of a semiconductor substrate containing impurities of a first conductivity type by ion implantation, And a step of forming a thermal oxide film on the semiconductor substrate into which the nitrogen and the impurities have been introduced.

Another feature of the present invention is that
Nitrogen is ion-implanted into a surface layer of the semiconductor substrate containing the first conductivity type impurity to make the surface of the semiconductor substrate amorphous, and the first conductivity type impurity having a higher impurity concentration than the semiconductor substrate. A first step of forming a first impurity diffusion layer containing at least one surface layer of the semiconductor substrate, and forming a gate oxide film on the semiconductor substrate, and then forming a first conductivity type impurity on the gate oxide film. A second step of forming a gate electrode made of a silicon film containing, and forming a pair of second impurity diffusion layers containing a second conductivity type impurity in the semiconductor substrate on both sides of the gate electrode. 3 is provided.

Another feature of the present invention is that a step of forming a thin film that can be conductive on the thermal oxide film, a step of patterning the thin film into an electrode shape, and a step of forming the electrode pattern are performed. Forming an impurity of a conductivity type opposite to that of the impurity in a surface layer of the semiconductor substrate which is not provided.

Another feature of the present invention is that the first conductivity type impurity is one of an N-type impurity and a P-type impurity.

[0014]

According to the present invention, nitrogen is ion-implanted into a semiconductor substrate to amorphize the substrate surface, and thereafter, is implanted to control the threshold voltage of the transistor and to form a buried channel of a P-type transistor. Impurity ions remain on the substrate surface. Therefore, the region where the buried channel of the P-channel transistor is formed can be made shallower than when nitrogen ions are not implanted, so that the short channel effect can be suppressed and a favorable semiconductor element can be formed. Becomes possible.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments. 1 and 2 are cross-sectional views showing a process flow of manufacturing a semiconductor device according to the present invention. First, FIG.
As shown in FIG. 2A, p ions of a dose of 1.0 to 2.0 × 10 ¹³ / cm ² are implanted into a p-type semiconductor substrate 1 having a specific resistance of about 10 Ω / cm ^{2 at} an energy of 150 keV.

In this state, a heat treatment for activating p ions implanted into the surface layer of the semiconductor substrate is performed to form an N-type well region 2 in the semiconductor substrate 1. Next, an oxide film 3 is formed to a thickness of about 15 nm by a thermal oxidation method.
A silicon nitride film 4 is deposited thereon to a thickness of about 150 nm by a CVD method. The silicon nitride film 4 formed on the element isolation formation region is removed.

Next, as shown in FIG. 1B, a field oxide film 5 having a thickness of about 450 nm is formed in the element isolation region using the silicon nitride film 4 patterned by the thermal oxidation method as a mask. After this thermal oxidation, the silicon nitride film 4 H ₃ PO
_{Use 4} to remove by wet etching. Next, the oxide film 3 in the element activation region is removed. In this state, sacrificial oxidation is performed by a thermal oxidation method to form an oxide film 6 having a thickness of about 15 nm.

Next, as shown in FIG. 1C, nitrogen ions (N.sup. ⁺ ) Are implanted into the surface layer of the semiconductor substrate 1 via the oxide film 6, thereby forming an amorphous layer 7 on the surface layer of the semiconductor substrate 1. Form. For example, this ion implantation energy is implanted at an energy of 50 keV and a dose of 2.0 * 10 ¹⁵ / cm ² . Thereby, the surface layer of the semiconductor substrate 1 in the element activation region can be made amorphous.

Thereafter, as shown in FIG. 2A, in order to control the threshold voltage of the P-channel transistor and to form a buried channel, B (boron) ions are added to the P-channel transistor for 10 to 10 hours.
By implanting ions at an energy of 15 keV and at a dose of 2.0 × 10 ¹² / cm ² through the sacrificial oxide film 6 over the entire surface layer of the semiconductor substrate 1, an impurity diffusion layer 8 containing boron is formed in the surface layer of the semiconductor substrate 1.

The impurity diffusion layer 8 controls the threshold voltage (V
t control). FIG. 1 (c)
Since the surface layer of the semiconductor substrate 1 in the element activation region has been made amorphous in the step, the implanted B (boron) ions remain in a shallow downward direction from the surface of the silicon substrate 1. Therefore, the impurity diffusion layer 8 having a shallow junction depth can be formed.

As a result, the junction depth of the region where the buried channel of the P-channel transistor is formed can be reduced as compared with the case where nitrogen ions are not implanted. That is, in the case of a P-channel transistor in which a buried channel is formed, a short channel effect of the transistor can be reduced by making the channel region shallow, so that favorable electric characteristics can be obtained.

Next, as shown in FIG. 2B, after removing the sacrificial oxide film 6, a gate oxide film 9 of about 7 to 15 nm is formed on the semiconductor substrate 1 in the element active region by a thermal oxidation method. I do. Thereafter, a polysilicon film 10 of about 300 nm containing p (phosphorus) as an impurity is deposited on the entire surface of the gate oxide film 9 by the CVD method.

Thereafter, a photoresist film (not shown) is formed on the polysilicon film 10, and then the photoresist is patterned into a line having a width of 0.8 μm or less, and the patterned photoresist is used as a mask. By etching the polysilicon film 10 using an etching method, a gate electrode shape made of the polysilicon film 10 is formed on the gate oxide film 9.

Next, using the gate electrode 10 as a mask, 5.0 × 10 ¹² / cm ² to 10 × 30 keV energy is applied to the semiconductor substrate 1.
B (boron) ions are implanted at a dose of about 3.0 × 10 ¹³ / cm ² to form a pair of impurity diffusion layers (LDD layers) 11 of the P-channel transistor on the semiconductor substrate 1 on both sides of the gate electrode 10.

After that, as shown in FIG. 2C, an oxide film 12 is deposited on the entire surface of the semiconductor substrate 1 by the CVD method, and the oxide film 12 is etched back, so that the oxide film 12 is formed on the side of the gate electrode. A sidewall oxide film 12 made of the oxide film 12 is formed. Then, using the gate electrode 10 and the sidewall oxide film 12 as a mask, BF ₂ ions are implanted into the semiconductor substrate 1 at an energy of 50 keV and at a dose of about 2.0 to 3.0 * 10 ¹⁵ / cm ² . Then, annealing is performed to activate the impurities, thereby forming a pair of impurity diffusion layers 13 serving as a source and a drain on the semiconductor substrate 1 on both sides of the gate electrode 10.

As described above, in the method of manufacturing a semiconductor device according to the present invention, in order to form a channel for controlling the threshold voltage of a transistor, B (boron) for threshold control (Vt control) is formed. Before ion implantation of impurities such as nitrogen, nitrogen is ion-implanted into the surface layer of the semiconductor substrate 1 to make the surface layer of the semiconductor substrate amorphous, thereby implanting nitrogen ions into the region where the buried channel of the P-channel transistor is formed. The junction depth can be made shallower than when not.

As a result, the short channel effect can be suppressed, and a good semiconductor device can be formed. In addition, since thermal diffusion from impurities taken into the insulating film is not used as in the related art, variations in the characteristics of the semiconductor element can be suppressed without being affected by variations in the thickness of the insulating film.

[0028]

As described above, according to the present invention, the short channel effect can be suppressed, and a good semiconductor device can be formed.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 N type well 3 Oxide film 4 Silicon nitride film 5 Field oxide film 6 Sacrificial oxide film 7 Amorphous layer 8 Impurity diffusion layer 9 Gate oxide film 10 Gate electrode 11 Impurity diffusion layer 12 Side wall oxide film 13 Source / drain

Claims (5)

[Claims] An electrode formed on a semiconductor substrate of a first conductivity type containing either a p-type impurity or an n-type impurity via an insulating film; and a semiconductor substrate on both sides of the electrode. In a semiconductor device comprising a pair of first impurity diffusion layers containing an impurity of a conductivity type opposite to a first conductivity type, a surface layer of the semiconductor substrate below the electrode is formed of an impurity contained in the semiconductor substrate. A semiconductor device, comprising: a second impurity diffusion layer containing an impurity of a first conductivity type higher in concentration than a second impurity diffusion layer, wherein nitrogen is mixed in the second impurity diffusion layer. 2. A step of introducing nitrogen ions into a surface layer of a semiconductor substrate containing impurities of a first conductivity type and introducing the impurities of the first conductivity type into a surface layer of the semiconductor substrate by an ion implantation method. And a step of forming a thermal oxide film on the semiconductor substrate into which the nitrogen and the impurities have been introduced. 3. The method according to claim 1, wherein nitrogen is ion-implanted into a surface layer of the semiconductor substrate containing impurities of the first conductivity type to make the surface of the semiconductor substrate amorphous, and that the first substrate has a higher impurity concentration than the semiconductor substrate. A first step of forming a first impurity diffusion layer containing an impurity of the conductivity type in a surface layer of the semiconductor substrate; forming a gate oxide film on the semiconductor substrate; and forming a first impurity diffusion layer on the gate oxide film. Forming a gate electrode made of a silicon film containing an impurity of the second conductivity type, and diffusing a pair of second impurities containing an impurity of the second conductivity type into the semiconductor substrate on both sides of the gate electrode. And a third step of forming a layer. 4. A step of forming a thin film that can be conductive on the thermal oxide film; a step of patterning the thin film into an electrode shape; and a step of forming the thin film on the surface of the semiconductor substrate on which the electrode pattern is not formed. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: forming an impurity of the opposite conductivity type. 5. The semiconductor device according to claim 2, wherein the impurity of the first conductivity type is one of an N-type impurity and a P-type impurity. Manufacturing method.