JP2012094874A - Photoelectric conversion device, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion device capable of reducing a leakage current and improving a numerical aperture of a photodiode.SOLUTION: A photoelectric conversion device has: a channel stop layer 105 formed of a second conductivity type semiconductor provided between a pair of adjacent photodiodes each having a region 102 formed of a first conductivity type semiconductor; an element isolation insulating film 103 provided on the channel stop layer 105; and an insulating film 104 provided on a surface of the photodiode and having a thickness thinner than that of the element isolation insulating film. In the photoelectric conversion device, an interface between the photodiode and the insulating film 104, and an interface between the channel stop layer 105 and the element isolation insulating film 103 exist on a plane at the same level. The first conductivity type semiconductor region 102 and the channel stop layer 105 are in contact with each other.

Description

  The present invention relates to a photoelectric conversion device, and an amplification type solid-state imaging device and system using the photoelectric conversion device, and to an imaging device and system such as a digital camera, a video camera, a copying machine, and a facsimile.

  Many image sensors in which solid-state imaging elements including photoelectric conversion elements are arranged one-dimensionally or two-dimensionally are mounted on digital cameras, video cameras, copying machines, facsimiles, and the like. Examples of the solid-state imaging device include a CCD imaging device and an amplification type solid-state imaging device.

  These image pickup devices tend to have a large number of pixels, and the photodiode area also tends to decrease as the area of one pixel is reduced. In particular, a MOS type solid-state imaging device has at least a photodiode in a unit pixel and a MOS transistor for reading out signal charges accumulated in the photodiode.

  FIG. 11 shows a cross-sectional structure of a conventional photodiode of a unit pixel. As shown in FIG. 11, an N-type region 203 made of an N-type semiconductor that constitutes a photodiode together with a P-type silicon substrate 200 is formed in a self-aligned manner with respect to a LOCOS (Local Oxidation of Silicon) oxide film 201 of element isolation. Thus, the area of the N-type region 203 corresponding to the area of the photodiode is increased to the limit. A P-type channel stop layer 202 is formed in advance under the LOCOS oxide film 201.

  However, when the N-type region 203 of the photodiode is formed in a self-aligned manner with respect to the LOCOS oxide film 201, the defect region 20 due to stress generated when the LOCOS oxide film 201 is formed is taken into the depletion layer of the photodiode. A large leakage current is generated.

  FIG. 12 shows a cross-sectional structure of another photodiode. A P-type channel stop layer 202 is formed in advance under the LOCOS oxide film 201. In this conventional example, the N-type region 203 constituting the photodiode is separated from the end of the LOCOS oxide film 201 so that the depletion layer 205 of the photodiode hardly contacts the defect region 20 from the defect region 20.

  However, in addition to the need for the distance L from the depletion layer 205 to the defect region 20, the N-type region 203 cannot be formed in a self-aligned manner with respect to the LOCOS oxide film 201. As a result, the area of the light receiving region of the photodiode is reduced. Therefore, as the pixels become finer, the ratio of (L + L ′) increases, and the aperture ratio of the photodiode is reduced.

  On the other hand, the sectional structure of another photodiode shown in FIG. 13 has a structure in which a P ++ layer 204 having a higher impurity concentration than the channel stop layer 202 is newly formed at the end of the LOCOS oxide film 201 to reduce the leakage current. However, not only the number of steps for forming the P ++ layer 204 is increased, but the P ++ layer 204 needs to completely cover the defect region 20, so that the area of the P ++ layer 204 occupying the photodiode is increased and sensitivity is lowered. Further, the breakdown voltage is reduced at the junction between the N-type layer 203 and the P ++ layer 204.

  Further, the bird's beak formed when the LOCOS oxide film 201 is formed is a cause that the aperture ratio of the photodiode cannot be improved.

  On the other hand, (a) of the nest 14 shows a cross-sectional structure of a PIN photodiode described in JP-A-55-154784. FIG. 14B shows an enlargement of the depletion layer in FIG. 14A. Specifically, phosphorus is implanted into the entire surface of the N-type high-resistance substrate 205 by ion implantation to form the low-resistance layer 206, and then the P + layer 208 of the light receiving portion is equivalent to the low-resistance layer 206 by boron diffusion. Form slightly deeper. Then, an N + type channel stopper 207 and an antireflection coating film 212 made of a nitride film for increasing the light receiving efficiency are formed. 211 is an oxide film. In addition, when the reverse bias is applied to the element of FIG. 14A, the spread of the depletion layer is indicated by 209 and 210 in FIG. 14B.

  However, there is no description about integrating a plurality of photodiodes.

  In the photoelectric conversion device and the amplification type individual imaging device using the photoelectric conversion device, it is desirable that noise other than the signal charge generated by the photoelectric effect in the unit pixel, that is, leakage current is as small as possible. Furthermore, since it is desirable that the distance between adjacent pixels is as small as possible, sufficient element isolation is required even if the distance between adjacent pixels is narrowed. Further, it goes without saying that the sensitivity of the pixel is not lowered.

  In the case where a LOCOS oxide film is used as the element isolation insulating film, a leak current is generated because a defect region caused by stress generated by the LOCOS oxide film is taken into the depletion layer of the photodiode. Furthermore, the bird's beak of the LOCOS oxide film cannot improve the aperture ratio of the photodiode.

  The present invention was invented in view of the above problems, and an object thereof is to provide a photoelectric conversion device capable of reducing leakage current and improving the aperture ratio of a photodiode.

  In order to solve the above-mentioned problem, the invention of claim 1 includes a channel stop layer made of a second conductivity type semiconductor provided between a pair of adjacent photodiodes having a region made of a first conductivity type semiconductor, In the photoelectric conversion device, comprising: an element isolation insulating film provided on the channel stop layer; and an insulating film provided on a surface of the photodiode and thinner than the element isolation insulating film. The interface with the insulating film and the interface between the channel stop layer and the element isolation insulating film are on the same level plane, and the semiconductor region of the first conductivity type and the channel stop layer are in contact with each other. It is characterized by that.

  In order to solve the above-mentioned problems, the invention of claim 6 is a pixel comprising a photodiode having a region made of a first conductivity type semiconductor and a MOS transistor having a source / drain region made of a first conductivity type semiconductor. Are arranged on a common semiconductor substrate, a channel stop layer made of a second conductivity type semiconductor formed between the photodiode and the MOS transistor, and on the channel stop layer An element isolation structure having an element isolation insulating film, and the element isolation insulating film provided on an interface between the channel stop layer and the element isolation insulating film and on the surface of the photodiode. The thinner insulating film and the interface between the photodiodes are on the same level plane.

  In order to solve the above-described problems, an invention according to claim 18 is directed to an imaging region in which a plurality of pixels each including a photodiode having a region made of a first conductivity type semiconductor are arranged, and a driving circuit for driving the pixels. And a peripheral circuit region in which a readout circuit for reading out signals from the pixel is formed on a common semiconductor substrate, an element isolation structure in the imaging region is formed between the elements. A channel stop layer made of a semiconductor of the second conductivity type, and an element isolation insulating film provided on the channel stop layer, and an interface between the channel stop layer and the element isolation insulating film And an interface between the photodiode and the insulating film provided on the surface of the photodiode and thinner than the element isolation insulating film, and on the same level plane, The element isolation structure in the peripheral circuit region includes a second channel stop layer formed between the elements, and a second element provided on the channel stop layer and having a bottom surface deeper than the bottom surface of the element isolation insulating film. And an insulating film for isolation.

  As described above, according to the present invention, it is possible to provide a photoelectric conversion device and a solid-state imaging device that can reduce the leakage current of the photodiode and improve the aperture ratio of the photodiode.

Sectional drawing and top view of the photoelectric conversion apparatus of this invention Sectional view showing the inclusion relationship between the element isolation insulating film and the channel stop layer Sectional drawing and top view of another embodiment of the photoelectric conversion apparatus of this invention Sectional view showing the inclusion relationship between the element isolation insulating film and the channel stop layer Sectional drawing and top view of another embodiment of the photoelectric conversion apparatus of this invention Sectional drawing and top view of another embodiment of the photoelectric conversion apparatus of this invention Sectional drawing and top view of another embodiment of the photoelectric conversion apparatus of this invention Circuit configuration diagram using photoelectric conversion device of the present invention Configuration diagram of a solid-state imaging system using the photoelectric conversion device of the present invention Configuration procedure of photoelectric conversion device of the present invention Cross-sectional structure of a photodiode in a unit cell in a conventional amplifying MOS sensor Cross-sectional structure of a photodiode in a unit cell in a conventional amplifying MOS sensor Cross-sectional structure of a photodiode in a unit cell in a conventional amplifying MOS sensor Conventional PIN photodiode

(Embodiment 1)
FIG. 1 is a schematic diagram illustrating a configuration of one pixel of the photoelectric conversion device according to the first embodiment of the present invention. FIG. 1B shows a planar structure of the photoelectric conversion device of this embodiment, and FIG. 1A shows a cross-sectional structure taken along the line QQ ′ of FIG. Further, FIG. 1 shows only one pixel, but in an actual photoelectric conversion device, a large number of pixels having such a structure are adjacently arranged in a one-dimensional or two-dimensional manner. In FIG. 1, 101 is a P-type substrate, 102 is an N-type region made of an N-type semiconductor as a photodiode having a region made of a first conductivity type semiconductor, and 105 is a first provided between a pair of adjacent photodiodes. A P + type channel stop layer that is darker than the P type substrate 101 as a channel stop layer made of a two-conductivity type semiconductor; 103 is a mesa-type element isolation insulating film provided on the channel stop layer 105; Reference numeral 104 denotes an insulating film thinner than the element isolation insulating film 103 provided on the surface of the N-type region 102.

  In order to form this photodiode structure, first, a P + type channel stop layer 105, which will be provided between a pair of adjacent photodiodes later, is ion-implanted near the surface of the P-type substrate 101. Form. Next, the oxide film deposited by the CVD method is patterned into a mesa shape by anisotropic etching to form an element isolation insulating film 103 on the channel stop layer 105. Next, the N-type region 102 is ion-implanted near the surface of the P-type substrate 101 in a self-aligned manner with respect to the element isolation insulating film 103. Further, an insulating film 104 thinner than the element isolation insulating film 103 is formed on the surface of the N-type region 102 by thermal oxidation. Through the above procedure, the interface between the N-type region 102 and the insulating film 104 and the interface between the channel stop layer 105 and the element isolation insulating film 103 can be formed on the same level plane. Therefore, by not forming irregularities as in the LOCOS structure, a leakage current that flows when a defect region formed during the formation of the LOCOS oxide film is taken into the depletion layer of the photodiode, and a bird's beak of the LOCOS oxide film causes the aperture ratio of the photodiode Improved the problem that was lowering.

  Further, in the present invention, the channel stop layer 105 is devised so as to be in contact with the N-type region 102 without fail. For this purpose, when the element isolation insulating film 103 is formed on the channel stop layer 105, the end portion of the channel stop layer 105 is formed by anisotropic etching of an oxide film deposited by the CVD method. An element isolation insulating film 103 is formed so as to be formed outside the end portion of the isolation insulating film 103 by a length A along the interface direction. Further, since the N-type region 102 is formed by ion implantation in a self-aligned manner with respect to the element isolation insulating film 103, the end of the channel stop layer 105 has a length A longer than the end of the element isolation insulating film 103. Only the N-type region 102 is formed inside the light receiving surface, and the overlapping region has an overlap width A.

  This will be described in more detail with reference to FIG.

  FIG. 2 is a schematic diagram of a photoelectric conversion device having no overlap width A in the photoelectric conversion device of FIG. 2A shows a structure in which the channel stop layer 105 is formed immediately below the element isolation insulating film 103, and FIG. 2B shows the element isolation insulating film 103 in FIG. 2A. 3 shows a structure in which an alignment shift occurs when forming the film.

  Since the leakage current on the surface of the N-type region 102 depends on the width of the depletion layer in contact with the insulating film 104 or the element isolation insulating film 103, the width should be as narrow as possible. Ideally, as shown in FIG. 2A, the end of the channel stop layer 105 and the end of the N-type region 102 coincide with each other. At this time, the spread of the depletion layer in the vicinity of the interface is the narrowest and the flowing leakage current is also reduced. However, it is extremely difficult to form such a structure with good reproducibility. Actually, as shown in FIG. 2B, when the channel stop layer 105 and the element isolation insulating film 103 are formed, due to process factors such as an alignment shift, the process shown in FIG. Region X is formed. In the region X, since the width of the depletion layer cannot be sufficiently reduced, a slightly larger leakage current flows than when the channel stop layer 105 is not in contact with the N-type region 102. On the other hand, in order to prevent the depletion layer from coming into contact with the insulating film 104 or the element isolation insulating film 103, it is also possible to dispose the P + type channel stop layer 105 so as to cover the surface of the N type region 102. However, with this method, the sensitivity near the surface of the N-type region 102 decreases. Similarly, the sensitivity of the N-type region 102 decreases as the P + type channel stop layer 105 and the N-type region 102 overlap each other inward of the light receiving surface. Therefore, the overlap width A along the interface direction of the region formed by overlapping the channel stop layer 105 and the N-type region 102 inward of the light receiving surface is preferably as thin as possible along the interface direction, and further misalignment occurs. However, it is desired not to form the region X because they are separated from each other. Therefore, the overlap width A is such that the channel stop layer 105 and the N-type region 102 are always in contact with each other even when an alignment shift between the element isolation insulating film 103 and the channel stop layer 105 or a variation in processing dimension occurs. A value is determined. Further, the value of the overlap width A is preferably 0.05 μm to 0.3 μm in consideration of the balance between the leakage current suppression, the alignment error, and the aperture ratio.

  In this embodiment, the conductivity type of the overlap width A between the channel stop layer 105 and the N-type region 102 is displayed with the same conductivity type as that of the channel stop layer 105. For example, the concentration of the N-type region 102 is If the concentration is sufficiently higher than that of the channel stop layer 105, the conductivity type of the overlap width A becomes the same conductivity type as that of the N-type region 102. In that case, the end portion of the channel stop layer 105 coincides with the end portion of the N-type region 102.

  Further, the interface direction described in this specification is a plane including the interface between the N-type region 102 and the insulating film 104.

(Embodiment 2)
FIG. 3 is a schematic diagram illustrating a configuration of one pixel in the photoelectric conversion device according to the second embodiment of the present invention. FIG. 3B shows a planar structure of the photoelectric conversion device of this embodiment, and FIG. 3A shows a cross-sectional structure taken along line RR ′ of FIG. In order to reduce the leakage current more effectively, the depth of the insulating layer 104 and the N-type region 102 from the interface is the same conductivity type as the P + type channel stop layer 105 in the configuration of FIG. In this photoelectric conversion device, the P + layer 106 is formed by ion implantation over the entire surface of the N-type region 102 so as to be shallower than the channel stop layer 105. By this method, the N-type region 102 is completely surrounded by a P-type conductive semiconductor.

  3 shows only one pixel, an actual photoelectric conversion device has a large number of pixels having such a structure arranged adjacently in a one-dimensional or two-dimensional manner.

  In this photodiode structure, the P + layer 106 is ionized in a self-aligned manner with respect to the element isolation insulating film 103 near the surface of the P-type substrate 101 while the N-type region 102 is formed in the photodiode of the first embodiment. After being formed by implantation, it can also be formed by implanting ions in a self-aligned manner to the element isolation insulating film 103.

  In the present embodiment, in addition to the effects of the first embodiment, the P + layer 106 is further formed so that the depletion layer of the photodiode formed by the P-type substrate 101 and the N-type region 102 is in contact with the insulating film 104. Disappeared and no leakage current occurred.

  Further, in the present embodiment, similarly to the first embodiment, the channel stop layer 105 and the N-type region 102 have a region having an overlapping width A.

  This will be described in more detail with reference to FIG.

  FIG. 4 is a schematic diagram of a photoelectric conversion device that does not have the overlap width A in the photoelectric conversion device of FIG. 3. 4A shows a structure in which the channel stop layer 105 is formed immediately below the element isolation insulating film 103, and FIG. 4B shows the element isolation insulating film 103 of FIG. 4A. 3 shows a structure in which an alignment shift occurs when forming the film.

  As shown in FIG. 4A, the state in which the end of the channel stop layer 105 and the end of the N-type region 102 coincide with each other is ideal without reducing the sensitivity in the N-type region 102 most. It is extremely difficult to form such a structure with good reproducibility. In practice, as shown in FIG. 4B, when the channel stop layer 105 and the element isolation insulating film 103 are formed, due to process factors such as an alignment shift, the process shown in FIG. Region X is formed. As a result, a leak current flows. On the other hand, the greater the overlap width A between the P + type channel stop layer 105 and the N-type region 102, the lower the sensitivity of the photodiode. Therefore, it is better that the overlap width A is thinner along the interface direction. Therefore, the overlap width A is such that the N-type region 102 and the channel stop layer 105 are always in contact with each other even when an alignment shift or variation in processing dimensions occurs when the element isolation insulating film 103 and the channel stop layer 105 are formed. Such a value is required. Further, the value of the overlap width A is preferably 0.05 μm to 0.3 μm in consideration of the balance between the leakage current suppression, the alignment error, and the aperture ratio.

  In this embodiment, the conductivity type of the overlap width A between the N-type region 102 and the channel stop layer 105 is displayed with the same conductivity type as the channel stop layer 105. For example, the concentration of the N-type region 102 is If the concentration is sufficiently higher than that of the channel stop layer 105, the conductivity type of the overlap width A becomes the same conductivity type as that of the N-type region 102. In that case, the end portion of the channel stop layer 105 coincides with the end portion of the N-type region 102.

(Embodiment 3)
FIG. 5 is a schematic diagram showing a photoelectric conversion device according to Embodiment 3 of the present invention. Specifically, a plurality of pixels each including a photodiode and a MOS transistor having a source / drain region are arranged on a common semiconductor substrate. 2 shows a part of a unit pixel area in a photoelectric conversion device. FIG. 5B shows a part of the planar structure of the unit pixel region, and FIG. 5A shows a cross-sectional structure taken along line BB ′ of FIG. On the other hand, (c), (d), and (e) of FIG. 5 show the cross-sectional structure of the region Y in the cross section of TT ′ of (b) of FIG.

  In this embodiment, in the photoelectric conversion device, due to a problem of leakage current and an aperture ratio, an element isolation insulating film between a photodiode and a MOS transistor is formed by an isolation method that does not use LOCOS, and a plurality of pixels in a pixel are formed. A LOCOS oxide film 401 is formed on the insulating film for element isolation between the MOS transistors.

  In the present embodiment, the N-type region 102 made of an N-type semiconductor as a photodiode having a region made of a first conductivity type semiconductor and the photodiode and the MOS transistor adjacent to the photodiode are patterned in a mesa shape. An element isolation insulating film 103, a P + type channel stop layer 105, a P + layer 106 formed shallower than the channel stop layer 105 in the vicinity of the surface of the N type region 102, and an element isolation insulating layer on the surface of the N type region 102 Transfer MOS transistor 302 and amplification MOS transistor 303 as a MOS transistor having an insulating film 104 thinner than film 103 and a source / drain region made of a first conductivity type semiconductor, and a second conductivity type provided between the plurality of MOS transistors Channel stop as a second channel stop layer made of any semiconductor 402, a LOCOS oxide film 401 serving as a second element isolation insulating film provided on the second channel stop layer and having a bottom surface deeper than the element isolation insulating film 103, and the signal charge amplified by the amplification MOS transistor The output signal line 307 is configured. In this embodiment, a transfer MOS transistor and an amplification MOS transistor are used as the plurality of MOS transistors. However, a MOS transistor having a source / drain region such as a reset MOS transistor may be used.

  The signal charge photoelectrically converted in the N-type region 102 is transferred to the drain region 309 of the transfer MOS transistor 302 by applying a transfer signal to the gate line 304, and the potential of the gate portion 305 of the amplification MOS transistor 303 is changed. A voltage suitable for operation is supplied to the drain region 306 of the amplification MOS transistor 303, and an output corresponding to the voltage of the gate portion 305 is output to the signal line 307 connected to the source region 310. Yes.

  In the present embodiment, the interface between the element isolation insulating film 103 and the channel stop layer 105 and the interface between the P + layer 106 and the insulating film 14 on the surface of the N-type region 102 are on the same level plane.

  Furthermore, the present embodiment is characterized in that the LOCOS oxide film 401 and the channel stop layer 402 are arranged in the element isolation structure between the transfer MOS transistor 302 and the amplification MOS transistor 303, that is, the channel stop layer 402 and the amplification. The channel region between the source region 306 and the drain region 310 of the MOS transistor 303 is separated. As a result, since the channel width of the channel region of the amplification MOS transistor 303 can be maximized, the driving capability is also maximized.

  However, if the LOCOS oxide film 401 and the element isolation insulating film 103 are used in combination in the unit pixel region, a problem occurs in the region Y in FIG. The region Y is a joint region between the element isolation insulating film 103 and the LOCOS oxide film 401.

  As shown in FIG. 5C, even when there is no alignment misalignment in the region Y, the wiring polysilicon for forming the gate line 304 is likely to remain in a minute concave portion, which may cause a short circuit of the wiring. is there.

  Further, as shown in FIG. 5D, when the element isolation insulating film 103 and the LOCOS oxide film 401 are formed apart from each other due to misalignment in the region Y, the gate line 304 is caused to run in the gap. There is a possibility that an unnecessary MOS transistor is formed to induce a malfunction, and that the area is wasted.

  Further, as shown in FIG. 5E, when the LOCOS oxide film 401 and the element isolation insulating film 103 are formed so as to overlap each other in the region Y, unevenness increases when a wiring such as the gate line 304 is run. This makes it difficult to form fine wiring.

  Therefore, it is not preferable to use the element isolation insulating film 103 and the LOCOS oxide film 401 in combination in the unit pixel region.

  Further, in this embodiment, depletion is achieved by applying a negative voltage to the gate line 304 while photoelectric conversion is performed in the N-type region 102, thereby making the P-type substrate under the gate line 304 a relatively dense P-type. Since the layer is not in contact with the insulating film 104, no leakage current is generated.

  In addition, it is not necessary to consider the leakage current in the amplification MOS transistor 303 because the moment when the voltage is applied to the gate portion 305 of the amplification MOS transistor is momentary (compared with accumulation of charge in the light receiving region). This is because the influence of current is small.

(Embodiment 4)
FIG. 6 is a diagram showing a photoelectric conversion device according to Embodiment 4 of the present invention. Specifically, a photoelectric conversion device in which a plurality of pixels each including a photodiode and a MOS transistor having a source / drain region are arranged on a common semiconductor substrate is shown. 2 shows a part of a unit pixel region in a conversion device. 6 (b) shows a part of the planar structure of the unit pixel region, FIG. 6 (a) shows a cross-sectional structure between DD ′ in FIG. 6 (b), and FIG. 6C shows a cross-sectional structure between EE ′ in FIG.

  5 is different from FIG. 5 in that an element isolation structure between a plurality of MOS transistors, that is, an element isolation structure between a transfer MOS transistor 302 and an amplification MOS transistor 303 is provided for the problem of the third embodiment. This is that a P + type channel stop layer 308 is arranged as a channel stop layer made of a second conductivity type semiconductor.

  FIG. 6C shows a configuration in which the N-type region 102 and the source region 310 of the amplification MOS transistor 303 are arranged with an element isolation insulating film 103 and a channel stop layer 308 for element isolation. The interface between the P + layer 106 and the insulating film 104 on the surface of the N-type region 102 and the interface between the element isolation insulating film 103 and the channel stop layer 308 are formed on the same level plane. Conventionally, a LOCOS oxide film has been used as an insulating film for element isolation between a photodiode and an adjacent MOS transistor. However, with the configuration of this embodiment, leakage current is reduced, and The aperture ratio can be improved. 6 shows a structure in which a thin P + layer 106 having the same conductivity type as the channel stop layer 105 is formed on the surface of the N-type region 102, the P + layer 106 may be omitted.

  The electrical breakdown voltage between the N-type region 102 and the amplification MOS transistor 303 is determined by the distance between the N-type region 102 and the amplification MOS transistor 303. Since the N-type region 102, the drain region 309, and the source region 310 can all be formed in a self-aligned manner with respect to the element isolation insulating film 103, the channel stop layers 105 and 308 and the element isolation insulating film 103 are temporarily provided. Since the distance between the elements does not change even when the alignment shift occurs, a stable element isolation withstand voltage can be obtained, and fine processing with high accuracy is possible.

  On the other hand, FIG. 6A shows a structure in which the element isolation insulating film 103 and the channel stop layer 308 are arranged to isolate the transfer MOS transistor 302 and the amplification MOS transistor 303 from each other. In the present embodiment, the MOS transistor having the channel stop layer 308 and the source / drain regions and the source region, or the drain region, or the source region and the domain, rather than the overlapping width of the channel stop layer 105 and the N-type region 102. The overlapping width between the region and the channel region may be small. Furthermore, they may be formed apart without overlapping width.

  6A, when the transfer MOS transistor 302 and the amplification MOS transistor 303 are separated from each other, the end portion of the channel stop layer 308 is closer to the interface direction than the end portion of the element isolation insulating film 103. If formed on the outside, the channel region that reverses when a voltage is applied to the gate portion 305 of the amplification MOS transistor 303 becomes narrower. In other words, the driving capability of the amplification MOS transistor 303 is reduced by reducing the channel width.

  Further, when the end portion of the channel stop layer 308 is formed inside the element isolation insulating film 103 along the interface direction, the channel stop layer 308 and the source region or the drain region of the amplification MOS transistor 303 There is no overlap width between the source region and the channel region between the domain region and the channel region. As a result, since the channel width of the amplification MOS transistor 303 is maximized, the driving capability is also maximized.

  Therefore, in order not to reduce the driving capability of the amplification MOS transistor 303, it is desirable that the overlap width between the channel stop layer 308 and the amplification MOS transistor 303 be small or separated.

  Further, in this embodiment, depletion is achieved by applying a negative voltage to the gate line 304 while photoelectric conversion is performed in the N-type region 102, thereby making the P-type substrate under the gate line 304 a relatively dense P-type. Since the layer is not in contact with the insulating film 104, no leakage current is generated.

  In addition, it is not necessary to consider the leakage current in the amplification MOS transistor 303 because the moment when the voltage is applied to the gate portion 305 of the amplification MOS transistor is momentary (compared with accumulation of charge in the light receiving region). This is because the influence of current is small.

(Embodiment 5)
FIG. 7 is a diagram illustrating a photoelectric conversion apparatus according to Embodiment 5 of the present invention. This figure shows an imaging region in which a plurality of pixels each having a photodiode are arranged, and a peripheral circuit region in which a driving circuit for driving the pixel and a reading circuit for reading a signal from the pixel are formed. A photoelectric conversion device provided on a common semiconductor substrate is conceptually shown. FIG. 7B shows a planar structure of the photoelectric conversion device of this embodiment, and FIG. 7A shows an element arranged in the cross-sectional structure taken along CC ′ in FIG. 7B. An insulating film for separation is shown.

  The sensor chip substrate 501 of the photoelectric conversion device according to the present embodiment includes an imaging region 502 in which a plurality of pixels having photodiodes are arranged, and peripheral circuit regions 503 to 506 for driving the sensor. More specifically, 503 is a vertical shift register for sequentially driving the sensors, 504 is a horizontal shift register, 505 is a timing generator provided as needed, and 506 is an A / D converter provided as needed. . In actual driving, an amplifier or the like is also necessary, but this is not particularly shown in the conceptual diagram. Further, this embodiment shows an example of a sensor chip of a photoelectric conversion device, and the configuration in the sensor chip is not limited to this.

  In this embodiment, as shown in FIG. 7A, all of the imaging region 502 is isolated using the element isolation insulating film 103, and the other peripheral regions are isolated by the LOCOS oxide film 401. It is characterized by.

  The imaging region 502 is an element isolation insulating film that does not form a defect region or a bird's beak due to stress in element isolation between a photodiode and an adjacent element in consideration of a leakage current flowing into the photodiode and an aperture ratio. 103 is desirable. Furthermore, due to the problem of using the LOCOS oxide film 401 and the element isolation insulating film 103 in the unit pixel area as in the third embodiment, all elements for element isolation in the imaging area are used for element isolation. It is desirable to form the insulating film 103. On the other hand, since the LOCOS oxide film 401 can form each element in a self-aligned manner, the LOCOS oxide film 401 is superior to the element isolation insulating film 103 in terms of miniaturization. In the regions 503 to 506, it is desirable to form the LOCOS oxide film 401 between the elements.

  As a result, it was possible to realize a high S / N photoelectric conversion device in which the separation performance and integration of the peripheral circuits were improved while the leakage current of the pixels was reduced.

  On the other hand, if the imaging region 502 and the peripheral circuit regions 503 to 506 are all separated from each other by the element isolation insulating film 103, the number of processes is reduced as compared with the case where both the LOCOS oxide film 401 and the both are used together. There is merit in terms.

  FIG. 8 is a circuit configuration diagram of the photoelectric conversion device used in the present invention. In FIG. 8, the unit pixel includes a photodiode 31, a transfer MOS transistor 32, an amplification MOS transistor 33, a reset MOS transistor 34 that resets the gate electrode of the amplification MOS transistor 33, and a selection MOS transistor 35 that selects a photodiode. , Is composed of. In FIG. 8, the timing generator 505 and the A / D converter 506 are omitted. Although FIG. 8 shows a circuit in which 3 × 4 unit pixels are arranged, the number of pixels and the circuit configuration of the unit pixels are not limited to this in the present invention, and the scope of the present invention is not changed. Of course, various modifications can be made.

  FIG. 9 is a configuration diagram of a system of an imaging device using the photoelectric conversion device of each embodiment described above as the imaging device of the present invention. The image pickup apparatus forms an image with a barrier 1 that serves as a lens switch and a main switch, a lens 2 that forms an optical image of a subject on a solid-state image pickup device 4, a diaphragm 3 that changes the amount of light passing through the lens 2, and a lens 2. The solid-state imaging device 4 (corresponding to the photoelectric conversion device described in each of the above embodiments) for capturing the captured subject as an image signal, various corrections, clamps, and the like on the image signal output from the solid-state imaging device 4 The image signal processing circuit 5 for performing image data, the A / D converter 6 for performing analog-digital conversion of the image signal output from the solid-state image sensor 4, and various corrections are performed on the image data output from the A / D converter 6. Timing generating unit for outputting various timing signals to the signal processing unit 7, the solid-state imaging device 4, the imaging signal processing circuit 5, the A / D converter 6 and the signal processing unit 7 In constructed. Each circuit of 5 to 8 may be formed on the same chip as the solid-state imaging device 4. Also, an overall control / arithmetic unit 9 for controlling various computations and the entire still video camera, a memory unit 10 for temporarily storing image data, a recording medium control interface unit 11 for recording or reading on a recording medium, The solid-state imaging system includes a removable recording medium 12 such as a semiconductor memory for recording or reading image data, and an external interface (I / F) unit 13 for communicating with an external computer or the like.

  Next, the operation of FIG. 9 will be described. When the barrier 1 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 6 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the aperture 3, and the signal output from the solid-state imaging device 4 passes through the imaging signal processing circuit 5 to the A / D converter 6. Is output. The A / D converter 6 performs A / D conversion on the signal and outputs it to the signal processing unit 7. The signal processing unit 7 performs an exposure calculation by the overall control / calculation unit 9 based on the data.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 9 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 4, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens 2 is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens 2 is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 4 is corrected in the imaging signal processing circuit 5, further A / D converted by the A / D converter 6, and totally controlled through the signal processing unit 7. Accumulated in the memory unit 10 by calculation 9 Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 9. Further, the image may be processed by directly entering the computer or the like through the external I / F unit 13.

  Next, an example of a method for forming a mesa element isolation region used in the present invention will be described. FIG. 10 is a schematic cross-sectional view for explaining a method for forming a structure in which the element isolation insulating film 103 patterned in a mesa shape and the channel stop layer 105 and the N-type region 102 are in contact with each other with an overlap width A It is.

  After forming a thermal oxide film 602 on a P-type substrate 101 made of silicon, a resist pattern 603 is formed by an existing photolithography technique, and a channel stop layer 105 is selectively formed thereon by an ion implantation technique (FIG. 10 (a)).

  After the resist pattern 603 is removed, a CVD oxide film 605 is deposited by a low pressure CVD method. In addition, a resist pattern 606 is newly formed by a lithography technique. This lithography process is different from the lithography process for forming the channel stop layer 105, and there is a finite alignment gap Z in the alignment accuracy between these two layers (FIG. 10B). .

  Next, the CVD oxide film 605 is selectively anisotropically etched using a reactive ion etching apparatus to form an element isolation insulating film 103 made of a CVD oxide film. At this time, even if anisotropic etching is performed, if the conditions are set so that an appropriate taper angle is given to the side wall of the remaining element isolation insulating film 103, the element isolation insulation in the subsequent film formation and etching process is performed. Etching residue and the like on the sidewall of the film 103 can be avoided. In this etching, the thermal oxide film 602 in the region where the element isolation insulating film 103 is not left is completely etched. Thereafter, the resist pattern 606 is removed (FIG. 10C).

  Further, in order to perform ion implantation for threshold control in the element region, the sacrificial oxide film 608 is formed by thermal oxidation, and then ion implantation is performed. This step also serves as a densification step for the element isolation insulating film 103. The densification step is to apply heat to make the element isolation insulating film 103, which is a CVD field oxide film, a dense film ((d) in FIG. 10).

  Subsequently, the sacrificial oxide film 608 is removed by a wet etching method using an HF solution. At this time, both the width and height of the element isolation insulating film 103 are reduced. Thereafter, an insulating film 104 which is a thermal oxide film thinner than the element isolation insulating film 103 is formed by thermal oxidation (FIG. 10E). Even if there is a misalignment Z between the element isolation insulating film 103 and the channel stop layer 105, the end of the element isolation insulating film 103 is closer to the interface direction than the end of the channel stop layer 105. Thus, the position and dimensions of the resist pattern 606 are determined so as to be formed shorter by a length A.

  Thereafter, a gate line 304 and a drain region 309, which serve as the gate electrode of the MOS transistor, and an N-type region 102 are selectively formed in the element region on the P-type substrate 101 via the insulating film 104 (FIG. 10). (F)).

  According to the semiconductor device manufacturing method, the channel stop layer 105 is always formed under the element isolation insulating film 103 even when there is an alignment shift Z between the element isolation insulating film 103 and the channel stop layer 105. At the same time, the N-type region 102 and the channel stop layer 105 are in contact with each other with an overlap width A.

  Further, according to the method for manufacturing a semiconductor device, the interface between the element isolation insulating film 103 and the channel stop layer 105 and the interface between the N-type region 102 and the insulating film 104 are formed on the same level plane. It will be.

The plane at the same level here is a structure in which the lower interface of the element isolation insulating film 103 does not protrude extremely downward like the LOCOS oxide film. In practice, the N-type region 102 and the insulating film 104 The interface may be slightly deeper than the lower interface of the element isolation insulating film 103 due to the etching action in the manufacturing process, but this is also included in the category of a plane of the same level. As a specific numerical value, if the difference in depth between the lower interface of the element isolation insulating film 103 and the lower interface of the insulating film 104 is about 16.7 nm, the planes are at the same level. This value is a value that considers how much the interface between the N-type region 102 and the insulating film 104 is lowered at present.

DESCRIPTION OF SYMBOLS 1 Barrier 2 Lens 3 Diaphragm 4 Solid-state image sensor 5 Imaging signal processing circuit 6 A / D converter 7 Signal processing part 8 Timing generation part 9 Overall control and calculation part 10 Memory part 11 Recording medium control interface (I / F) part 12 Recording medium 13 External interface (I / F) section 20 Defective area 31 Photodiode 32 Transfer MOS transistor 33 Amplifying MOS transistor 34 Reset MOS transistor 35 Select MOS transistor 101 P-type substrate 102 N-type area 103 Element isolation insulating film 104 Insulating film 105 channel stop layer 106 thin P + layer 200 P-type silicon substrate 201 LOCOS oxide film 202 channel stop layer 203 N-type region 204 P ++ layer 205 N-type high-resistance substrate 206 low-resistance layer on the surface 207 N + -type channel Numeral 208 P + layer 209 of light-receiving section Spread of depletion layer near surface 210 Spread of light-receiving section 211 Thermal oxide film 212 Non-reflective coating film of light-receiving section 302 Transfer MOS transistor 303 Amplifying MOS transistor 304 Gate line 305 Gate section of amplifying MOS transistor 306 Drain region of amplification MOS transistor 307 Signal line 308 Channel stop layer 309 Drain region of transfer MOS transistor 310 Source region of amplification MOS transistor 401 LOCOS oxide film 402 Channel stop layer under LOCOS oxide film 501 Sensor chip substrate 502 Configure pixel portion 503 Vertical shift register 504 Horizontal shift register 505 Timing generator 506 A / D converter 602 Thermal oxide film 603 Resist Pattern 605 CVD oxide film 606 Resist pattern 608 Sacrificial oxide film

On the other hand, FIG. 14A shows a cross-sectional structure of a PIN photodiode described in Japanese Patent Laid-Open No. 55-154784. FIG. 14B shows an enlargement of the depletion layer in FIG. 14A. Specifically, phosphorus is implanted into the entire surface of the N-type high-resistance substrate 205 by ion implantation to form the low-resistance layer 206, and then the P + layer 208 of the light receiving portion is equivalent to the low-resistance layer 206 by boron diffusion. Form slightly deeper. Then, an N + type channel stopper 207 and an antireflection coating film 212 made of a nitride film for increasing the light receiving efficiency are formed. 211 is an oxide film. In addition, when the reverse bias is applied to the element of FIG. 14A, the spread of the depletion layer is indicated by 209 and 210 in FIG. 14B.

A first aspect for solving the above problem includes a photodiode, a transfer MOS transistor having a drain region to which a signal charge of the photodiode is transferred, and a gate electrode electrically connected to the drain region. In the photoelectric conversion device including the amplification MOS transistor, a channel stop layer is provided to sandwich the channel region of the amplification MOS transistor in the channel width direction of the amplification MOS transistor, and the gate electrode is provided on the channel region. A first portion provided on the channel stop layer and extending from the first portion in the channel width direction and positioned on the channel stop layer, and the first portion and the channel region A first insulating film is provided between the second portion and the channel stop layer. A second insulating film thicker than the first insulating film, which is deposited using a method, is provided, and the second insulating film is in a plane including a surface of the first insulating film on the channel region side. Further, it is characterized in that it protrudes to the second portion side from the channel stop layer side.
A second aspect for solving the above-described problem includes a photodiode, a transfer MOS transistor having a drain region to which a signal charge of the photodiode is transferred, and a gate electrode electrically connected to the drain region. In the photoelectric conversion device including the amplification MOS transistor, a channel stop layer is provided to sandwich the channel region of the amplification MOS transistor in the channel width direction of the amplification MOS transistor, and the gate electrode is provided on the channel region. A first portion provided on the channel stop layer and extending from the first portion in the channel width direction of the channel region, and the first portion and the second portion A first insulating film is provided between the channel region, the second portion, the channel stop layer, A second insulating film thicker than the first insulating film, which is deposited using a CVD method, is provided between the source region of the amplification MOS transistor and the channel stop layer of the second insulating film. It is arranged to a level deeper than the side surface.

According to a third aspect of the present invention, there is provided a photodiode, a transfer MOS transistor having a drain region to which signal charges of the photodiode are transferred, and a gate electrode electrically connected to the drain region. An amplifying MOS transistor, wherein a channel stop layer is provided to sandwich the channel region of the amplifying MOS transistor in the channel width direction of the amplifying MOS transistor, and the gate electrode is connected to the channel region A first portion provided on the channel stop, and a second portion extending from the first portion in the channel width direction of the channel region and positioned on the channel stop layer, and the first portion A first insulating film is provided between the second portion and the channel stop layer. A second insulating film thicker than the first insulating film is provided between the first insulating film and the second insulating film with respect to a plane including the surface of the first insulating film on the channel region side. A third insulating film that protrudes from the stop layer side to the second portion side and is between the second insulating film and the channel stop layer and is in contact with the channel stop layer and is thinner than the second insulating film. Is provided.

A fourth aspect of the present invention for solving the above problem is a method of manufacturing a semiconductor device comprising: an element region in which a MOS transistor is provided; and an element isolation region arranged adjacent to the element region. Forming a first insulating film in the element isolation region using a thermal oxidation method; forming a first semiconductor region under the first insulating film by ion implantation through the first insulating film; After forming the first semiconductor region, depositing a CVD oxide film on the first insulating film using a CVD method, processing the CVD oxide film to form an element isolation insulating film, Forming a second insulating film in the element region using a thermal oxidation method, and forming a gate electrode of the MOS transistor so as to extend from the second insulating film to the element isolating insulating film; Process and ions through the second insulating film Forming a second semiconductor region having a conductivity type opposite to that of the first semiconductor region under the second insulating film, the element isolation insulating film being thicker than the second insulating film. And it is formed so that it may protrude in the opposite side to the 1st semiconductor field rather than the 1st semiconductor field side to the plane containing the undersurface of the 2nd insulating film.

On the other hand, FIG. 6A shows a structure in which the element isolation insulating film 103 and the channel stop layer 308 are arranged to isolate the transfer MOS transistor 302 and the amplification MOS transistor 303 from each other. In the present embodiment, between the overlapping width, or the overlap width between the drain region and the channel stop layer 308, or the source region and the Drain-in area of the source region and the channel stop layer 308 of the MOS transistor having a source-drain region The overlap width between the channel region and the channel stop layer 308 may be smaller than the overlap width between the channel stop layer 105 and the N-type region 102 . Furthermore, they may be formed apart without overlapping width.

Claims (1)

A channel stop layer made of a second conductivity type semiconductor provided between a pair of adjacent photodiodes having a region made of a first conductivity type semiconductor, and an element isolation insulation provided on the channel stop layer In a photoelectric conversion device having a film and an insulating film provided on the surface of the photodiode and thinner than the insulating film for element isolation,
The interface between the photodiode and the insulating film and the interface between the channel stop layer and the element isolation insulating film are on the same level plane,
The photoelectric conversion device, wherein the first conductivity type semiconductor region and the channel stop layer are in contact with each other.

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