JPH02211623A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make a sum of thickness of an alloy layer and an impurity layer amount enough for low resistance processing to provide a shallow impurity layer and to realize a structure suitable for the low resistance processing by forming the alloy layer on a substrate surface, by making the layer have a composition rich in semiconductor and by performing heat treatment for the alloy layer. CONSTITUTION:Ge ions are implanted into a substrate 1 using a laminated film and a field SiO2 film 2 as a mask to form impurity implanted layers 51, 61. Then, a paradium Pd layer 41 is deposited for heat treatment to form Pd2Si layers 53, 63. If heat treatment is further carried out, the Pd2Si layers 53, 63 become PdSi layers 54, 64. B ions are thereafter implanted into form SiPi layers 55, 65 containing impurity. PdSi layers 55, 66 are subjected to partial phase conversion to form Pd2Si layers 57, 67. Although the silicon layers 56, 66 are formed shallow, the Pd2Si layer rises and becomes thick, thereby keeping resistance of a source/drain region low.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having a shallow impurity layer.

(Prior Art) In recent years, large-scale integrated circuits (LSI), which are formed by integrating a large number of transistors, resistors, etc. on a semiconductor substrate, have been frequently used in important parts of computers and communication equipment. Improving the degree of integration of this LSI is one of the recent important issues, and
Basic elements of SI such as field effect transistor (FET)
miniaturization is necessary. Therefore, the gate length of the FET is shortened to reduce the occupied area, but this requires forming the source/drain regions shallowly so as not to change the threshold voltage. A conventional method for forming such an FET will be described with reference to FIG.

One step later, a field oxide film (2) is formed on an n-type silicon substrate (1) having a (100) main surface and having a thickness of 4 to 5 Ωcm.

In the area surrounded by this oxide film ■, there is a gate oxide film (3□),
A stack of a doped polycrystalline silicon layer (3□), a tungsten silicide layer (33), and a SiO□ film (34) is etched into the shape of a gate electrode, and a 5in2 film (35) is further provided on the side wall. Form a gate electrode (■).

After that, the entire surface was covered with N1 (
41) by 300 people (Figure 6(a)).

Next, the entire substrate was exposed to N gas at 400° C. for 30 minutes to form two N15j layers (5□) and (6,).

By this heat treatment, N j , S i two layers (57), (
The bottom of the base substrate (6□) has an uneven shape and has a wide area.
1) (Fig. 1(b)).

Furthermore, B ions were accelerated at a voltage of 10 KeV and at a dose of 5.
NiSi was implanted over the entire surface under the condition of
Contain B ions in the second layer (5□) and (6□) (6th layer)
Figure (C)).

Thereafter, by exposing the entire substrate to N2 gas at 900°C for 30 minutes, the NiSi2 layers (5□), (6
,) B thermally diffuses below to form a P+ type layer (5G), (6,)
is formed.

In this way, a source region (c) and a drain region 0 are formed, and the FET is completed (FIG. 6(d)).

In this way, low resistance N
15x2 layers (5□) and (6G) are provided, and this N15j7 layer (5□).

(6□) is a P+ type layer (5,) with a wide area uneven bottom.
The structure of this FET is suitable for miniaturization because the source train region (c) and (0) are in contact with (6,), so the resistance of these regions remains low even when the (0) layer is thinned. .

However, after forming the NiSi2 layers (5□) and (6□), using this as a diffusion source, B is thermally diffused into the silicon substrate (υ) below, and the P+ type layers (5□) and (6□) are formed. In order to form this P+ type layer, the NiSi2 layer (5
g)', it is formed deeper than the position (6,). Therefore, the depth of such source/drain regions is the total thickness of the NiSi2 layer, which is an alloy layer, and the P+ type layer, which is an impurity layer.

Therefore, in order to form these source/drain regions shallowly, it is possible to reduce the total thickness of the impurity layers in the alloy layer, but if the total thickness of the impurity layers in the alloy layer is made thinner, the resistance of these regions increases, and it is necessary to make the layers thinner. It was extremely difficult to adapt. sauce·
Unless the drain region can be thinned, high integration and high speed of FETs cannot be expected.

(Problems to be Solved by the Invention) In conventional semiconductor devices, the total thickness of the alloy layer and the impurity layer of the conductivity type provided below is the depth of the source/drain region, so it is impossible to make the alloy layer any thinner than this. There was a problem in that the resistance in the tobacco area was high.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to easily form a semiconductor device having a structure suitable for forming a shallow impurity layer and reducing resistance.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an alloy layer made of constituent elements and metals of the first semiconductor layer on the first semiconductor layer. a step of forming the alloy layer with a composition rich in constituent elements; a step of including an impurity exhibiting a conductivity type in the alloy layer; The present invention provides a method for manufacturing a semiconductor device, comprising a step of depositing a second semiconductor layer containing the constituent elements of a first semiconductor layer and the impurities.

(Function) After forming an alloy layer on the surface of the substrate, this layer is made to have a composition of a semiconductor ridge, and this alloy layer is recrystallized by heat treatment. In this recrystallization process, a semiconductor that will become an impurity layer is deposited on the substrate. The bottom depth of this impurity layer is the same as the bottom depth of the first alloy layer and is not formed deeper than this. If a semiconductor component is intentionally added to an alloy and the above process is performed, the alloy layer will be formed to be higher than the first alloy layer, so the total thickness of the alloy layer and impurity layer will be low resistance. It maintains sufficient thickness for oxidation.

(Example) The details of the present invention will be explained along with examples.

FIG. 1 is a cross-sectional view showing a field effect transistor according to a first embodiment of the present invention in the order of manufacturing steps.

First, a semiconductor substrate, for example, 5Ω with (] 00) as the main surface.
0.6 μm by thermal oxidation on a cm n-type silicon substrate ■
Form a thick field oxide film. Surrounded by this film are a 100-layer thick 0 gate oxide film (3□), doped polycrystalline silicon (32), and a tungsten silicide (WSi2.s) film formed by DC magnetron sputtering (
33) and 500-person-thickness C1) CV D-5in2 films (34) are sequentially laminated and processed into a gate shape by etching. Next, using this laminated film and the field 5in2 film (2) as a mask, Ge ions were accelerated at a voltage of 30 keV, a dose of 5 x 1014 cm-2, and
BF2 ions are accelerated at a voltage of 10 keV and a dose of I
Injected into each substrate (1) under the condition of 10"cm-2,
00 person thickness C1 pure dopant injection layer (51).

Form (6,). Thereafter, a 0.1 μm thick 5in2 film (35) is formed on the side wall of the laminated film processed into the gate shape (FIG. 1(a)).

Next, a 1000-layer thick palladium (Pd) layer (41)
is deposited by, for example, DC magnetron sputtering (
Figure 1(b)).

Furthermore, by performing heat treatment at 300°C for 30 minutes, 1
A Pd2Si layer (5,l), (63) with a thickness of 400 layers is formed. (42) is the Pd layer that remained unreacted (FIG. 1(C)).

After that, this unreacted Pd layer (4□) is selectively removed with KI+I2 solution, and further heated to 730°C or higher, for example, 750°C.
, after 30 minutes of heat treatment, a Pd, Si layer (53),
Phase transition is performed so that (63) becomes PdSi layers (5,), (6,), and a silicon-rich film is formed again. At this time, the substrate (υ) is slightly eaten away, and the PdSi layer (5,), (64
) becomes somewhat deeper (Fig. 1(d)).

Next, the acceleration voltage was 10 keV, and the dose was I x 1.0.
B ions are implanted using "crn-" to form impurity-containing Pi.
Si layer (5S).

(6S) is formed (Fig. 1(e)).

After this, by performing heat treatment at 650°C for 60 minutes,
The PdSi layers (5,) and (6,) are subjected to anti-phase transposition, and the B-containing silicon layers (56) and (6G) are placed on the silicon substrate ω.
Pd2Si layers (5□), (6□) are precipitated on top.
form. 600 to 700 to achieve this reverse phase rearrangement.
°C is preferred. As a result, the P-type source region (2) and drain region (2) are completed. This silicon layer (5G), (
Since PdSi (55) and (6,) are precipitated using the silicon substrate (1) as a seed, the bottom shape and depth are almost the same as those of PdSi (55) and (6,).

Also, silicon layers (5,), (66) and Pd2Si layer (
Since the interface between 5□) and (6□) is uneven, the contact area between these layers is wide and suitable for lowering the resistance in the source/drain region.

When this unevenness was observed under a microscope, the depth from the peaks to the valleys was 100 Å or more.

In this way, the silicon layers (56) and (6,) are formed even though they are formed shallowly, so the Pd2Si layer rises and the total thickness of the silicon layer and the Pd2Si layer becomes thicker, and the source/drain regions are thicker. resistance is kept low (first
Figure (f)).

Finally, an interlayer insulating film of 5i was applied to the entire surface by CVD.
An FET is completed by forming an n2 film (1), providing openings on the source region 0 and drain region 0, and forming AQ electrode wiring (8) connected to the Pd2Si layers (57), (6,). Figure (g)).

When the cross section of the FET thus formed was examined using an electron microscope, it was found that the depth of the intermediate concentration layers (5□) and (6□) was 500 mm, and the source/drain regions were 0.5 mm deep. (2) was formed about 1000 times above the surface of the n-type substrate. In such an FET, the drain current can be made to flow into a shallow part of the silicon substrate, and the drain current can be easily controlled by the voltage applied to the gate.

As a result, the mutual conductance of a FET with a gate length of 0.5 μs has increased from 10,100 O/mm to 18
The speed was significantly improved to 00ms/mm.

Here, Fig. 2 shows that the PdSi layers (5,), (6,,) are subjected to anti-phase dislocation to form PdSi layers (5,), (6,) on the silicon layers (5,), (6,).
2Si layers (57) and (6□) are stacked to form the source and
When forming drain regions 0,0, PdSi layer (55)
, (65) shows the relationship between the thickness of these regions and the specific contact resistance of these regions.

-△- marks are those in which As ions were implanted into the PiSi layer before reverse phase dislocation under the conditions of acceleration voltage 45 keV and dose amount I
Injections at 0 keV and I x 1016 cm-2 are shown, respectively.

As is clear from this figure, the PdSi layer is 1100C]
As the thickness increases, the specific contact resistance increases.

From this, in order to keep the specific contact resistance low, it is preferable that the PdSi layer has a density of 1100 [people] or less.

In this embodiment, Pd is used as the metal capable of reverse phase transition, but other metals may also be used. Further, here, the alloy layer is made silicon-rich by phase transition, but in addition to this, the alloy layer may be made silicon-rich by ion implantation of silicon.

Next, a second embodiment of the present invention will be described with reference to FIG.

This differs from the first embodiment in that the metal silicide layer is made silicon-rich and that Co is used instead of Pd.

First, through the same steps as in FIGS. 1(a) to (c), Pd
CQS12 Ml (53) + (6
3) Form. c.

The film was deposited using DC magnetron sputtering. In addition, heat treatment was performed at 650° C. for 10 minutes for silicidation. Unreacted Co film was selectively removed with a mixture of hydrogen peroxide, hydrochloric acid, and water.

Next, S was applied to the CoSi two layers (53) and (63) at an accelerating voltage of 20 keV and a dose of I x 10'7 cm-2.
Silicon-rich cobalt silicide (5
, ), (64) are formed (Fig. 3(a)).

After that, B ions were implanted into the cobalt silicide layers (5,) and (6,) at an acceleration voltage of 15 keV and a dose of I x 10"6 cm-2 to form a B-doped cobalt silicide layer (5 g).
, (65) is formed. This step may be performed before implanting Si ions (FIG. 3(b)).

Furthermore, B-doped silicon layers (5,), (6r,) were precipitated using the silicon substrate ■ as a nucleus by heat treatment at 850°C for 1 hour in Ar gas, and CoSi2
Form layers (5□) and (6□). As a result, a P-type source region (2) and a drain region (0) are formed, and shallow source/drain regions similar to those of the previous embodiment are obtained (FIG. 3(C)).

After this, electrode wiring is provided in the same way as in Fig. 1(g), and the FET is
is completed. This FET is also excellent and has characteristics similar to those of the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIG.

This embodiment differs from the second embodiment described above in the method of making the metal silicide layer silicon-rich.

First, through the same steps as in Figures 1(a) to (c), CoS
Form i2 layers (53) and (63). In forming this film, the same conditions as in the second embodiment may be used.

Thereafter, using the LPCVD method, the partial pressure of silane was reduced to 5×10
-'Torr, temperature 500℃ condition, 300 people thickness 0
Silicon layers (59) and (6□) are replaced with CoSi2 layer (53)
, (63) selectively formed on (Fig. 4(a))
.

Next, for example, B ions are applied to the silicon layers (59) and (69) at an acceleration voltage of 20 keV and a dose of I x 10.
Inject under the condition of ``Cm-2'' (Fig. 4(b)).

Furthermore, by performing heat treatment at a temperature of 850°C for 1 hour in Ar gas, the C0807 layers (53) and (63) become silicon-rich and the excess silicon is transferred to the silicon substrate (1
), B-doped P-type silicon layers (5G), (6G) of I x 102-'Cm-'' are deposited, and CoSi2 layers (57), (6□) are formed on this layer. (Figure 4(C)).

Thereafter, through the same steps as in FIG. 1(g), an interlayer insulating film and electrode wiring are formed, and the P-channel type FET is completed.

This FET also has a P-type silicon layer (5
Since □) and (6□) are formed at shallow depths, they have similar excellent characteristics.

1]2 Figure 5(a) shows the transition from the cobalt silicide layer to the silicon layer (5G).
, (6G) is deposited to form source/drain regions ■.

(The results of measuring the specific contact resistance of these regions by changing the composition ratio of the cobal silicide layer when forming the cobal silicide layer are shown below.

−〇− marks accelerate BF2 ions into the cobalt silicide layer at a voltage of 4
Those implanted at 0 keV and a dose of I x 1016 cm-2, and -△- are similarly implanted with As ions at 50 keV.
, 1×10 16 cm −2 , respectively. As is clear from this figure, Si/Co is 2.5
As the contact resistance increases, the specific contact resistance increases. Therefore, in order to provide shallow and low resistance source/drain regions from a silicon-rich cobalt silicide layer, Si/G is used.

It was found that it is preferable that the value is 2 or more and 2.5 or less.

Further, in the present invention, Ni can be used instead of Pd or Co. FIG. 5(b) shows measurement results similar to those shown in FIG. 5(a) when an FET is provided using a nickel silicide layer instead of cobalt silicide. As is clear from this figure, even in the case of a silicon-rich nickel silicide layer, Si
/Nj ratio was found to be preferably 2 or more and 2.5 or less.

Although the MO8 type FET was described in the second embodiment, the present invention can also be applied to other FETs, such as Schottky gate type FETs, and can also be applied to devices other than FETs that require shallow diffusion layers, such as Pn junction diodes and bipolar FETs. It can also be used for transistors, etc. Although silicon is used for the substrate here, germanium or a compound semiconductor such as GaAs or InP may also be used. Furthermore, in addition to Pd, CO, etc., W'l'Ti may be used as the metal.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be practiced with various modifications without departing from the spirit thereof.

〔Effect of the invention〕

According to the present invention, it is possible to easily form a semiconductor device having a shallow impurity layer and having a structure suitable for reducing resistance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the first embodiment of the present invention in the order of steps;
Fig. 2 is a diagram explaining the first embodiment of the present invention, Fig. 3 is a cross-sectional view showing the second embodiment of the invention in the order of steps, and Fig. 4 is a diagram illustrating the third embodiment of the invention. 5 is a diagram for explaining the second and third embodiments of the present invention, and FIG. 6 is a sectional view of the conventional example in the order of steps. 1... Silicon substrate 3... Gate electrode 5... Source region 7... Interlayer insulating film 2... Field oxide film 4... Metal layer 6... Drain region 8... Electrode wiring substitute People Patent Attorney Nori Ken Yudo Matsuyama Mitsuyuki ＼－/ To

Claims (3)

[Claims] (1) forming an alloy layer made of the constituent elements of the first semiconductor layer and a metal on the first semiconductor layer with a composition rich in the constituent elements of the first semiconductor layer; and A step of including an impurity exhibiting a conductivity type in the layer, and then a second layer containing the constituent elements of the first semiconductor layer and the impurity from the alloy layer by heating between the first semiconductor layer and the alloy layer. A method for manufacturing a semiconductor device, comprising the step of depositing a semiconductor layer. (2) By causing the alloy layer to undergo reverse phase dislocation, the first
2. The method of manufacturing a semiconductor device according to claim 1, wherein the composition is rich in constituent elements of the semiconductor layer. (3) The composition of the alloy layer is made such that the constituent elements of the first semiconductor layer are rich by ion-implanting the constituent elements of the first semiconductor layer into the alloy layer. A method of manufacturing the semiconductor device described above.