JP3471884B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
A fine wiring or between the contact hole adjacent to a semiconductor equipment manufacturing method which opens the contact bottom in a self-aligned manner.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated, and fine semiconductor memory devices have been actively developed.
Above all, DRAM is highly integrated, and in order to form a MOS transistor and a capacitive element forming a memory cell in a small area, a method of forming a contact vertically on a sidewall to reduce an occupied area of the contact. Is generally widely used.

Here, in a semiconductor integrated circuit in which the contacts have a vertical structure, it is necessary to reduce the area of the contacts connecting the conductors to each other or between the conductors to the conductor substrate. A method is used in which a contact is formed between the wiring formed via a thin oxide film and a wiring adjacent to the wiring at a fine interval with respect to the two wirings by self-alignment.

In the conventional contact forming method, the insulating film above the wiring is made thicker than the opening at the bottom of the contact so that the wiring is protected by the insulating film even if the insulating film at the opening is removed by etching. However, the contact could be formed by self-alignment.

Here, an example of a cross section of a DRAM formed by a conventional method is shown in FIG. 18, and a conventional contact forming method will be described below with reference to FIG. First,
A LOCOS 231, a trench capacitor, a MOS transistor / gate are formed on a semiconductor substrate 230. In the figure, 236 is an insulating film, 237 is a conductive film, 238 is a capacitor insulating film, 239 is a conductive film, and 240 is an insulating film.
232 is a gate oxide film, 233 is a gate electrode, 2
Reference numeral 34 is an oxide film.

Next, an insulating film 235 is deposited by atmospheric pressure CVD. At that time, as described above, the insulating film of the gate electrode 233 is made thicker than the opening at the bottom of the contact. A photolithography process is used to form a contact pattern mask between the source electrode of the MOS transistor and the trench capacitor electrode, and a contact hole is formed by isotropic etching. Then, a conductive film 241, an insulating film 242, and an insulating film 243 are sequentially formed between the gate electrodes 233.

Next, after forming the conductive film 244 and the insulating film 245, a contact pattern mask between the capacitor electrode and the transistor electrode is formed by using an optical lithography process, and a contact hole is formed by isotropic etching. . And polycrystalline silicon (strap) 2
46 is formed.

However, according to this method, it is necessary that the sidewall of the wiring (gate electrode) stands vertically and that the sidewall portion be vertically etched at the same etching rate as the contact bottom portion in the etching of the contact opening. Actually, the sidewall on the top of the wiring always has a taper, and the etching of the shoulder of the sidewall is faster than that of the contact bottom for etching, so the insulating film on the shoulder of the wiring is removed by overetching. I will end up.

Therefore, a short circuit may occur between the gate electrode and the bit line. Further, in the conventional method, isotropic etching is used for removing the insulating film at the time of opening the contact hole, so that the insulating film under the side wall of the MOS gate electrode is etched and a short circuit occurs between the gate electrode and the source electrode. There was an occasion.

Although the above problem has been described by taking the DRAM as an example, it does not occur only in the DRAM but generally occurs in the semiconductor device having the contact between fine wirings.

On the other hand, a technique for forming an element isolation or a capacitor by utilizing a trench formed on the surface of a semiconductor substrate is widely used. There is a case where a diffusion layer is formed by selectively implanting ions into the bottom of this wrench. Conventionally, a normal pressure C is used as a mask for this selective ion implantation.
A VD silicon oxide deposited film is used. in this case,
This is because the bottom of the contact is thin.

A process of selectively forming a diffusion layer on the bottom of the trench will be described below. First, on the silicon substrate 301,
After forming the buffer oxide film 303, the selective oxide film (LO
COS) 302 is formed (FIG. 19A).

Next, a silicon nitride film 304 and a silicon oxide film 305 are sequentially deposited to form a trench 306 (FIG. 19B). Next, the trench inner wall oxide film 397
To remove the oxide film corresponding to the contact portion of the capacitor lower electrode with the silicon substrate 301 (see FIG. 1).
9 (a)).

Next, polycrystalline silicon 308 is deposited (FIG. 20A), and then silicon oxide film 30 is formed by atmospheric pressure CVD.
9 is deposited (FIG. 20 (b)). Then, ion implantation is performed. Next, the atmospheric pressure CVD deposition film 309 is removed by wet etching (FIG. 20 (c)).

Thereafter, trench capacitor formation and MOS
Gate transistor formation and wiring formation are performed. Here, in the conventional method, a silicon oxide deposited film of atmospheric pressure CVD is used as a mask for selectively implanting ions into the bottom of the trench as described above. When silicon oxide is used as the mask material, etching having high selectivity with respect to the underlying material is used in the mask material removing step. Therefore, if there is a portion where the same quality (low selectivity) material is exposed in the base, this conventional technique cannot be used.

In the prior art, when the impurity diffusion layer is selectively formed at the bottom of the trench covered with the oxide film,
Ion ions are implanted into the bottom of the trench by implanting ions from a direction perpendicular to the surface of the semiconductor device (that is, the surface of the silicon substrate). In this case, when the surface of the substrate on which the semiconductor device is formed is large, the ion implantation angle does not become perpendicular to the substrate surface from the ion implantation target to the position of the semiconductor device, and ions are implanted at a slight angle. Therefore, ions are also implanted into the oxide film inside the trench. When ions are implanted into the oxide film inside the trench, when used as a film for element isolation, the ions in the oxide film diffuse into the substrate and deteriorate the electrical characteristics of element isolation. Further, when it is used as a capacitor insulating film, it damages the insulating film, which causes deterioration of reliability of the capacitor insulating film.

Further, in the conventional method, since the silicon oxide film formed by the atmospheric pressure CVD is used as the mask material for the selective ion implantation, the steps of forming the silicon oxide film and removing the silicon oxide film increase in number of steps, There is a drawback that the processing time also increases.

[0018]

As described above, the conventional method for manufacturing a semiconductor device, in particular, between the wiring formed on the semiconductor substrate via the thin oxide film and the wiring adjacent to the wiring at a fine interval. In the method of forming the contact hole, the insulating film on the shoulder portion of the wiring is removed by overetching, which may cause a short circuit between the electrode and another wiring formed thereon. . Also,
In the conventional method, isotropic etching is used for removing the insulating film at the time of opening the contact hole, so that the insulating film under the sidewall of the MOS gate electrode is etched, and wiring (gate electrode)
A short circuit may occur between the semiconductor substrate surface and the diffusion region (source electrode) on the surface of the semiconductor substrate.

The present invention has been made in consideration of the above circumstances. Even after a contact hole opening process between fine wirings, the wirings formed on the semiconductor substrate via the oxide film and the wirings formed on the wirings are formed. and between the wires, and an object thereof is to provide a semiconductor equipment manufacturing method without a short circuit between the wiring diffusion region (gate electrode) and the semiconductor substrate surface (the source electrode).

[0020]

A method for manufacturing a semiconductor device according to the present invention (claim 1) is a semiconductor having an LDD structure.
The method of manufacturing a device, comprising the steps of forming an insulating film on the wiring layer formed through an oxidation film on a semiconductor substrate, before
On serial insulating film, forming a mask layer made of a material resistant to etching of the insulating film and the oxide film, anisotropic etching using a resist as a mask
The upper part and the side wall of the wiring layer of the mask layer.
A step of removing the mask layer in the other region leaving the upper part,
With the resist left, use anisotropic etching to
Etching the insulating film and the oxide film underneath it
The substrate with the mask layer left on the sidewall of the linear layer.
Exposing the resist and the mask layer
After the removal, a contact made of wiring material is formed on the exposed portion of the substrate.
Process to form the substrate and the substrate through the contact.
High impurity concentration diffusion of LDD structure by ion implantation of impurities
And a step of forming a layer .

Further, a method of manufacturing a semiconductor device according to the present invention (claim 2) is the method of manufacturing a semiconductor device having an LDD structure, in which a first layer is formed on a wiring layer formed on a semiconductor substrate via an oxide film. A step of forming a first insulating film, a step of sequentially forming a polycrystalline silicon film and a second insulating film on the first insulating film, and a step of forming the LDD structure from the upper part of the wiring layer on the side wall. Removing the second insulating film and the polycrystalline silicon film over the diffusion layer, and forming a mask layer made of a material having resistance to the etching of the first insulating film and the oxide film on the entire surface. And a step of removing the mask layer above the diffusion layer forming the LDD structure with the mask layer left on the sidewall of the wiring layer by anisotropic etching, and by anisotropic etching. Forming a step by etching the first insulating film and before hexanes monolayer, contact holes are formed in the diffusion layer above constituting the LDD structure, the contact comprising a wiring material in the contact hole, wherein Impurity is ion-implanted into the substrate through the contact and L
And a step of forming a high impurity concentration diffusion layer having a DD structure.

[0022]

[0023]

In the present invention, since the mask layer provided on the wiring layer and the insulating film and the insulating film on the wiring layer have resistance to the etching of the insulating film and the oxide film, the mask layer at the time of contact opening, that is, on the semiconductor substrate When the insulating film and the oxide film are etched, the wiring layer and the insulating film above it are protected.

Therefore, it is possible to prevent the insulating film on the shoulder portion of the wiring layer from being removed by over-etching. Therefore, when another wiring is formed on the wiring layer, it is formed on the wiring layer and the wiring layer. It is possible to prevent a short circuit from occurring between other wirings.

Further, since isotropic etching is used for the etching for the contact opening, it is possible to avoid etching the insulating film under the side wall of the wiring layer, so that between the wiring layer and the diffusion region on the surface of the semiconductor substrate. It is possible to prevent a short circuit from occurring.

As described above, it is possible to form a contact hole between adjacent wirings, which was difficult in the conventional technique, with good controllability without increasing the number of steps, and to provide a highly reliable semiconductor device. it can.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. In each of the process cross-sectional views, the reference numerals already described are omitted in some cases, and the cross-sectional portions already illustrated are omitted in some cases.

(First Embodiment) A method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described. This example
DRAM is characterized by the method of manufacturing contact holes.
It is suitable for S / N contact, etc.

The manufacturing method will be described below with reference to the process sectional views shown in FIGS. 1) As shown in FIG. 1A, after a buffer oxide film 3 is formed on a semiconductor (for example, silicon) substrate 1, a selective oxide film (LOCOS) 2 is formed by a conventional method.

2) A trench capacitor is formed by a conventional method as shown in FIG. That is, a trench is dug in the end of the element formation region on the surface of the semiconductor substrate 1, and the oxide film 4 is formed on the sidewall of the trench. Then, the conductive film 5 is formed thereon, the capacitor insulating film 6 is formed, the trench is filled with the conductive film 7, and the upper portion of the trench is covered with the insulating film 8. The buffer oxide film 3 has been removed.

3) MO as shown in FIG. 1 (c) by the conventional method.
Form SFET. That is, the gate oxide film 9 is formed, the gate electrode 10 is patterned, and the upper portion 11 thereof is formed.
After oxidizing, an insulating film (interlayer insulating film) 12 is deposited.

4) As shown in FIG. 1D, the mask material 13 is sputtered or evaporated. It is preferable to use carbon or an oxidation resistant film etching film for the mask material 13. 5) As shown in FIG. 2A, after applying the resist 14, a resist pattern of a hole for making contact between the MOSFET and the trench spacer is formed by light exposure in a pattern that covers the gate of the MOSFET.

6) As shown in FIG. 2B, the mask material 13 is anisotropically etched. At this time, the etching condition is M
The thin portion of the mask material 13 between the OSFET gates 10 is removed, and the carbon on the MOSFET gates 10 is set to remain.

7) As shown in FIG. 2C, anisotropic etching of the oxide film between the MOSFET gates 10 is performed using the resist 14 and the mask material 13 as a mask. 8) Hereinafter, in the conventional method, using the known wiring material 15,
As shown in FIG. 2D, a contact is formed between the S / D electrode of the MOSFET and the upper portion of the trench capacitor.

In this embodiment, the gate electrode 10
Since the mask layer 13 provided on the upper part and the side wall of the insulating film 12 thereabove has resistance to the etching of the insulating film 13 and the oxide film, the insulating film 13 and the oxide film 9 on the semiconductor substrate are opened at the time of contact opening. When etching, the gate electrode 10 and the insulating film 13 on the gate electrode 10 are protected.

Therefore, it is possible to prevent the insulating film 13 on the shoulder portion of the gate electrode 10 from being removed by overetching, and thus it is possible to prevent a short circuit from occurring between the gate electrode 10 and the wiring 15.

Further, since isotropic etching is used for the etching for the contact opening, the insulating film 9 under the gate electrode 10 can be prevented from being etched, so that the gate electrode 10 and the diffusion region on the surface of the semiconductor substrate (see FIG. (Not shown)
It is possible to prevent a short circuit from occurring.

Since the step of removing the mask layer such as carbon sputtering is the same as the step of removing the resist by the ordinary light exposure, when the pattern of the diffusion layer is patterned by the resist by the light exposure, the number of steps does not increase.

As described above, according to this embodiment, it is possible to form the contact hole between the adjacent wirings, which was difficult in the prior art, with good controllability without increasing the number of steps, and the reliability is high. A semiconductor device can be provided.

(Second Embodiment) Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described. This embodiment is characterized by a method of manufacturing a contact hole, and
It is suitable for bit line contacts of RAM.

Hereinafter, the manufacturing method will be described with reference to the process sectional views shown in FIGS. 1) As shown in FIG. 3A, after forming a buffer oxide film 23 on a semiconductor (for example, silicon) substrate 21, a LOCOS 22 is formed by a conventional method, and a first mask layer 24 and a second mask are formed. Layers 25 are sequentially deposited to form trenches 26. The silicon nitride film S is used as the first mask layer.
iN and a silicon oxide film SiO _{2 formed} by LPCVD may be used for the second mask layer.

2) As shown in FIG. 3B, according to the conventional method,
After removing the first mask layer 24 and the second mask layer 25, a trench capacitor is formed. In the trench capacitor, an oxide film 27 is formed on a sidewall portion of the trench 26 on the surface of the semiconductor substrate 21, a conductive film 28 and a capacitor insulating film 29 are sequentially formed on the oxide film 27, the trench 26 is filled with a conductive film 30, and the trench 26 is further formed. It is created by covering the upper part with the insulating film 31. The buffer oxide film 23 is removed.

3) As shown in FIG. 3C, the MOSFET is formed by the conventional method as described in the first embodiment, and the contact between the capacitor electrode and the S / D electrode of the MOSFET is formed. In the figure, 32 is a gate oxide film, 33 is a gate electrode, 34 is an oxide film, 35 is an interlayer insulating film, and 36 is a wiring material.

4) Next, using a well-known conventional method such as a poly-stopper method, as shown in FIG.
An interlayer insulating film 40 is formed on the T gate 33. In addition,
In the figure, 37 is an oxide film, 38 is an insulating film, and 39 is polycrystalline silicon.

5) As shown in FIG. 4A, after applying a resist 41, a pattern of a self-aligned contact is formed on the gate wiring 33 of the MOSFET by a light exposure method. Then, the interlayer insulating film 40 is formed by anisotropic etching.
And the stopper polysilicon is removed by isotropic etching.

6) As shown in FIG. 4B, after removing the resist 41, the interlayer insulating film 40 is melted and the mask material 4 is formed.
2 is sputtered or vapor deposited. It is preferable to use carbon or an oxidation resistant film etching film for the mask material 42.

7) As shown in FIG. 4C, the mask material 42 is anisotropically etched. At this time, the etching conditions are
Only the lower portion between the gate wirings 33 of the MOSFET is removed and the gate 33 is set to remain.

8) As shown in FIG. 5A, the insulating film is etched to open the contact portion. Note that FIG. 5A is an enlarged view of the area indicated by A in FIG. 4C. 9) Thereafter, the upper wiring 43 and the interlayer insulating film 44 are formed by the conventional method as shown in FIG.

Also in this embodiment, the same operational effects as those described in the first embodiment can be obtained. Since it is self-explanatory, detailed description thereof will be omitted. (Third Embodiment) Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described. This embodiment is characterized by a method of manufacturing a contact hole and is suitable for a bit line contact of DRAM or the like.

The manufacturing method will be described below with reference to the sectional views of the steps shown in FIGS. 1) As shown in FIG. 6A, after forming a buffer oxide film 53 on a semiconductor (for example, silicon) substrate 51, a LOCOS 52 is formed by a conventional method. LOC by conventional method
Form OS.

2) As shown in FIG. 6 (b), M is formed by the conventional method.
Form OSFET. In the figure, 50 is a gate oxide film, 54 is a gate electrode, 55 is an oxide film, and 56 is an insulating film.

3) As shown in FIG. 6C, after forming the oxide film 57, an insulating film 58 such as a silicon nitride film and polycrystalline silicon 59 are sequentially deposited, and an interlayer insulating film 60 is further deposited.

4) As shown in FIG. 6D, after the resist 61 is applied, a contact pattern is formed by a light exposure method, and the interlayer insulating film 60 is etched by anisotropic etching.

5) As shown in FIG. 7A, after removing the polycrystalline silicon 59 by isotropic etching, the polycrystalline silicon layer 59 is converted into a silicon oxide film layer 59 by an oxidation process.

6) As shown in FIG. 7B, a conductive film (for example, Al) 62 for wiring is sputtered or evaporated. Note that FIG. 7B is an enlarged view of the area indicated by B in FIG. 7A.

7) As shown in FIG. 7C, the conductive film 62 is etched under the condition that the conductive film 62 on the bottom of the contact hole can be removed and the conductive film 62 on the flat portion other than the hole bottom cannot be removed.

8) Here, when the insulating film at the bottom of the contact hole has not been removed, the insulating film is further removed by anisotropic etching as shown in FIG. 7D. 9) As shown in FIG. 8, heating is performed at a temperature equal to or higher than the melting point of the conductive film 62 so that the contact hole is filled with the melted conductive film 62.

10) Thereafter, the interlayer insulating film and the conductive film wiring on the upper portion are formed by the conventional method (not shown).
Also in this embodiment, the same operational effects as those described in the first embodiment can be obtained. Since it is self-explanatory, detailed description thereof will be omitted.

The present embodiment also has the advantage that there is no carbon contamination. (Fourth Embodiment) Next, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described. This embodiment is characterized by a method of manufacturing a contact hole and is suitable for a bit line contact of DRAM or the like.

The manufacturing method of this embodiment will be described below with reference to the process sectional views shown in FIGS. 1) As shown in FIG. 9A, after forming a buffer oxide film 73 on a semiconductor (for example, silicon) substrate 71, a LOCOS 72 is formed by a conventional method.

2) As shown in FIG. 9B, M is obtained by the conventional method.
Form OSFET. In the figure, 70 is a gate oxide film, 74 is a gate electrode, 75 is an oxide film, and 76 is an insulating film.

3) As shown in FIG. 9C, after forming the oxide film 77, an insulating film 78 such as a silicon nitride film and polycrystalline silicon 79 are sequentially deposited, and an interlayer insulating film 80 is further deposited.

4) As shown in FIG. 10A, the resist 81
After applying, a contact pattern is formed by a light exposure method, and the interlayer insulating film 80 is etched by anisotropic etching.

5) As shown in FIG. 10B, after removing the polycrystalline silicon 79 by isotropic etching, the polycrystalline silicon layer 79 is oxidized by a silicon oxide film layer 79.
And

6) As shown in FIG. 10C, a conductive film (for example, Al) 82 for wiring is sputtered or evaporated. Note that FIG. 10C is an enlarged view of the region indicated by C in FIG. 10B.

7) As shown in FIG. 10D, the conductive film 82 is etched under the condition that the conductive film 82 on the bottom of the contact hole can be removed and the conductive film 82 on the flat portion other than the hole bottom cannot be removed.

8) Here, when the insulating film at the bottom of the contact hole has not been removed, the insulating film is further removed by anisotropic etching as shown in FIG. 11A. 9) As shown in FIG. 11B, Ti or TiN 83 is sputtered or vapor-deposited to electrically conduct the contact bottom and the conductive film 82.

10) As shown in FIG. 11C, a conductor (for example, boron-doped polycrystalline silicon) 84 is deposited. 11) As shown in FIG. 11D, the conductor 84 is etched under the condition that the contact portion is embedded. Note that this etching may be anisotropic etching or isotropic etching.

12) Thereafter, the interlayer insulating film and the conductive film wiring are further formed on the upper portion by a conventional method (not shown). Also in this embodiment, the same operational effects as those described in the first embodiment can be obtained. Since it is self-explanatory, detailed description thereof will be omitted.

In addition, this embodiment has the advantage that there is no carbon contamination and that the reflow process is not required as in the third embodiment. (Fifth Embodiment) Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described. This embodiment is characterized by the method of manufacturing the diffusion region at the bottom of the trench and is suitable for forming the diffusion region at the bottom of the trench of the DRAM.

The manufacturing method will be described below with reference to the process sectional views shown in FIGS. 1) As shown in FIG. 12A, after forming a buffer oxide film 93 on a semiconductor (for example, silicon) substrate 91, LOCOS is performed by a conventional method.
Form a 92.

2) As shown in FIG. 12B, a first mask layer 94 and a second mask layer 95 are sequentially deposited to form a trench 96. The silicon nitride film SiN may be used for the first mask layer, and the silicon oxide film SiO _{2 formed} by the LPCVD method may be used for the second mask layer.

3) As shown in FIG. 12C, carbon 98
Is sputtered or evaporated. 4) As shown in FIG. 13A, ion implantation is performed to form an impurity diffusion layer 99 at the bottom of the trench.

5) As shown in FIG. 13B, a trench capacitor is formed by a conventional method. In the figure, 97 is an oxide film formed on the side wall of the trench, 100 is a conductive film, 101
Is a capacitor insulating film, 102 is a conductive film, and 103 is an insulating film 8. The buffer oxide film 93 is removed.

6) A MOSFET is formed by a conventional method (not shown). 7) An interlayer insulating film is deposited, a conductive film for wiring is deposited on the insulating film, and wiring is formed by a conventional method (not shown).

8) Thereafter, the conductive wiring film and the interlayer insulating film on the upper portion are formed by the conventional method (not shown). Here, as described above, in the conventional technique, atmospheric pressure CVD is used as a mask material for selectively implanting ions into the bottom of the trench.
A silicon oxide deposited film was used. Highly selective etching is used by using silicon oxide as a mask material. Therefore, if there is a portion where the same quality (low selectivity) material is exposed in the base, this conventional technique cannot be used.

On the other hand, in this embodiment, carbon is used as the mask material. Since carbon can be removed by the same technique as the resist used in the photolithography technique, it can be removed with high selectivity with respect to the material of the conventionally used semiconductor device. Therefore, there is an advantage that the material of the portion exposed to the carbon underlayer is not limited as in the conventional case. Of course, in the shape in which the inside of the trench is covered with the silicon oxide film, the ion implantation technique can be used with the carbon film as the mask material.

Furthermore, as described above, in the prior art,
When the impurity diffusion layer is selectively formed at the bottom of the trench covered with the oxide film, the ion implantation is performed from the direction perpendicular to the surface of the semiconductor device to implant the ion at the bottom of the trench. In this case, when the surface of the substrate on which the semiconductor device is formed is large, the ion implantation angle does not become perpendicular to the substrate surface from the ion implantation target to the position of the semiconductor device, and ions are implanted at a slight angle. Therefore, ions are also implanted into the oxide film inside the trench. If ions are implanted into the oxide film inside the trench, the ions in the oxide film will diffuse to the substrate when used as a film for element isolation, deteriorating the electrical characteristics of element isolation. Further, when it is used as a capacitor insulating film, the insulating film is damaged, which causes deterioration of reliability of the capacitor insulating film.

On the other hand, in this embodiment, the surface of the oxide film inside the trench is covered with carbon at the time of ion implantation, so that the above problems can be solved. Further, the processing time can be shortened as compared with the process of forming and removing the atmospheric pressure CVD silicon oxide film used in the conventional mask material.

(Sixth Embodiment) Next, a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention will be described. This embodiment is characterized by the method of manufacturing the diffusion region at the bottom of the trench and is suitable for forming the diffusion region at the bottom of the trench of the DRAM.

The manufacturing method will be described below with reference to the process sectional views shown in FIGS. 1) A semiconductor (for example, silicon) as shown in FIG.
After forming the buffer oxide film 113 on the substrate 111,
The LOCOS 112 is formed by a conventional method. LOCOS is formed by conventional methods.

2) As shown in FIG. 14B, a first mask layer 112 and a second mask layer 114 are sequentially deposited to form a trench 116. A silicon nitride film SiN is used for the first mask layer and LPCVD is used for the second mask layer.
A silicon oxide film SiO _{2 formed} by the method may be used.

3) As shown in FIG. 14C, an insulating film 117 is formed in the trench 116 by a conventional method. 4) As shown in FIG. 15A, carbon 118 is sputtered.

5) As shown in FIG. 15B, the carbon 118 and the insulating film 117 are removed only at the bottom of the trench 116 by anisotropic etching, and ions are implanted to form the trench 116.
An impurity diffusion layer 119 is formed on the bottom.

7) A trench capacitor is formed by a conventional method (not shown). 8) A MOSFET is formed by a conventional method (not shown). 9) An interlayer insulating film is deposited, a conductive film for wiring is deposited on the insulating film, and wiring is formed by a conventional method (not shown).

8) Thereafter, the conductive wiring film and the interlayer insulating film on the upper portion are formed by the conventional method (not shown). As described above, according to this embodiment, the same effect as that described in the fifth embodiment can be obtained.

(Seventh Embodiment) FIG. 16 shows a seventh embodiment of the present invention.
3 is a cross-sectional view of a MOS transistor of the semiconductor memory device according to the example of FIG. A cross-sectional structure such as this semiconductor memory device can be obtained by carrying out the manufacturing method of the above-described first to fourth embodiments.

On the other hand, FIG. 17 is a sectional view of a MOS transistor of a conventional semiconductor memory device. Here, in FIG.
Inside, 121 is a semiconductor substrate, 122 is a gate oxide film, and 12
3 is a gate electrode, 124 is an insulating film, 125 is a conductor, 1
26 is an n ⁻ diffusion layer, 127 is an n ⁺ diffusion layer, s is the offset amount of the insulating film 124 above the gate, and 1 is the n ⁻ diffusion layer 1.
The amount of offset between the end of 26 and the end of the n ⁺ diffusion layer 127 is shown.

The insulating film 124 is the insulating film 12 in the first embodiment, the insulating film 35 in the second embodiment, the insulating films 56 and 58 in the third embodiment, and the fourth embodiment. Then, they correspond to the insulating films 76 and 78, respectively.

Further, in FIG. 17, 221 is a semiconductor substrate, 2
22 is a gate oxide film, 223 is a gate electrode, 224 is an insulating film, 225 is a conductor, 226 is an n ^- diffusion layer, 227 is an n ⁺ diffusion layer, and l ′ is an end of the n ⁻ diffusion layer 226 and n ⁺ diffusion. The amount of offset from the edge of layer 227 is shown. In the prior art, the offset amount of the insulating film 224 above the gate is
It is 0.

Here, a conventional technique relating to the semiconductor device as shown in FIG. 17 will be described. As the miniaturization of semiconductor integrated circuit devices progresses, a technique for opening contacts in self-alignment with wiring is required. Conventionally, when a contact is formed in self alignment with the gate electrode 223 of a MOS transistor, the contact is formed vertically on the side wall of the gate electrode. In the case of such a structure, LD
When a D-type MOS transistor is formed, the length of the LDD low-concentration diffusion layer is defined by the film thickness of the side wall of the gate electrode. Therefore, the diffusion layer of the source / drain electrodes of the MOS transistor formed in the contact portion is formed together with this ion implantation in order to perform high-concentration ion implantation after forming the contact hole and depositing the wiring material 225. However, since the diffusion of the impurities isotropically extends due to the extension of the diffusion layer due to the thermal process, the high-concentration diffusion layer is formed even under the gate sidewall of the LDD structure. For this reason, the diffusion structure is the same as that of the non-LDD MOS transistor, though the same process as that of the LDD is performed, and the reliability is lowered.

On the other hand, in this embodiment, the first to fourth
The portion formed on the side wall of the wiring (including the oxide film on the side wall) 123 of the mask materials 13, 42, 62 and 82 used when the contact hole is opened as in the embodiment of FIG. (Including upper oxide film)
The insulating film 124 on 123 has a shape having an offset s from the side wall of the wiring 123 with respect to the opening of the contact hole.

As a result, the LDD structure can be realized by setting the offset amount l between the end of the n ⁻ diffusion layer 126 and the end of the n ⁺ diffusion layer 127 to a sufficiently large amount as shown in FIG. Becomes Further, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0094]

According to the present invention, it is possible to form a contact hole between adjacent wirings, which has been difficult in the prior art, with good controllability without increasing the number of steps.
A highly reliable semiconductor device can be provided.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a process cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment.

FIG. 3 is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the invention.

FIG. 4 is a process sectional view showing the manufacturing method of the semiconductor device according to the embodiment.

FIG. 5 is a process sectional view showing the manufacturing method of the semiconductor device according to the embodiment.

FIG. 6 is a process sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the invention.

FIG. 7 is a process sectional view showing the manufacturing method of the semiconductor device according to the embodiment.

FIG. 8 is a process sectional view showing the method of manufacturing the semiconductor device according to the embodiment.

FIG. 9 is a process sectional view showing a method for manufacturing a semiconductor device according to a fourth embodiment of the invention.

FIG. 10 is a process sectional view showing the manufacturing method of the semiconductor device according to the embodiment.

FIG. 11 is a process sectional view showing the manufacturing method of the semiconductor device according to the embodiment.

FIG. 12 is a process sectional view showing the manufacturing method of the semiconductor device according to the fifth embodiment of the invention.

FIG. 13 is a process sectional view showing the manufacturing method of the semiconductor device according to the embodiment.

FIG. 14 is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 15 is a process sectional view showing the manufacturing method of the semiconductor device according to the embodiment.

FIG. 16 is a sectional view of a MOS transistor according to a seventh embodiment of the present invention.

FIG. 17 is a sectional view of a conventional MOS transistor.

FIG. 18 is a sectional view of a conventional DRAM.

FIG. 19 is a process sectional view showing a method of selectively implanting ions into the bottom of a conventional trench.

FIG. 20 is a process sectional view showing a method of selectively implanting ions into the bottom of a conventional trench.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... LOCOS, 3 ... Buffer oxide film, 4 ... Oxide film, 5 ... Conductive film, 6 ... Capacitor insulating film,
7 ... Conductive film, 8 ... Insulating film, 9 ... Gate oxide film, 10 ... Gate electrode, 11 ... Oxide film, 12 ... Interlayer insulating film, 13 ... Mask material, 14 ... Resist, 15 ... Wiring material, 2 ... 1 semiconductor Substrate, 22 ... LOCOS, 23 ... Buffer oxide film, 24
...... First mask layer, 25 ...... Second mask layer, 26 ... Trench, 27 ... Oxide film, 28 ... Conductive film, 29 ... Capacitor insulating film, 30 ... Conductive film, 31 ... Insulating film, 32 ... Gate oxidation Film, 33 ... Gate electrode, 34 ... Oxide film, 35 ... Interlayer insulating film, 36 ... Wiring material, 37 ... Oxide film, 38 ... Insulating film,
39 ... Polycrystal, 40 ... Interlayer insulating film, 41 ... Resist, 4
2 ... Mask material, 43 ... Wiring, 44 ... Interlayer insulating film, 62 ...
Conductive film, 82 ... Conductive film, 83 ... Ti, TiN

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 (56) Reference JP-A-6-69451 (JP, A) JP-A-1-189157 (JP, A) USA Patent 5069747 (US, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/28 H01L 21/336 H01L 21/768 H01L 21/8242 H01L 27/108 H01L 29/78

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device having an LDD structure, the method comprising: forming an insulating film on a wiring layer formed on a semiconductor substrate via an oxide film; and forming an insulating film on the insulating film. And a step of forming a mask layer made of a material having resistance to etching of the oxide film, and anisotropic etching using a resist as a mask to leave other portions of the mask layer above the wiring layer and the sidewalls. A step of removing the mask layer in the region, and a state in which the insulating film and the oxide film thereunder are etched by anisotropic etching while leaving the resist, and the mask layer is left on the sidewall of the wiring layer. The step of exposing the substrate with a step of removing the resist and the mask layer, and then forming a contact made of a wiring material on the exposed part of the substrate, And a step of forming a high impurity concentration diffusion layer having an LDD structure by ion-implanting an impurity into a substrate through a contact. 2. A method of manufacturing a semiconductor device having an LDD structure, the step of forming a first insulating film on a wiring layer formed on a semiconductor substrate via an oxide film, and the first insulating film. A step of sequentially forming a polycrystalline silicon film and a second insulating film on the wiring layer, and a step of forming the second insulating film and the second insulating film from the upper portion of the wiring layer to the side wall and the diffusion layer forming the LDD structure. A step of removing the crystalline silicon film, a step of forming a mask layer made of a material having resistance to the etching of the first insulating film and the oxide film on the entire surface, and a step of anisotropic etching on the sidewall of the wiring layer. etching and removing the diffusion layer above the mask layer for forming the LDD structure while leaving the mask layer, the first insulating film and before hexanes <br/> monolayer by anisotropic etching Then The step of forming a contact hole above the diffusion layer forming the LDD structure, the step of forming a contact made of a wiring material in the contact hole, and the step of forming an LDD structure by ion-implanting impurities into the substrate through the contact. And a step of forming a high impurity concentration diffusion layer.