JPH07273185A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE:To prevent local oxidation of a silicon substrate at the end of a field shield isolation structure. CONSTITUTION:A shield electrode 5 is deposited, on the side wall, with silicon nitride 8 while covering a shield gate oxide 4 deposited beneath the side wall. This structure prevents local heating of a silicon substrate 1 at the part beneath the side wall at the time of depositing a gate oxide 10 thus preventing the shield gate oxide 4 from bulging at the end part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having element isolation by a field shield element isolation structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher integration of semiconductor devices, the conventional element isolation method by the LOCOS method is finer to the submicron level because of the problem of lateral diffusion of impurities from bird's beaks and channel stopper layers. It has become difficult to apply to integrated devices, and LOCOS
In place of the law, element isolation technology using a field shield element isolation structure is drawing attention.

In the element isolation technique using this field shield element isolation structure, a shield electrode is formed on an element isolation region of a silicon substrate via a silicon oxide film for capacitive coupling (hereinafter referred to as "shield gate oxide film"). Then, by fixing the potential of the shield electrode to the GND potential, for example, the potential from the gate wiring passing over the shield electrode is cut off to prevent the conduction of the parasitic MOS transistor.

Therefore, the element isolation technique using the field shield element isolation structure has no problems such as bird's beak and lateral diffusion of impurities from the channel stopper layer unlike the conventional LOCOS method, and is noted as suitable for miniaturization. Has been done.

For example, IEDM-88, pp246-249 "Fully plan
It has been reported that, in the arized 0.5 μm technorogies for 16Mb DRAM ", the element isolation by the field shield element isolation structure is applied to the 16M DRAM to obtain good element isolation characteristics.

14 to 19 are schematic sectional views showing a method of forming a conventional field shield element isolation structure in the order of steps. The element formed in the element region is a MOS transistor.

First, as shown in FIG. 14, ion implantation 2
2. Boron is added to the silicon substrate 21 at 1 × 10 ¹² /
An impurity implantation layer 23 'is formed by implanting about ² cm ² . The boron ion implantation 22 is for adjusting the threshold voltages of the MOS transistor formed in the element region and the parasitic MOS transistor formed in the element isolation region.

Next, as shown in FIG. 15, a shield gate oxide film 24 is formed on the silicon substrate 21 to a film thickness of about 50 nm by a thermal oxidation method (the heat treatment at this time forms the impurity implantation layer 23 '). The impurities are activated to become the impurity diffusion layer 23), and a method such as CVD is used.
A phosphorus-doped polycrystalline silicon film 25 is formed to a thickness of about 200 nm, and a silicon oxide film 26 is further formed to a thickness of 300 nm.
It is formed to a thickness of about 400 nm. The polycrystalline silicon film 25 will serve as a shield electrode for performing element isolation later.

Next, a photoresist 27 is applied to the entire surface and then patterned by a lithography technique so that the photoresist 27 covers only the element isolation region.

Next, as shown in FIG. 16, the silicon oxide film 26 is etched by anisotropic etching such as RIE using the photoresist 27 as a mask, and further,
After removing the photoresist 27 by ashing or the like, the polycrystalline silicon film 25 is etched by an anisotropic etching method such as RIE using the silicon oxide film 26 as a mask to form the shield electrode.

Next, as shown in FIG. 17, a silicon oxide film having a thickness of about 100 to 300 nm is formed on the entire surface by CVD or the like. Then, this silicon oxide film is
The sidewall spacers 28 are formed on both sides of the polycrystalline silicon film 25 by anisotropic etching by IE or the like. At this time, as shown in the figure, the shield gate oxide film 24 in the element region is also removed.

Next, as shown in FIG. 18, a gate oxide film 29 is formed on the surface portion of the silicon substrate 21 in the element region by thermal oxidation. At this time, the silicon substrate 21 is also oxidized at the end of the element isolation region, so that the local oxide film 30 is formed below the sidewall spacer 28 at the end of the element isolation region.

Next, as shown in FIG. 19, a gate electrode 31 of the MOS transistor (the drawing shows a cross section taken along the gate) is formed of a polycrystalline silicon film, and then ion implantation 32 is performed to illustrate it. Although omitted, the source / drain diffusion layers are formed in the silicon substrate 21, respectively.

[0014]

As described above, the field shield element isolation structure originally has the advantage that bird's beak does not occur unlike the LOCOS method.
Actually, as described above, when the element isolation region is formed by the field shield element isolation structure and then thermal oxidation is performed, a local oxide film 30 is formed at the end of the element isolation region as shown in FIG. As in the bird's beak of the LOCOS method, there is a problem that the width of the element isolation region is expanded. As a result, M formed in the element region
There is a problem of the narrow channel effect in which the gate width of the OS transistor is reduced and the threshold voltage is increased. Further, due to local oxidation at the end of the element isolation region, crystal defects are generated in the silicon substrate 21, and the shield gate oxide film 2
There was also a problem that the reliability of 4 decreased.

Therefore, an object of the present invention is to provide a semiconductor device capable of suppressing local oxidation at the end of the element isolation region by the field shield element isolation structure and a method for manufacturing the same.

[0016]

In order to solve the above-mentioned problems, the present invention provides a semiconductor device in which element isolation is performed by a shield electrode formed on a semiconductor substrate with a shield gate oxide film interposed therebetween. An electrically insulating sidewall spacer including an oxidation resistant insulating film is formed on the shield gate oxide film on the side wall of the.

According to one aspect of the present invention, the oxidation resistant insulating film is a silicon nitride film.

In one aspect of the present invention, the sidewall spacers are all made of a silicon nitride film.

In one aspect of the present invention, the sidewall spacer is composed of at least a silicon nitride film formed on the shield gate oxide film and a silicon oxide film formed on the silicon nitride film. There is.

A method of manufacturing a semiconductor device according to the present invention is
A step of sequentially forming a shield gate oxide film, a conductive film, and a silicon oxide film on a semiconductor substrate, and selectively removing the silicon oxide film and the conductive film to form a shield electrode pattern in an element isolation region. A step of forming a silicon nitride film on the entire surface, and a step of anisotropically etching the silicon nitride film to form a sidewall spacer made of the silicon nitride film on the side wall of the shield electrode made of the conductive film. Have.

According to one embodiment of the present invention, a step of sequentially forming a shield gate oxide film, a conductive film, and a silicon oxide film on a semiconductor substrate, and selectively removing the silicon oxide film and the conductive film to form an element A step of forming a shield electrode pattern in the isolation region; a step of forming a silicon nitride film and a silicon oxide film on the entire surface thereof; and a step of anisotropically forming the silicon nitride film and the silicon oxide film formed thereon. Of the silicon nitride film and the side wall spacer made of the silicon oxide film on the side wall of the shield electrode made of the conductive film.

[0022]

In the present invention, the shield gate oxide film existing under the side wall of the shield electrode is covered with an oxidation resistant insulating film such as a silicon nitride film to suppress the oxidation of the semiconductor substrate thereunder.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to FIGS.

1 to 6 are schematic cross-sectional views showing, in the order of steps, a method for manufacturing a semiconductor device having a field shield element isolation structure according to the first embodiment of the present invention. The element formed in the element region is a MOS transistor.

The manufacturing method of this embodiment will be described in the order of steps. First, as shown in FIG.
By ion implantation 2 of boron under the conditions of eV and a dose amount of about 1 × 10 ^{12 to} 5 × 10 ¹² / cm ² , a boron impurity implantation layer 3 ′ is formed on the semiconductor silicon substrate 1 (containing boron, specific resistance of 1 to 12 Ωcm). Form. The boron ion implantation 2 is for adjusting the threshold voltages of the MOS transistor formed in the element region and the parasitic MOS transistor formed in the element isolation region.

Next, as shown in FIG. 2, a shield gate oxide film 4 having a thickness of 50 to 100 nm is formed by a thermal oxidation method.
(The heat treatment at this time activates the impurities in the impurity-implanted layer 3'to form the impurity diffusion layer 3).
Then, by a method such as CVD or plasma CVD,
A polycrystalline silicon film 5 doped with phosphorus at a concentration of about 2 × 10 ^{20 to} 6 × 10 ²⁰ / cm ³ is formed to a thickness of about 100 to 200 nm, and a silicon oxide film 6 is further formed to a thickness of 150 to 3
It is formed to a thickness of about 00 nm. Polycrystalline silicon film 5
Serves as a shield electrode for performing element isolation later.

Next, a photoresist 7 is applied on the entire surface and then patterned by a lithography technique so that the photoresist 7 covers only the element isolation region.

Next, RIE and ECR (Electron Cyclotro
n Resonance) The silicon oxide film 6 is etched using the photoresist 7 as a mask by an anisotropic etching method such as plasma etching or low temperature etching, and then the photoresist 7 is removed by a method such as ashing.

Next, as shown in FIG. 3, RIE and ECR are performed.
The polycrystalline silicon film 5 is etched using the silicon oxide film 6 as a mask by an anisotropic etching method such as plasma etching or low temperature etching. In this way, after removing the photoresist 7, the polycrystalline silicon film 5 is etched using the silicon oxide film 6 as a mask,
A large etching selection ratio can be obtained, and a good shape can be obtained.

Next, as shown in FIG. 4, a silicon nitride film 8 is formed on the entire surface by CVD, plasma CVD, or the like.
After forming the silicon nitride film 8 to a thickness of about 0 to 200 nm, the silicon nitride film 8 is anisotropically etched by RIE, ECR plasma etching, low temperature etching or the like to form a sidewall spacer on the side wall of the polycrystalline silicon film 5. At this time, as shown in the figure, the shield gate oxide film 4 in the element region is also removed. The etching conditions are
For example, in the case of RIE, SF ₆ / He gas is used,
The pressure is 0.5 Torr and the time is about 100 to 200 sec.

Next, as shown in FIG. 5, the silicon substrate 1
The thermal oxidation is performed at a temperature of 800 to 850 ° C. for about 30 to 90 minutes to form the gate oxide film 10 on the surface of the silicon substrate 1 in the element region to a thickness of about 10 to 50 nm. At this time, since the sidewall spacer made of the silicon nitride film 8 is formed on the side wall of the polycrystalline silicon film 5, the shield gate oxide film 4 under the side wall is covered with the silicon nitride film 8. Therefore, thermal oxidation of the silicon substrate 1 thereunder is suppressed.

Next, as shown in FIG. 6, 2 × 10 ^{20 to} 6 × 10 ²⁰ are formed on the entire surface by CVD or plasma CVD.
A polycrystalline silicon film doped with phosphorus or arsenic having a concentration of about / cm ³ is formed to a thickness of 100 to 400 nm. Then, the polycrystalline silicon film is patterned by the lithography technique to form the gate electrode 11.

Next, an impurity of phosphorus or arsenic is introduced into the silicon substrate 1 by ion implantation 12 to form an impurity diffusion layer (not shown) serving as the source / drain of the MOS transistor in a self-aligned manner. The surface concentration of this impurity diffusion layer is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ ,
The junction depth is, for example, about 0.2 to 0.3 μm.

After that, after the heat treatment of the impurity diffusion layer, although not shown, an interlayer insulating film is formed, contact holes are formed, metal wiring such as Al--Si--Cu is formed, and the like is performed. Forming a semiconductor device.

By the above manufacturing method, it is possible to prevent the silicon substrate 1 below the side wall portion of the field shield element isolation structure from being thermally oxidized and the shield gate oxide film 4 thereon to be enlarged.

As a result, the width of the element isolation region unexpectedly expands and the element region is relatively reduced, so that the problem of dimensional variation does not occur.
The semiconductor device can be highly integrated and, for example, the gate width of the MOS transistor in the element region is prevented from being narrowed and the threshold value is prevented from rising. Further, since thermal oxidation of the silicon substrate 1 below the side wall portion of the field shield element isolation structure is prevented, crystal defects do not occur in that portion of the silicon substrate 1 and the reliability of the shield gate oxide film 4 is improved. .

In the field shield element isolation structure formed according to the first embodiment, the electrical insulation between the shield electrode 5 and the gate electrode 11 is made by the silicon nitride film 8 having a relatively poor electrical insulation property. Will be taken,
By forming the entire sidewall spacer with the silicon nitride film 8, the shield electrode 5 and the gate electrode 11 can be formed.
Good electrical insulation is obtained by forming a sufficient film thickness between and.

7 to 13 are schematic sectional views showing, in the order of steps, a method of manufacturing a semiconductor device having a field shield element isolation structure according to the second embodiment of the present invention. This second
In the embodiment, parts corresponding to those in the first embodiment described with reference to FIGS. 1 to 6 are designated by common reference numerals. The element formed in the element region is a MOS transistor.

First, as shown in FIG. 7, energy 30
〜50 KeV, Dose amount 1 × 10 ¹² 〜5 × 10 ¹² / cm
^A boron impurity implantation layer 3'is formed in the semiconductor silicon substrate 1 (containing boron and having a specific resistance of 1 to 12 Ωcm) by ion implantation 2 of boron under the condition of about ² . The boron ion implantation 2 is for adjusting the threshold voltages of the MOS transistor formed in the element region and the parasitic MOS transistor formed in the element isolation region.

Next, as shown in FIG. 8, a shield gate oxide film 4 having a thickness of 50 to 100 nm is formed by a thermal oxidation method.
(The heat treatment at this time activates the impurities in the impurity-implanted layer 3'to form the impurity diffusion layer 3).
Then, by a method such as CVD or plasma CVD,
A polycrystalline silicon film 5 doped with phosphorus at a concentration of about 2 × 10 ^{20 to} 6 × 10 ²⁰ / cm ³ is formed to a thickness of about 100 to 200 nm, and a silicon oxide film 6 is further formed to a thickness of 150 to 3
It is formed to a thickness of about 00 nm. Polycrystalline silicon film 5
Serves as a shield electrode for performing element isolation later.

Next, after applying the photoresist 7 on the entire surface, patterning is performed by the lithography technique so that the photoresist 7 covers only the element isolation region.

Next, by anisotropic etching such as RIE, ECR plasma etching and low temperature etching,
After the silicon oxide film 6 is etched using the photoresist 7 as a mask, the photoresist 7 is removed by a method such as ashing.

Next, as shown in FIG. 9, RIE, ECR
The polycrystalline silicon film 5 is etched using the silicon oxide film 6 as a mask by an anisotropic etching method such as plasma etching or low temperature etching. In this way, after removing the photoresist 7, the polycrystalline silicon film 5 is etched using the silicon oxide film 6 as a mask,
A large etching selection ratio can be obtained, and a good shape can be obtained.

Next, as shown in FIG. 10, a silicon nitride film 18 having a thickness of about 20 to 50 nm is formed on the entire surface by CVD, plasma CVD, or the like, and a silicon oxide film 19 is further formed on the silicon nitride film 18 to 150 to 50 nm. It is formed to a thickness of about 200 nm.

Next, as shown in FIG. 11, the silicon oxide film 19 and the silicon nitride film 18 are anisotropically etched to form a silicon nitride film 18 and a silicon oxide film 19 on the side wall of the polycrystalline silicon film 5. A sidewall spacer having a laminated structure of and is formed. At this time, as shown in the figure,
The shield gate oxide film 4 in the element region is also removed. The etching conditions at this time are CHF ₃ / CF
₄ / Ar is used, and pressure of 1700 mTorr
Perform for about 30 seconds. In this example, the sidewall spacers are formed of the silicon nitride film 18 and the silicon oxide film 19.
In comparison with the case where the side wall spacer is formed of only the silicon nitride film, by using the above reaction gas, the side wall spacer portion mainly composed of the silicon oxide film 19 and the silicon substrate are formed. The etching selection ratio with 1 can be made large,
It is possible to reduce the etching damage to the silicon substrate 1.

Next, as shown in FIG. 12, the silicon substrate 1 is thermally oxidized at a temperature of 800 to 850 ° C. for about 30 to 90 minutes to form the gate oxide film 10 on the surface of the silicon substrate 1 in the element region. It is formed to a thickness of about 10 to 50 nm. At this time, since the shield gate oxide film 4 under the side wall portion of the polycrystalline silicon film 5 is covered with the silicon nitride film 18, thermal oxidation of the silicon substrate 1 thereunder is suppressed.

Next, as shown in FIG. 13, 2 × 10 ^{20 to} 6 × 10 are formed on the entire surface by CVD or plasma CVD.
A polycrystalline silicon film doped with phosphorus or arsenic having a concentration of about ²⁰ / cm ³ is formed to a thickness of 100 to 400 nm.
Then, the polycrystalline silicon film is patterned by the lithography technique to form the gate electrode 11.

Next, an impurity of phosphorus or arsenic is introduced into the silicon substrate 1 by ion implantation 12 to form an impurity diffusion layer (not shown) serving as the source / drain of the MOS transistor in a self-aligned manner. The surface concentration of this impurity diffusion layer is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ ,
The junction depth is, for example, about 0.2 to 0.3 μm.

After that, after the heat treatment of the impurity diffusion layer, although not shown, formation of an interlayer insulating film, opening of contact holes, formation of metal wiring such as Al--Si--Cu, etc. are carried out, and the desired Forming a semiconductor device.

By the above manufacturing method, it is possible to prevent the silicon substrate 1 below the side wall portion of the field shield element isolation structure from being thermally oxidized and the shield gate oxide film 4 thereon to be enlarged.

As a result, the width of the element isolation region is unexpectedly expanded and the element region is relatively reduced, so that the problem of dimensional variation does not occur.
The semiconductor device can be highly integrated and, for example, the gate width of the MOS transistor in the element region is prevented from being narrowed and the threshold value is prevented from rising. Further, since thermal oxidation of the silicon substrate 1 below the side wall portion of the field shield element isolation structure is prevented, crystal defects do not occur in that portion of the silicon substrate 1 and the reliability of the shield gate oxide film 4 is improved. .

In the field shield element isolation structure formed according to the second embodiment, the sidewall spacers that electrically insulate the shield electrode 5 and the gate electrode 11 are replaced with the silicon nitride film 18 and the silicon oxide film. Since it has a laminated structure with the film 19, the silicon oxide film 19 can obtain good electric insulation.

The present invention has been described above with reference to the embodiments.
The invention is not limited to the embodiments described above. For example, the polycrystalline silicon film 5 serving as the shield electrode may be amorphous silicon, tungsten silicide, polycide, or the like, or may be a refractory metal such as tungsten. Further, the silicon substrate 1 is SIMOX (separation by
SOI (Silicon On Insu) such as implanted oxygen) substrate
rator) substrate. Further, a silicon nitride film can be used instead of the silicon oxide film 5 which is the cap insulating film of the shield electrode 5, and in that case, the thickness of the cap insulating film can be reduced.

[0054]

According to the present invention, since the local oxidation of the semiconductor substrate at the end of the field shield element isolation structure is suppressed, it is possible to prevent an unexpected dimensional variation of the element isolation region and thus the element region. Since it is not necessary to secure a design margin for that purpose, the degree of integration of the semiconductor device can be further increased.

Further, for example, a MOS formed in the element region
The gate width of the transistor is narrowed to prevent the threshold value from rising unexpectedly, and further, the reliability of the shield gate oxide film can be prevented from being lowered, so that the reliability of the semiconductor device is improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the first embodiment of the present invention.

FIG. 6 is a schematic cross sectional view showing a manufacturing process of the semiconductor device having the field shield element isolation structure according to the first embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the second embodiment of the present invention.

FIG. 8 is a schematic cross sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to a second embodiment of the present invention.

FIG. 9 is a schematic cross sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to a second embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the second embodiment of the invention.

FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the second embodiment of the invention.

FIG. 12 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the second embodiment of the invention.

FIG. 13 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the field shield element isolation structure according to the second embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 15 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 16 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the conventional field shield element isolation structure.

FIG. 17 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 18 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the conventional field shield element isolation structure.

FIG. 19 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the conventional field shield element isolation structure.

[Explanation of symbols]

 1 Silicon Substrate 3 Impurity Diffusion Layer 4 Shield Gate Oxide Film 5 Polycrystalline Silicon Film (Shield Electrode) 6 Silicon Oxide Film 8 Silicon Nitride Film 10 Gate Oxide Film 11 Gate Electrode 18 Silicon Nitride Film 19 Silicon Oxide Film

Claims (6)

[Claims] 1. A semiconductor device in which element isolation is performed by a shield electrode formed on a semiconductor substrate via a shield gate oxide film, wherein an oxidation resistance is provided on the shield gate oxide film on a side wall portion of the shield electrode. A semiconductor device, wherein an electrically insulating sidewall spacer including an insulating film is formed. 2. The semiconductor device according to claim 1, wherein the oxidation resistant insulating film is a silicon nitride film. 3. The semiconductor device according to claim 2, wherein the sidewall spacers are all made of a silicon nitride film. 4. The sidewall spacer is composed of at least a silicon nitride film formed on the shield gate oxide film and a silicon oxide film formed on the silicon nitride film. The semiconductor device according to claim 2. 5. A shield gate oxide film on a semiconductor substrate,
A step of sequentially forming a conductive film and a silicon oxide film, a step of selectively removing the silicon oxide film and the conductive film to form a shield electrode pattern in the element isolation region, and a silicon nitride film over the entire surface. And a step of anisotropically etching the silicon nitride film to form sidewall spacers made of the silicon nitride film on the sidewalls of the shield electrode made of the conductive film. Manufacturing method. 6. A shield gate oxide film on a semiconductor substrate,
A step of sequentially forming a conductive film and a silicon oxide film; a step of selectively removing the silicon oxide film and the conductive film to form a shield electrode pattern in an element isolation region; And forming a silicon oxide film over the entire surface, and anisotropically etching the silicon nitride film and the silicon oxide film formed thereon to form the silicon nitride film on the sidewall of the shield electrode made of the conductive film. And a step of forming a sidewall spacer made of the above-mentioned silicon oxide film thereon, and a method of manufacturing a semiconductor device.