JP2629663B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS transistor.

[0002]

2. Description of the Related Art FIGS. 11 to 15 show "IEDM 1987 Technica".
1 is a cross-sectional view showing a conventional method for manufacturing a MOS transistor disclosed in Digest, pp. 32-35.

First, as shown in FIG. 11, a field oxide film 2 is formed on a surface region of a silicon substrate 1, and a gate electrode 6 of polycrystalline silicon is formed on the surface of the silicon substrate 1 via a gate oxide film 5. I do. Arsenic-doped polycrystalline silicon 15 is formed on the top of gate electrode 6 via nitride film 14. Thereafter, a source / drain 8 is formed in the surface region of the silicon substrate 1 with the gate electrode 6 interposed therebetween.
After forming the side wall 9 of the oxide film on the side surface of the gate electrode 6, the surface of the silicon substrate 1 is exposed in the region of the source / drain 8.

Next, as shown in FIG. 12, non-doped polycrystalline silicon 16 is deposited on the entire surface and heat-treated.
Arsenic is diffused from polycrystalline silicon 15 to polycrystalline silicon 16 only near the upper portion of gate electrode 6. Thereafter, when the polycrystalline silicon 16 is uniformly etched, the etching rate is higher in the region where arsenic is diffused than in the non-doped region. Therefore, as shown in FIG. Can be removed.
At this time, the nitride film 14 functions as an etching stopper.

Next, as shown in FIG. 14, the polycrystalline silicon 16 is patterned and separated from other elements, and impurities of the same conductivity type as the source / drain 8 are introduced into the polycrystalline silicon 16. As shown in FIG. 15, the entire surface is covered with an interlayer insulating film 11, a contact hole 17 is opened, and an aluminum wiring 13 is formed.

In the MOS transistor thus formed, the source / drain 8 extends above the field oxide film 2, and a contact hole can be arranged on the field oxide film 2. Accordingly, there is an advantage that the planar area of the source / drain can be reduced accordingly, and the junction capacitance can be reduced.

[0007]

However, this conventional M
In the method for manufacturing the OS transistor, a method is employed in which polycrystalline silicon is removed only near the upper portion of the gate electrode 6 by utilizing the difference in etching rate between the non-doped region and the region where arsenic is diffused. There is a problem that controllability in separating the drain and the drain is poor, and a leak or a short circuit is easily generated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is a semiconductor which can stably manufacture a MOS transistor having a small source / drain plane area and a small junction capacitance without causing leakage or short circuit. An object of the present invention is to provide a method for manufacturing a device.

[0009]

In order to achieve the above object, the present invention provides an element isolation insulating film formed on a surface region of a semiconductor substrate and a gate oxide film formed on a surface of the semiconductor substrate. Gate electrode, a sidewall of an insulating film formed on a side surface of the gate electrode, and a source and a drain formed on the surface region of the semiconductor substrate with the gate electrode interposed therebetween and extended on the element isolation insulating film. Forming a first semiconductor layer or a metal layer in advance in an extension region of the source and the drain on the element isolation insulating film; and a step of forming the first semiconductor layer or the metal layer. Simultaneously and selectively on the source and the drain in the surface region of the semiconductor substrate.
Forming a semiconductor layer or a metal layer and connecting them.

A method for selectively forming the second semiconductor layer or metal layer simultaneously on the first semiconductor layer or metal layer and on the source and drain in a surface region of the semiconductor substrate is provided. And a selective chemical vapor deposition method.

[0011]

According to the present invention, the source and the drain are extended above the field oxide film by using the selective chemical vapor deposition method so that the source and the drain are separated.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 to 5 are sectional views showing a method for manufacturing a MOS transistor according to one embodiment of the present invention.

First, as shown in FIG.
A field oxide film 2 is formed on the surface region of the substrate, and a non-doped polysilicon layer 4 is formed on the field oxide film 2 via an oxide film 3.

Next, as shown in FIG. 2, the surface of the silicon substrate 1 is exposed except for the region where the field oxide film 2 and the polycrystalline silicon layer 4 are formed, and as shown in FIG. A gate electrode 6 is formed on the surface via a gate oxide film 5. An oxide film 7 is formed on the top of the gate electrode 6. Thereafter, a source / drain 8 is formed in the surface region of the silicon substrate 1 with the gate electrode 6 interposed therebetween, and a side wall 9 of an oxide film is formed on a side surface of the gate electrode 6. To expose.

Next, as shown in FIG. 4, a non-doped silicon layer 10 is simultaneously formed on the non-doped polycrystalline silicon layer 4 and the source / drain 8 by a selective chemical vapor deposition method. Is introduced with the same conductivity type as the source / drain 8, and these are connected.

Finally, as shown in FIG. 5, the entire surface is covered with an interlayer insulating film 11, a contact hole 12 is opened, and an aluminum wiring 13 is formed.

FIGS. 6 to 10 show an MO according to another embodiment of the present invention.
It is sectional drawing which shows the manufacturing method of S transistor.

First, as shown in FIG.
A field oxide film 2 is formed in the surface region of FIG. 1, and a gate electrode 6 of polycrystalline silicon is formed on the surface of the silicon substrate 1 via a gate oxide film 5. An oxide film 7 is formed on the top of the gate electrode 6. Thereafter, a source / drain 8 is formed in the surface region of the silicon substrate 1 with the gate electrode 6 interposed therebetween, and a side wall 9 of an oxide film is formed on a side surface of the gate electrode 6.

Next, as shown in FIG. 7, a non-doped polycrystalline silicon layer 4 is formed on the field oxide film 2 via the oxide film 3. Further, as shown in FIG. 8, the surface of the silicon substrate 1 is exposed in the region of the source / drain 8 and, as shown in FIG. A non-doped silicon layer 10 is formed by a phase growth method, impurities of the same conductivity type as the source / drain 8 are introduced into the non-doped silicon layer 10, and these are connected.

Finally, as shown in FIG. 10, the entire surface is covered with an interlayer insulating film 11, a contact hole 12 is opened, and an aluminum wiring 13 is formed.

In the manufacturing method of the MOS transistor described above, the source / drain 8 is extended above the field oxide film 2 by using the selective chemical vapor deposition method, so that the source and the drain can be easily separated. Therefore, a MOS transistor having a small source / drain plane area and a small junction capacitance can be stably manufactured without causing leakage or short circuit.

[0023]

As described above, according to the present invention,
M with small source / drain plane area and small junction capacitance
The OS transistor can be manufactured stably without causing leakage or short circuit.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method for manufacturing a MOS transistor according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method for manufacturing the MOS transistor according to one embodiment of the present invention, showing a step following FIG. 1;

FIG. 3 is a cross-sectional view showing the method for manufacturing the MOS transistor according to one embodiment of the present invention, showing a step following FIG. 2;

FIG. 4 is a cross-sectional view showing the method for manufacturing the MOS transistor according to one embodiment of the present invention, showing a step following FIG. 3;

FIG. 5 is a cross-sectional view showing the method for manufacturing the MOS transistor according to one embodiment of the present invention, which shows a step following FIG. 4;

FIG. 6 is a sectional view showing a method for manufacturing a MOS transistor according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a method for manufacturing a MOS transistor according to another embodiment of the present invention, and shows a step following FIG. 6;

FIG. 8 is a cross-sectional view showing a method for manufacturing a MOS transistor according to another embodiment of the present invention, and shows a step following FIG. 7;

FIG. 9 is a cross-sectional view showing a method for manufacturing a MOS transistor according to another embodiment of the present invention, and shows a step following FIG.

FIG. 10 is a cross-sectional view showing a method for manufacturing a MOS transistor according to another embodiment of the present invention, and shows a step following FIG. 9;

FIG. 11 is a cross-sectional view showing a method for manufacturing a conventional MOS transistor.

FIG. 12 is a cross-sectional view showing a conventional method for manufacturing a MOS transistor, and shows a step following FIG. 11;

FIG. 13 is a cross-sectional view showing a conventional method for manufacturing a MOS transistor, and shows a step following FIG. 12;

FIG. 14 is a cross-sectional view showing a conventional method for manufacturing a MOS transistor, and shows a step following FIG. 13;

FIG. 15 is a cross-sectional view showing a conventional method for manufacturing a MOS transistor, and shows a step following FIG. 14;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Field oxide film 3 Oxide film 4 Polycrystalline silicon layer 5 Gate oxide film 6 Gate electrode 7 Oxide film 8 Source / drain 9 Side wall 10 Silicon layer 11 Interlayer insulating film 12 Contact hole 13 Aluminum wiring 14 Nitride film 15 Polycrystal Silicon 16 Polycrystalline silicon 17 Contact hole

Claims (2)

(57) [Claims] An element isolation insulating film formed on a surface region of a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate via a gate oxide film, and an insulating film formed on a side surface of the gate electrode. A method of manufacturing a semiconductor device, comprising: a side wall of a film; and a source and a drain formed on a surface region of the semiconductor substrate with the gate electrode interposed therebetween and extended on the element isolation insulating film. Forming a first semiconductor layer or a metal layer in advance on the extended region of the source and the drain, and forming the first semiconductor layer or the metal layer on the first semiconductor layer or the metal layer and on the source and the drain in the surface region of the semiconductor substrate; Simultaneously, selectively forming a second semiconductor layer or a metal layer,
And a step of connecting them. 2. A method for selectively forming said second semiconductor layer or metal layer simultaneously on said first semiconductor layer or metal layer and on said source and drain in a surface region of said semiconductor substrate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a selective chemical vapor deposition method is used.