JPS6258670A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a contact hole with a single mask, by forming a semiconductor layer within and around the contact hole with is formed in two or more surface insulation layers with the same mask, and forming an electrode layer thereon through an insulation film of a transistion-metal oxide. CONSTITUTION:In order to form a capacitor in an LSI is which an element forming region or the like is divided by trench isolation regions 9, a contact hole 14 is formed by etching a silicon nitride film 12 and a silicon oxide film 4 with a photoresist film 13 used as a mask. After removing the film 13, a polysilicon layer 15 is formed within and around the hole 14 on the film 12. After an interlayer insulation film 16 is adhered on the layer 15 and the film 12, an aperture 17 is provided in a place corresponding to the layer 15. An electrode layer 10 is then formed in and around the aperture 17 through an insulation film 18.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and a method of manufacturing a semiconductor device, for example, for forming a capacitor in an LSI (large scale integrated circuit). Concerning effective techniques.

[Background Art] In semiconductor memories, as devices become more highly integrated, capacitors with smaller areas and larger capacitances are desired. Therefore, instead of the conventional silicon oxide as a dielectric material, tantalum oxide (T
Attempts have been made to use oxides of transition metals such as a205).

By the way, when forming a capacitor in an LSI,
It is common to form this as one electrode on a semiconductor substrate. Furthermore, in current LSI processes, silicon oxide and silicon nitride are mainly used as insulating films. Therefore, when forming a capacitor using a transition metal oxide as a dielectric material on a semiconductor substrate as described above, a contact hole is first formed in an insulating film on the surface of the semiconductor substrate.

It is necessary to form the other electrode layer over the contact hole with a transition metal oxide film interposed therebetween.

When forming the above contact holes, since two or more layers of insulating films are often formed on the surface of the semiconductor substrate, the first and second insulating films are selectively removed using the same mask to form the contact holes. If this is attempted, a so-called overhang will occur at the open end. As a result, breakage occurs in the insulating film (transition metal oxide film) as a dielectric of the capacitor and the electrode layer formed thereon, which may reduce the withstand voltage and yield of the capacitor.

Therefore, as shown in FIG. 3, an insulating film 2 consisting of two or more layers
1. In the contact area of the semiconductor substrate 1 covered with 22,
A first resist mask 23 is patterned (FIG. 2(a)), and the first insulating film 22 is etched to form an opening 24 (FIG. 2(b)). After removal, a second resist mask 25 is formed to cover the end of the opening 24, and the second insulating film 21 is etched to form a contact hole 26 without overhang. ), an electrode layer 28 or a capacitor insulating film 2 deposited thereon.
An invention has been proposed that prevents the breakage of the number 7 (Tokugan Sho, /-p-768'/Kuda issue).

However, in the capacitor forming method as described above, two resist masks are required to form a contact hole without overhang, which makes the process complicated. Since the first opening is smaller than the first opening, the actual capacitance of the capacitor also decreases, which disadvantageously lowers the degree of integration.

[Objective of the Invention] An object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the manufacturing process without reducing the actual capacitance or reducing the withstand voltage or yield of the capacitor. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A typical invention disclosed in this application is summarized as follows. Namely, the same mask is applied to two or more layers of insulating films on the surface of a semiconductor region where a capacitor is formed. A contact hole is formed in the contact hole, a semiconductor layer such as polysilicon is deposited from the surface of the semiconductor region exposed inside the contact hole to its periphery, and an insulating layer made of a transition metal oxide is deposited on the semiconductor layer. An electrode layer is formed through the film. This makes it possible to form a contact hole in the insulating film on the surface of the semiconductor region with a single mask, and also allows the overhang generated in the insulating film to be hidden within the semiconductor layer. The above object is to simplify the manufacturing process by forming a capacitor between the electrode layer and the capacitor, without reducing the actual capacitance of the capacitor and without reducing the withstand voltage or yield of the capacitor. It is something to be achieved.

The present invention will be specifically explained below using the drawings.

[Embodiment] FIG. 1 shows the present invention applied to a multi-emitter transistor Q1. One embodiment is applied to forming capacitors C1 and C2 in parallel with load resistor R1R2 connected to the collector side of Q2.

Shown in order of manufacturing process.

First, an N-type impurity is selectively introduced into the surface of a semiconductor substrate 1 made of P-type crystalline silicon using a silicon oxide film or the like as a mask to form an N-type buried layer 2. An N- type epitaxial layer 3 is formed on the N+ type buried layer 2 by vapor phase growth, and then a silicon oxide film 4 is formed by thermal oxidation. Then, after a silicon nitride film is deposited on the silicon oxide film 4 by a CVD method or the like, an anisotropic dry film is applied to the parts corresponding to the device boundaries (around the capacitor and diode) using this silicon nitride film as a mask. A groove is formed by etching or the like so as to penetrate through the N+ type buried layer 2 and reach the surface of the semiconductor substrate 1. and,
A P-type impurity is introduced into the bottom of this groove by ion implantation to form a channel stopper layer 5.

Thereafter, thermal oxidation is performed to form a silicon oxide film on the inner wall of the trench, and if necessary, a silicon nitride film or the like is deposited to form an insulating film 6 within the trench. After polysilicon is deposited on the entire surface, etching back is performed to leave polysilicon 7 in the groove inside insulating film 5. Then, thermal oxidation is performed to cover the surface of the polysilicon 7 with a silicon oxide film 8, and then the silicon nitride film serving as a mask is removed, forming an element formation region 10 separated by a trench isolation region 9. be done.

Next, using a silicon nitride film or the like as a mask, N-type impurities are introduced into the epitaxial layer 3 in the region surrounded by the trench isolation region 9 by ion implantation or the like, reaching the N+-type buried layer 2. An N-medium or N-type semiconductor region 11 is formed. Thereafter, the silicon nitride film serving as a mask is removed, and a silicon nitride film 12 is again deposited over the entire surface by CVD, resulting in the state shown in FIG. 1(A).

Note that the ion implantation for forming the N-type semiconductor region 11 may be omitted and the epitaxial layer 3 may be left as is.

After the state shown in FIG. 1(A), a photoresist film 13 is entirely deposited on the silicon nitride film 12 and patterned, and then etching is performed using the photoresist film 13 as an etching mask. Then, a contact hole 14 is formed in the silicon nitride film 12 and the silicon oxide film 4 on the surface of the semiconductor region 11, resulting in the state shown in FIG. 1(B). At this time, the underlying silicon oxide film 4 is etched to below the silicon nitride film 12, resulting in a so-called overhang a.

After removing the photoresist film 13 while leaving this overhang a as it is, the silicon nitride film 1
After step 2, a polysilicon layer is deposited over the entire surface by CVD. Then, this polysilicon layer is patterned, leaving the polysilicon layer 15 in and around the contact hole 14, resulting in the state shown in FIG. 1(c).

In this embodiment, the polysilicon layer 15 is formed on the surface of the emitter region of a bipolar transistor (for example, the multi-emitter transistor QztQ2 in the memory cell in FIG. 2) formed at another location (not shown) in the semiconductor substrate 1. The polysilicon electrode is formed at the same time as the polysilicon electrode.

In other words, in recent bipolar integrated circuits, transistors have become shallower, and the emitter region is formed by depositing a high concentration polysilicon layer that will serve as an electrode on the surface of the semiconductor region where the emitter is to be formed, and from this polysilicon layer. It has come to be formed by impurity diffusion. Therefore, in such a device, if the capacitor polysilicon layer 15 is formed at the same time as the emitter polysilicon electrode is formed, there is no need to provide a new process for forming the polysilicon layer 15.

After the state shown in FIG. 1C, an interlayer insulating film 16 such as a PSG (phosphorus silicate glass) film is entirely deposited on the polysilicon layer 15 and silicon nitride film 12. Then, an opening 17 is formed in this interlayer insulating film 16 at a position corresponding to the polysilicon layer 15.

Next, an insulating film 18 having a high dielectric constant such as tantalum oxide (Ta205) is entirely formed on the interlayer insulating film 16.
For example, by sputtering. Thereafter, a high-melting point metal such as dungesten or molybdenum or its silicide is deposited on the insulating film 18 and patterned to form an electrode layer inside and around the opening 17 via the insulating film 18. 19 and the first
The state shown in figure (D) is obtained.

Incidentally, in the above embodiment, a case has been described in which two layers of insulating films (4 and 12) are formed on the surface of the semiconductor region 11 where a capacitor is formed.

It goes without saying that this insulating film may have three or more layers.

[Effect (1) Contact holes are formed using the same mask in two or more layers of insulating films on the surface of the semiconductor region where the capacitor is formed,
A semiconductor layer such as polysilicon is deposited from the surface of the semiconductor region exposed inside this contact hole to its periphery, and an electrode layer is placed on top of this semiconductor layer via an insulating film made of a transition metal oxide. As a result, a contact hole can be formed in the insulating film on the surface of the semiconductor region with a single mask, and the overhang that occurs in the insulating film is hidden in the semiconductor layer. This has the effect of simplifying the manufacturing process without reducing the withstand voltage or yield of the capacitor.

(2) forming contact holes with the same mask in two or more layers of insulating films on the surface of the semiconductor region where the capacitor is formed;
A semiconductor layer such as polysilicon is deposited from the surface of the semiconductor region exposed inside this contact hole to its periphery, and an electrode layer is placed on top of this semiconductor layer via an insulating film made of a transition metal oxide. Since a capacitor is formed between the semiconductor layer (polysilicon layer) above the contact hole formed in the insulating film on the surface of the semiconductor region and the electrode layer, the size of the semiconductor region can be reduced. Regardless of the size of the contact hole thereon, the capacitance of the capacitor is determined by the size of the semiconductor layer and the electrode layer. Therefore, by extending the semiconductor layer and the electrode layer onto the isolation region around the semiconductor region, there is an effect that the substantial capacitance of the capacitor can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although the isolation region 9 around the semiconductor region 11 in which the capacitor is formed is considered to be a trench isolation region,
The separation area 9 is not limited to this, but may be LOCOS (COCO2).
It may also be a selective oxide film called . Also, poQ
It is also possible to form a double, triple or more T a 205 structure on ysi.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the formation of a capacitor constituting a memory cell in a bipolar memory, which is the field of application that formed the background of the invention. The present invention is not limited thereto, and can be used in MOS integrated circuits and other semiconductor devices in general that require large capacitance capacitors.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views showing an example of the method for forming a capacitor according to the present invention in the order of manufacturing steps, and FIG. 2 shows a capacitor suitable for applying the present invention. FIG. 1... Semiconductor substrate, 2... N+ type buried layer, 3...
... N-type epitaxial layer, 4... Insulating film (silicon oxide film), 7... Polysilicon, 8...
Silicon oxide film, 9... Trench isolation region, 11... Capacitor formation region (N-type semiconductor region), 12... Insulating film, 15... Semiconductor layer (
polysilicon layer), 16... interlayer insulating film, 17°°
...opening, 18...insulating film (capacitor dielectric), 19...electrode layer (barrier metal). Figure 1 CB) Figure 1 CD) Figure 3 (ct) (le)

Claims (1)

[Claims] 1. When forming a transistor and a capacitor on the same semiconductor substrate, contact holes are sequentially formed using a resist mask in two or more insulating films on the surface of the semiconductor region where the capacitor is formed. After that, a conductive layer is formed inside and around this contact hole, an insulating film as a dielectric is formed on this conductive layer, and an electrode layer is formed on this insulating film to form a capacitor. A method of manufacturing a semiconductor device, characterized in that: 2. After forming the conductor layer, depositing an interlayer insulating film thereon,
After forming an opening in this interlayer insulating film at a position corresponding to the conductor layer, an insulating film as a dielectric is formed inside and around this opening, and then the electrode layer is formed on this insulating film. 2. A method of manufacturing a semiconductor device according to claim 1, further comprising: forming a semiconductor device.