JPH01220856A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01220856A JPH01220856A JP63046558A JP4655888A JPH01220856A JP H01220856 A JPH01220856 A JP H01220856A JP 63046558 A JP63046558 A JP 63046558A JP 4655888 A JP4655888 A JP 4655888A JP H01220856 A JPH01220856 A JP H01220856A
- Authority
- JP
- Japan
- Prior art keywords
- film
- trench
- trenches
- insulating film
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 55
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に大きな容量値の容量(
キャパシタ)を備える半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, particularly a capacitor with a large capacitance value (
The present invention relates to a semiconductor device including a capacitor.
従来、回路に容量を必要とする半導体装置では、例えば
バイポーラトランジスタのベース・コレクタ接合、エミ
ッタ・ベース接合などの各種接合容量が広く用いられて
いる。しかし、この種の容量はバラツキが大きいこと、
容量値が電圧依存性をもつこと、電圧の極性は通常反転
しないようにして使用しなければならないこと等の理由
から、最近では酸化膜、チン化膜を絶縁膜として用いる
MIs型容型炉量流となっている。Conventionally, various types of junction capacitors, such as base-collector junctions and emitter-base junctions of bipolar transistors, have been widely used in semiconductor devices that require capacitance in circuits. However, this type of capacity varies widely;
Due to the fact that the capacitance value is dependent on voltage and that the polarity of the voltage must be used without being reversed, recently MIs type reactors using oxide films and tin oxide films as insulating films have been developed. It has become a trend.
しかしながら、この容量では、例えば比誘電率が高いチ
ン化膜を絶縁膜として用いた場合でも、単位面積当たり
の容量は1.3 X 10− ’PF/μ2程度であり
0.01 μFの容量を作ろうとすると28fflII
1口の面積が必要となりチップ面積を大きく越えてしま
い実用的ではない。単位面積当たりの容量値を大きくす
る方法として、最近、シリコン基板をトレンチエツチン
グして溝を作りこの溝の側面に酸化膜又はチン化膜の薄
膜を形成した後、ポリシリコンで溝を埋め、ポリシリコ
ン中にリンなどの不純物を拡散して一方の電極とし、基
板を他方の、電極とするトレンチ構造の容量が提案され
、DRAMにおいて採用されている。However, with this capacitance, even if a tinned film with a high dielectric constant is used as an insulating film, the capacitance per unit area is about 1.3 x 10-'PF/μ2, which means a capacitance of 0.01 μF. When I try to make it, 28fflII
The area required for one opening greatly exceeds the chip area, making it impractical. Recently, as a method to increase the capacitance per unit area, a silicon substrate is trench-etched to form a groove, a thin film of oxide or tin oxide is formed on the sides of the groove, and then the groove is filled with polysilicon. A capacitor with a trench structure in which an impurity such as phosphorus is diffused into silicon to serve as one electrode and a substrate as the other electrode has been proposed and has been adopted in DRAMs.
上述した従来のトレンチ構造の容量は平面構成のものに
比較して大きな容量値が得られるものの、バイポーラア
ナログICにおいて使用される位相補償用やフィルタ特
性決定用の容量はその容量値に極めて大きなものが要求
されるため、トレンチ構造で容量を構成した場合でも、
その占有面積が大きなものとなり、ICチップに内蔵す
ることは困難である。Although the conventional trench structure described above has a larger capacitance value than that of the planar structure, the capacitance values for phase compensation and filter characteristic determination used in bipolar analog ICs are extremely large. is required, so even if the capacitance is configured with a trench structure,
The area it occupies is large, making it difficult to incorporate it into an IC chip.
本発明は単位面積当たりの容量値を太き(して小面積で
かつ大容量値の容量を提供することを目的としている。An object of the present invention is to increase the capacitance value per unit area (to provide a capacitor with a small area and a large capacitance value).
本発明の半導体装置は、半導体基板に形成されたトレン
チの周囲に形成した導電層と、このトレンチの内面に形
成した絶縁膜と、この絶縁膜の内側に形成した導電膜と
で容量を構成し、かつこの導電膜の内側に絶縁膜と導電
膜とを交互にかつ多層に形成して複数個の容量を積層状
態に構成している。In the semiconductor device of the present invention, a capacitor is formed by a conductive layer formed around a trench formed in a semiconductor substrate, an insulating film formed on the inner surface of this trench, and a conductive film formed inside this insulating film. , and inside this conductive film, insulating films and conductive films are alternately formed in multiple layers to form a plurality of capacitors in a stacked state.
〔作用〕
上述゛した構成では、複数個の容量がトレンチ内に多層
に形成されるため、同一の面積において複数倍の容量値
を構成できる。[Operation] In the above-described configuration, since a plurality of capacitors are formed in multiple layers within the trench, a plurality of capacitance values can be constructed in the same area.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の断面図であり、第2図(a
)乃至(c)はその製造工程の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention, and FIG.
) to (c) are cross-sectional views of the manufacturing process.
第1図において、1はP型半導体基板であり、表面にN
型エピタキシャル層2が成長されている。In FIG. 1, 1 is a P-type semiconductor substrate, with N on the surface.
A type epitaxial layer 2 is grown.
そして、このN型エピタキシャル層に複数のトレンチ(
溝)4が形成されている。外側に形成したトレンチ4内
には酸化膜5aを形成してエピタキシャル層2を分離さ
せ、この間に容量領域を画成してトランジスタ等の素子
領域との電気的絶縁を図っている。また、N型エピタキ
シャルN2の表面にも酸化膜5bを形成している。Then, a plurality of trenches (
Groove) 4 is formed. An oxide film 5a is formed in the trench 4 formed on the outside to separate the epitaxial layer 2, and a capacitance region is defined between the oxide films 5a and the trench 4 is electrically insulated from an element region such as a transistor. Further, an oxide film 5b is also formed on the surface of the N-type epitaxial layer N2.
内側のトレンチ4の周囲の基板1及びエピタキシャル層
2には容量電極としての導電層、ここではN型不純物拡
散領域6を形成している。また、このトレンチ4の内面
には第1絶縁膜7としての窒化膜を形成している。更に
、この内側に第1導電膜8をポリシリコンで形成し、前
記N型不純物拡散領域6.第1絶縁膜7及び第1導電膜
8で第1容量を構成している。A conductive layer as a capacitor electrode, here an N-type impurity diffusion region 6, is formed in the substrate 1 and epitaxial layer 2 around the inner trench 4. Further, a nitride film as a first insulating film 7 is formed on the inner surface of the trench 4. Furthermore, a first conductive film 8 is formed of polysilicon inside this, and the N-type impurity diffusion region 6. The first insulating film 7 and the first conductive film 8 constitute a first capacitor.
また、前記第1導電膜8の内側に第2絶縁膜9としての
窒化膜9を形成し、この内側に更に第2導電n’J10
をポリシリコンで形成し、前記第1導電膜8.第2絶縁
膜9及び第2導電膜10で第2容量を構成している。Further, a nitride film 9 as a second insulating film 9 is formed inside the first conductive film 8, and a second conductive film n'J10 is further formed inside this.
is formed of polysilicon, and the first conductive film 8. The second insulating film 9 and the second conductive film 10 constitute a second capacitor.
そして、全面が酸化膜11で絶縁され、この酸化膜11
に開設したコンタクトホールを通してアルミニウム電極
12が電気接続されている。Then, the entire surface is insulated with an oxide film 11, and this oxide film 11
An aluminum electrode 12 is electrically connected through a contact hole formed in the aluminum electrode 12 .
上述した構造の製造方法を、第2図を用いて説明する。A method of manufacturing the above-described structure will be explained using FIG. 2.
−
先ず、第2図(a)に示すように、P型半導体基板1上
のN型エピタキシャル層2に酸化膜3を1μm成長させ
部分的にフッ酸などでエツチングした後、トレンチエツ
チングによって深さ5〜10μmの基板1に達するトレ
ンチ4を形成する。- First, as shown in FIG. 2(a), an oxide film 3 is grown to a thickness of 1 μm on an N-type epitaxial layer 2 on a P-type semiconductor substrate 1, partially etched with hydrofluoric acid, etc., and then trench-etched to a depth of 1 μm. A trench 4 reaching the substrate 1 with a thickness of 5 to 10 μm is formed.
次に、全面にチッ化膜を成長させた後、絶縁を行う溝の
表面部分に形成した窒化膜を選択的にエツチングし、第
2図(b)のように、外側のトレンチ4の内部及びエピ
タキシャルN2の表面に夫々同時に酸化膜5a、5bを
形成する。Next, after growing a nitride film over the entire surface, the nitride film formed on the surface of the trench for insulation is selectively etched, and as shown in FIG. Oxide films 5a and 5b are simultaneously formed on the surface of the epitaxial layer N2.
次に、窒化膜を除去した上で、前記酸化膜5bをマスク
としてN型不純物例えばリンをエネルギ70KeV、打
込み量I XIO”cm−”でイオン注入し、かつ10
00°c1〜2時間で熱拡散を行って、内側のトレンチ
4の周囲の基板1及びエピタキシャル層2にN型不純物
拡散領域6を形成する。その後、内側のトレンチ4の内
面に第1絶縁膜としての窒化膜7を厚さ300〜500
人で気相成長させる。Next, after removing the nitride film, using the oxide film 5b as a mask, an N-type impurity such as phosphorus is ion-implanted at an energy of 70 KeV and an implantation amount of IXIO"cm-".
Thermal diffusion is performed for 1 to 2 hours at 00°C to form an N-type impurity diffusion region 6 in the substrate 1 and epitaxial layer 2 around the inner trench 4. After that, a nitride film 7 as a first insulating film is formed on the inner surface of the inner trench 4 to a thickness of 300 to 500
Grown by vapor phase in humans.
次いで、第2図(C)に示すように、ポリシリコンを1
000人〜2000人気相成長させ高濃度にAsをイオ
ン注入し、第1導電膜8を形成する。Next, as shown in FIG. 2(C), 1 layer of polysilicon is
The first conductive film 8 is formed by growing a phase of 0.000 to 2000 and then implanting As ions at a high concentration.
以下、第1図に示したように、第1絶縁膜7しての窒化
膜9を厚さ300〜500人で気相成長させる。その後
、ポリシリコンを2000〜4000人で成長させ、か
つポリシリコン中にヒ素又はリンを高濃度にドープして
第2導電膜10を形成する。Thereafter, as shown in FIG. 1, a nitride film 9 serving as the first insulating film 7 is grown in a vapor phase to a thickness of 300 to 500 nm. Thereafter, polysilicon is grown by 2,000 to 4,000 people, and the polysilicon is doped with arsenic or phosphorus at a high concentration to form the second conductive film 10.
以下、通常の電極形成工程により、酸化膜11を0.4
μで成長させコンタクトの窓を開けた後、アルミニウム
を蒸着し、フォトレジストをマスクとして、ドライエツ
チングによってパターニングし電極12を形成する。Thereafter, the oxide film 11 is formed by 0.4
After growth with μ and opening a contact window, aluminum is vapor deposited and patterned by dry etching using a photoresist as a mask to form the electrode 12.
この構成によれば、トレンチ内に形成した2層構造の容
量を並列接続することにより、同一面積に対して略2倍
の容量値を得ることができ、トレンチ構造の容量値が大
きいことに加えて更に大きな容量値を得ることができる
。したがって、半導体装置における同一面積で約2倍の
容量値を得ることができ、バイポーラアナログIC等へ
の適用が可能となる。According to this configuration, by connecting the capacitors of the two-layer structure formed in the trench in parallel, it is possible to obtain approximately twice the capacitance value for the same area, and in addition to the large capacitance value of the trench structure. Even larger capacitance values can be obtained. Therefore, approximately twice the capacitance value can be obtained with the same area in a semiconductor device, and application to bipolar analog ICs and the like is possible.
ココで、窒化膜、ポリシリコンはスパッタ法で形成する
方法もあるが、現在のプロセス技術では溝内の膜厚の均
一性に問題があり、本実施例のように気相成長(CVD
)法で形成することが好ましい。Here, there is a method to form the nitride film and polysilicon by sputtering, but the current process technology has a problem with the uniformity of the film thickness within the trench, and as in this example, vapor phase growth (CVD) is used to form the nitride film and polysilicon.
) method is preferable.
なお、前記実施例では容量を2層構造とした場合につい
て説明したが、3層以上に構成してもよいことは言うま
でもない。また、絶縁膜として窒化膜を用いているが、
高誘電体材料、例えばタンタルオキサイドTazO□を
使えばさらに大幅に容量値を大きくすることができる。In the above embodiment, the case where the capacitor has a two-layer structure has been described, but it goes without saying that the capacitor may have a structure of three or more layers. In addition, although a nitride film is used as the insulating film,
If a high dielectric material such as tantalum oxide TazO□ is used, the capacitance value can be further increased significantly.
以上説明したように本発明は、半導体基板に形成された
トレンチ内に絶縁膜と導電膜を交互にかつ多層に形成し
て複数個の容量を積層状態に構成しているので、同一の
面積に対して複数倍の容量を得ることができ、大容量値
の容量を半導体基板上に高密度に形成できる効果がある
。また、大容量値の容量を半導体装置内に構成すること
により、従来外付けしていた容量を焼灼でき、半導体装
置のピン数の削減、調整工数の削減を行うことができる
効果もある。As explained above, in the present invention, insulating films and conductive films are formed alternately and in multiple layers in a trench formed in a semiconductor substrate, and a plurality of capacitors are configured in a stacked state. This has the effect that a capacitance that is several times larger than that of the semiconductor substrate can be obtained, and that capacitors with large capacitance values can be formed at high density on a semiconductor substrate. Further, by configuring a capacitor with a large capacitance value within the semiconductor device, it is possible to cauterize the capacitor that was conventionally attached externally, and there is also an effect that the number of pins of the semiconductor device and the number of adjustment steps can be reduced.
第1図は本発明の一実施例の断面図、第2図(a)乃至
(C)はその製造方法を工程順に示す断面図である。
1・・・P型半導体基板、2・・・N型エピタキシャル
層、3・・・酸化膜、4・・・トレンチ、5a、5b・
・・酸化膜、6・・・N型不純物拡散領域、7・・・第
1絶縁膜、8・・・第1導電膜、9・・・第2絶縁膜、
10・・・第2導電膜、11・・・酸化膜、12・・・
アルミニウム電極。
第“2図FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2(a) to 2(C) are sectional views showing the manufacturing method in order of steps. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type epitaxial layer, 3... Oxide film, 4... Trench, 5a, 5b.
... Oxide film, 6... N-type impurity diffusion region, 7... First insulating film, 8... First conductive film, 9... Second insulating film,
10... Second conductive film, 11... Oxide film, 12...
Aluminum electrode. Figure 2
Claims (1)
導電層と、このトレンチの内面に形成した絶縁膜と、こ
の絶縁膜の内側に形成した導電膜とで容量を構成し、か
つこの導電膜の内側に絶縁膜と導電膜とを交互にかつ多
層に形成して複数個の容量を積層状態に構成したことを
特徴とする半導体装置。1. A capacitor is constituted by a conductive layer formed around a trench formed in a semiconductor substrate, an insulating film formed on the inner surface of this trench, and a conductive film formed inside this insulating film, and this conductive film 1. A semiconductor device characterized in that a plurality of capacitors are configured in a stacked state by alternately forming insulating films and conductive films in multiple layers inside the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63046558A JPH01220856A (en) | 1988-02-29 | 1988-02-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63046558A JPH01220856A (en) | 1988-02-29 | 1988-02-29 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01220856A true JPH01220856A (en) | 1989-09-04 |
Family
ID=12750654
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63046558A Pending JPH01220856A (en) | 1988-02-29 | 1988-02-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01220856A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100308640B1 (en) * | 1998-06-30 | 2001-11-15 | 한신혁 | Core type trench capacitor and fabrication method thereof |
JP2009515353A (en) * | 2005-11-08 | 2009-04-09 | エヌエックスピー ビー ヴィ | Integrated capacitor placement for extremely high capacitance values |
JP2016162904A (en) * | 2015-03-03 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
CN111630663A (en) * | 2018-12-28 | 2020-09-04 | 深圳市汇顶科技股份有限公司 | Capacitor and manufacturing method thereof |
-
1988
- 1988-02-29 JP JP63046558A patent/JPH01220856A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100308640B1 (en) * | 1998-06-30 | 2001-11-15 | 한신혁 | Core type trench capacitor and fabrication method thereof |
JP2009515353A (en) * | 2005-11-08 | 2009-04-09 | エヌエックスピー ビー ヴィ | Integrated capacitor placement for extremely high capacitance values |
TWI415270B (en) * | 2005-11-08 | 2013-11-11 | Nxp Bv | Integrated capacitor arrangement for ultrahigh capacitance values |
JP2016162904A (en) * | 2015-03-03 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
CN111630663A (en) * | 2018-12-28 | 2020-09-04 | 深圳市汇顶科技股份有限公司 | Capacitor and manufacturing method thereof |
EP3758067A4 (en) * | 2018-12-28 | 2021-04-14 | Shenzhen Goodix Technology Co., Ltd. | Capacitor and manufacturing method therefor |
US11903182B2 (en) | 2018-12-28 | 2024-02-13 | Shenzhen GOODIX Technology Co., Ltd. | Capacitor and manufacturing method therefor |
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