KR100308640B1 - Core type trench capacitor and fabrication method thereof - Google Patents

Abstract

The present invention relates to a core-type trench capacitor and a method of manufacturing the same, which allow a large surface area to be obtained through an uneven storage node electrode having a core therein. For this purpose, the trench capacitor according to the present invention includes a core inside a trench. It is formed of a core-shaped trench capacitor having a roughly W-shape uneven shape, and the storage node electrode, the capacitor insulating film and the plate electrode are formed to a predetermined thickness along the inner wall of the trench and the outer wall of the core facing the trench. Therefore, the core trench capacitor of the present invention can secure a stable capacitance sufficiently by forming a large surface area of the storage node electrode.

Description

CORE TYPE TRENCH CAPACITOR AND FABRICATION METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (DRAM), and more particularly, to a core trench capacitor employed in a DRAM having a high density and a method of manufacturing the same.

In recent years, one of the biggest problems that arise in reality due to the high integration of semiconductor memory devices is to effectively reduce the footprint (or thickness) on the substrate occupied by the capacitor, where the suppression of the capacitor occupies the DRAM cell capacitor. Consideration should be given to ensuring a stable capacitance at.

That is, since the capacitance of the cell capacitor is proportional to the area of the dielectric / thickness of the dielectric, a method of reducing the thickness of the dielectric for high integration of the DRAM is limited due to leakage current or the like. Therefore, in order to secure stable capacitance, it is necessary to increase the area of the dielectric. In consideration of this, as a capacitor structure, a technology for securing stable capacitance of a capacitor is formed by forming a charge storage node electrode in a cylindrical shape to increase the surface area. It is.

On the other hand, the above-described cylindrical capacitor contributes to high integration to some extent, that is, it can be applied to technologies such as 4M and 16M DRAM, but stable capacitance in DRAMs requiring a higher degree of integration, for example, high density DRAM of 64M or more. It was not possible to obtain sufficient surface area to obtain.

Accordingly, an object of the present invention is to provide a core trench capacitor capable of obtaining a large surface area by forming a convex-concave storage node electrode having a core therein in a capacitor.

Another object of the present invention is to provide a method of manufacturing a core trench capacitor which can obtain a large surface area by forming a storage node electrode in a capacitor in a concave-convex shape having a core therein.

According to an aspect of the present invention, there is provided a trench capacitor for a DRAM formed in a silicon substrate in a structure in which a storage node electrode, a capacitor insulating film, and a plate electrode are sequentially formed along an inner wall of the trench, wherein the trench capacitor includes: And a core-type trench capacitor having a concave-convex shape having a core inside the trench, wherein the storage node electrode, the capacitor insulating film, and the plate electrode are sequentially formed with a predetermined thickness along an inner wall of the trench and an outer wall of the core facing the trench. A core trench capacitor is provided.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a trench capacitor for a DRAM, which is formed in a silicon substrate in such a manner that a storage node electrode, a capacitor insulating film, and a plate electrode are sequentially formed along an inner wall of the trench. Forming a first dielectric mask pattern by laminating a first dielectric layer on the silicon substrate, applying a photosensitive resist layer, and then performing a photolithography process; Forming an external trench pattern by dry etching a portion of the first dielectric layer by using the formed first dielectric mask pattern as a mask, and stripping the first dielectric mask pattern; Sequentially forming a second dielectric layer and a polysilicon layer over the formed outer trench pattern and an upper portion of the silicon substrate, and etching back and removing the polysilicon layer existing on the outer trench pattern; Forming an internal trench pattern by removing a portion of the second dielectric layer through a dry etch using the remaining polysilicon film as a mask; Performing a dry etch using the core trench forming mask pattern formed of the formed outer trench pattern and the formed inner trench pattern to form a core trench in the silicon substrate in the form of a W-shaped concave-convex shape having a core therein; process; And sequentially forming the storage node electrode, the capacitor insulating film, and the plate electrode of a predetermined thickness along an inner wall of the core trench and an outer wall of the core facing the core trench.

According to another aspect of the present invention, there is provided a method of manufacturing a trench capacitor for a DRAM, which is formed in a silicon substrate in such a manner that a storage node electrode, a capacitor insulating film, and a plate electrode are sequentially formed along an inner wall of the trench. Forming a first dielectric mask pattern by laminating a first dielectric layer on the silicon substrate, applying a first photosensitive resist layer, and performing a photolithography process using an internal trench pattern mask; Forming an internal trench pattern by dry etching a portion of the first dielectric layer by using the formed first dielectric mask pattern as a mask, and stripping the first dielectric mask pattern; A second dielectric layer and a second photosensitive resist layer are sequentially formed over the formed inner trench pattern and the upper portion of the silicon substrate, and a photolithography process using an external trench pattern mask is performed to form a second dielectric mask pattern. Process of doing; Forming an external trench pattern by dry etching a portion of the second dielectric layer by using the formed second dielectric mask pattern as a mask and stripping the second dielectric mask pattern; Performing a dry etch using the formed trench pattern of the inner trench pattern and the outer trench pattern to form a core trench having a concave-convex shape having a core therein in the silicon substrate; And sequentially forming the storage node electrode, the capacitor insulating film, and the plate electrode of a predetermined thickness along an inner wall of the core trench and an outer wall of the core facing the core trench.

According to still another aspect of the present invention, there is provided a trench capacitor for a DRAM, which is formed in a silicon substrate in a structure in which a storage node electrode, a capacitor insulating film, and a plate electrode are sequentially formed along an inner wall of the trench. A method comprising: depositing a dielectric layer on a silicon substrate, applying a photosensitive resist layer, and performing a photolithography process using a dual structure core trench pattern mask to form a mask pattern for a core dielectric; A part of the dielectric layer is dry-etched and removed by using the formed cored dielectric mask pattern as a mask, and the cored dielectric mask pattern is stripped to form a core trench formation mask pattern formed of an outer trench pattern and an inner trench pattern. Forming process; Performing a dry etch using the formed cored trench forming mask pattern to form a cored trench having a concave-convex shape having a core therein in the silicon substrate; And sequentially forming the storage node electrode, the capacitor insulating film, and the plate electrode of a predetermined thickness along an inner wall of the core trench and an outer wall of the core facing the core trench.

1 is a cross-sectional view of a cored trench capacitor according to a preferred embodiment of the present invention;

FIG. 2 is a plan sectional view taken along the line AA ′ of the core trench capacitor shown in FIG. 1;

3A to 3I are process diagrams sequentially showing respective processes of manufacturing a cored trench capacitor according to an embodiment of the present invention;

4A to 4E are partial process diagrams illustrating a process of forming a mask pattern for a dielectric on which a core is to be formed when manufacturing a cored trench capacitor according to another embodiment of the present invention;

5 illustrates a pattern mask used to form an internal trench pattern of photoresist resist when fabricating a cored trench capacitor according to another embodiment of the present invention;

6 illustrates another pattern mask used to form an external trench pattern of photoresist resist when fabricating a cored trench capacitor in accordance with another embodiment of the present invention;

7A-7C illustrate some process diagrams of forming a cored dielectric mask pattern when fabricating a cored trench capacitor in accordance with another embodiment of the present invention;

FIG. 8 illustrates a dual structure pattern mask used to form a cored trench mask pattern when fabricating a cored trench capacitor in accordance with another embodiment of the present invention. FIG.

<Description of the code | symbol about the principal part of drawing>

10 silicon substrate 11 core

12: trench capacitor 14: field oxide film

121: trench 123: storage node electrode

125 capacitor insulating film 127 plate electrode

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a cross-sectional view of a cored trench capacitor in accordance with a preferred embodiment of the present invention.

Referring to the cross section of FIG. 1, the core trench capacitor 12 according to the present invention, which is formed at a predetermined portion inside the silicon substrate 10, is integrally formed with the silicon substrate 10 at an approximately middle portion of the trench 121. The trench 121 is formed in an uneven shape (preferably W-shaped uneven shape) having the formed core 11 and etched (etched) to a predetermined depth from the surface of the silicon substrate 10 to form an uneven shape. Inside the trench 121, the storage node electrode 123 and the capacitor insulating layer 125 are sequentially formed over the inner wall of the trench and the outer wall of the core 11, and the trench 121 in which the storage node electrode 123 and the capacitor insulating layer 125 is not formed. The plate electrode 127 is buried in the remaining area of the inside), and a field oxide film 14 for insulating between devices is formed on the upper front surface including the upper side of the plate electrode 127. Here, the storage node electrode 123 is electrically connected to a drain diffusion layer (not shown). In addition, although not shown in the drawing because of no significant relationship with the present invention, films of other uses such as bit lines, protective films, and the like are sequentially formed on the field oxide film 14.

In addition, the core 11 formed in the middle portion of the trench 121 in the cored trench capacitor of the present invention has an upper surface formed at least lower than the upper surface of the silicon substrate 10, which is an inner side of the trench 121. The upper surface of the plate electrode 127 buried in the upper portion of the capacitor 121 is formed integrally with at least not higher than the upper surface of the capacitor insulating film 125 extending to the outside of the trench 121 (that is, the upper portion of the silicon substrate where the trench is not formed) This is to ensure the insulating structure between the elements formed in the subsequent process, that is, to prevent leakage current with the neighboring capacitor.

On the other hand, the core trench capacitor according to the present invention shows an elliptical outer structure when viewed from the top, which is shown well in Figure 2 showing a planar cross-sectional view taken along the line AA 'shown in FIG. . That is, a valley is formed along the ellipse between the core 11 formed to protrude upward from the center of the ellipse and the outer side of the trench 121, and is formed along the upper and inner walls of the valley to form the lower end of the trench 121. Storage node electrodes 123 and 123 'and capacitor insulating layers 125 and 125' connected to each other are sequentially formed, and between the capacitor insulating layer 125 formed on the outer side of the trench and the capacitor insulating layer 125 'formed on the core 11 side, respectively. In the plate electrode 127 is embedded.

Accordingly, the present invention forms the structure of the trench capacitor 12 including the storage node electrode 123, the capacitor insulating film 125, and the plate electrode 127 as the core trench capacitor in the form of unevenness as described above. By forming the surface area of the storage node electrode 123 as large as possible, a stable capacitance can be sufficiently secured.

For example, the cored trench capacitor formed in accordance with the present invention has an outer diameter (t1 of FIG. 2) of the trench 121 as 0.25 μm and an inner diameter of the trench 121 (t2 of FIG. 2) (ie, In the case where the trench capacitor 12 is formed with the outer diameter of the core 11) as 0.18 μm, the capacitance is approximately 40% at the same trench depth as compared to the formation of the trench capacitor with a conventional trench structure having no core. It was found to increase.

Therefore, according to the core trench capacitor of the present invention, even if the thickness of the trench capacitor is reduced as much as possible for high integration, it is possible to suppress the depth of the trench (that is, minimize the depth of the trench), which is extremely difficult to implement technically, so that the trench capacitor for DRAM The production of can be realized more easily.

Next, a process of manufacturing the core trench capacitor according to the present invention having the structure as described above will be described.

Example 1

The present embodiment forms an outer trench pattern of a trench by a self-aligning method using polysilicon, and performs polysilicon deposition and dielectric coating on the outer trench pattern to partially etch polysilicon to form an inner trench pattern ( and a method of forming a core trench using a trench pattern mask pattern including the formed inner trench pattern and the outer trench pattern, and based on the technique, as shown in FIG. 1. Similarly, a core trench capacitor in the form of an unevenness having a core in the middle portion of the trench can be formed in the silicon substrate.

3A to 3I are sequential diagrams illustrating each process of manufacturing a cored trench capacitor according to an embodiment of the present invention. In the drawings, only one cored trench capacitor is provided for convenience of description and improvement of understanding. The bay is shown.

First, the silicon oxide film 22 is formed on the entire surface of the silicon substrate 10 by a CVD method such as, for example, Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure CVD (APCVD), or the like. Is formed to a predetermined thickness, a photoresist is applied to the entire upper surface of the silicon oxide film 22, and then a photolithography process is performed, as shown in FIG. ). Here, the portion where the photosensitive resist is developed in the dielectric mask pattern 24 is a region where the trench capacitor is to be formed by a subsequent process.

Next, by using the dielectric mask pattern 24, a predetermined portion of the silicon oxide film 22 (a silicon oxide film region present in the portion where the photosensitive resist is developed) is removed by dry etching to form the dielectric mask pattern 24. By removing the remaining photosensitive resist by a stripping process, an outer trench pattern 22 'for forming a core trench capacitor made of a silicon oxide film is formed, and as shown in FIG. 3B, an outer trench pattern 22 ') And the polysilicon film 26 is deposited over the entire surface of the exposed silicon substrate 10, for example using a CVD method.

Next, as shown in FIG. 3C, after applying the polysilicon film 28 over the entire upper surface of the dielectric layer 26 using the LPCVD method, the etch back of the polysilicon film 28 is applied. By doing so, as shown in Fig. 3D, only the polysilicon film portion on which the mask pattern for dielectric is to be formed remains. At this time, the etch back of the polysilicon film 28 is set at the end of the time when the dielectric layer 26 formed at the bottom thereof is exposed.

Then, the polysilicon film 26 is removed by, for example, a dry etch method using the remaining polysilicon film remaining on the upper portion of the dielectric layer 26 as the dielectric mask pattern 28 ', as shown in FIG. 3E. As described above, an internal trench pattern for forming a core trench capacitor formed of the polysilicon film 28 'and the dielectric layer 26' is formed.

Therefore, through the process as described above, the mask pattern for forming the trench of the core trench capacitor according to the present invention, that is, the trench forming mask comprising the inner trench patterns 26 ', 28' and the outer trench pattern 22 '. A pattern is formed.

Next, dry etching using the trench forming mask pattern as a mask is performed to selectively remove a predetermined portion of the silicon substrate 10 (that is, a silicon substrate region where no mask pattern exists), as shown in FIG. 3F. Similarly, a trench 121 having a core 11 at an approximately middle portion thereof, that is, a trench 121 having a concave-convex shape having a core 11 at the middle portion, is formed in the silicon substrate 10 to a predetermined depth. In this case, the depth of the trench 121 formed in the silicon substrate 10 may be adjusted according to the required capacitance of the capacitor and the cell area.

Meanwhile, as described above, after forming the trench 121 region, dry etching is performed to remove the inner trench patterns 26 'and 28' and the outer trench patterns 22 'in the mask pattern for forming trenches. As shown in 3g, the upper end portion of the core 11 is removed by a predetermined thickness to form the core removal region N. FIG. Here, the core removing region N should be formed to a thickness suitable for accommodating the storage node electrode 123, the capacitor insulating film 125, and the plate electrode 127 formed in a subsequent process. The reason for forming (N) is a capacitor insulating film extending from the upper surface of the plate electrode 127 buried inside the trench 121 to the outside of the trench 121 (that is, a portion of the upper portion of the silicon substrate where the trench is not formed). By forming at least not higher than the upper surface of the 125, it is to ensure the insulation between the elements formed in the subsequent process, that is to prevent leakage current with the neighboring capacitor.

On the other hand, unlike the above, a capacitor insulating film that extends the upper surface of the plate electrode 127 buried inside the trench 121 to the outside of the trench 121 (that is, a portion of the upper portion of the silicon substrate where the trench is not formed). It is not necessary to form the core removal region N as long as it is formed higher than the upper surface of the 125 and can surely prevent leakage current with the neighboring capacitor. That is, in the case of introducing another method for solving the leakage current problem with the neighboring capacitor, the process of forming the core removing region N may be omitted, as shown in FIG. 3G.

Next, a trench 121 having a roughly W-shape uneven shape is formed at a predetermined position in the silicon substrate 10 through the above-described process, and then n-type impurities (for example, on the inner wall of the trench 121) are formed. As) doped material is laminated, and the stacked material is diffused by a diffusion process to form a storage node electrode 123, and ONO (Oxide) is formed on the surface of the storage node electrode 123 by a CVD method. A capacitor insulating film 125 is formed by embedding a dielectric material such as Nitride Oxide) to a predetermined thickness, and the remaining region inside the trench 121 where the storage node electrode 123 and the capacitor insulating film 125 are not formed by a CVD method. By forming a plate electrode 127 by embedding a material such as polysilicon, a core trench capacitor 12 having a structure as shown in FIG. 3H is formed.

Then, dry etching is performed to remove the upper portion of the plate electrode 127, thereby completing the fabrication of the finished cored trench capacitor 12 as shown in FIG. 3I. At this time, although not shown in the drawing, the storage node electrode 123 is electrically connected to the drain diffusion layer, not shown. In addition, through the subsequent processes, various films such as source and drain regions, gate regions, channel regions, field oxide films, and bit lines will be formed, thereby obtaining a completed DRAM having cored trench capacitors according to the present invention.

As described above, according to the present embodiment, a trench forming mask pattern formed of an inner trench pattern and an outer trench pattern is formed, and using this, an uneven shape having a core in the middle portion of the trench (for example, approximately W shape). By forming a core trench capacitor having a concave-convex shape, i.e., greatly expanding the surface area of the storage node electrode, it is possible to easily manufacture a core trench capacitor having stable capacitance without increasing the trench depth.

Example 2

In this embodiment, an internal trench pattern is formed using an internal trench pattern mask prepared after applying a photosensitive resist on a dielectric layer, and a second dielectric layer is laminated and externally formed using an external trench pattern mask prepared after applying a photosensitive resist. It forms a trench pattern, and is different from the above-described Embodiment 1 in view of forming a core type trench by using a trench forming mask pattern comprising the formed inner trench pattern and the outer trench pattern. As shown in FIG. 1, a core trench capacitor in a concave-convex form (for example, an approximately W-shaped concave-convex form) having a core in the middle portion of the trench can be formed in the silicon substrate.

To this end, in the present embodiment, as an example, an internal trench pattern is formed using an internal trench pattern mask as shown in FIG. 5, in which reference numeral 52 denotes a photosensitive resist remaining when performing a photolithography process. Reference numeral 54 denotes a region where the photosensitive resist is removed when the photolithography process is performed. In other words, the resist remaining region 52 is a region in which a core formed integrally with the silicon substrate is formed at an approximately middle portion of the trench in the core-type trench capacitor having an uneven shape.

In addition, in the present embodiment, as an example, an external trench pattern is formed using an external trench pattern mask as shown in FIG. 6, in which the reference numeral 62 denotes that the photosensitive resist is removed when performing a photolithography process. An area is indicated, and reference numeral 64 denotes an area where a photosensitive resist remains when performing a photolithography process. That is, the resist removal region 64 becomes the outer diameter width of the trench in the core trench capacitor in the uneven shape.

Therefore, in the present embodiment, trenches constituting the core trench capacitor 12 are formed between the resist remaining region 52 shown in FIG. 5 and the resist removal region 62 shown in FIG. ), The storage node electrode 123, the capacitor insulating film 125, and the plate electrode 127 are sequentially formed.

4A-4E are some process diagrams illustrating a process of forming a mask pattern for a dielectric on which a core is to be formed when manufacturing a cored trench capacitor according to another embodiment of the present invention.

Referring to FIG. 4A, after depositing the first dielectric layer 42 on the silicon substrate 10 by a method such as CVD, applying a photosensitive resist, a photo using an internal trench pattern mask as shown in FIG. 5. A lithography process is performed to form the dielectric mask pattern 44, and after the portion of the first dielectric layer 42 is removed by dry etching using the formed dielectric mask pattern 44 as a mask, the remaining photosensitive resist (ie, By removing the dielectric mask pattern 44 by stripping, an internal trench pattern 42 'is formed, and as shown in FIG. 4B, a second dielectric layer 46 having a predetermined thickness is deposited by a CVD method or the like. All.

Subsequently, a photosensitive resist is applied to the entire upper surface of the second dielectric layer 46 and then subjected to a photolithography process using an external trench pattern mask as shown in FIG. 6 to form a dielectric mask pattern 48 ( Fig. 4C), after removing a portion of the second dielectric layer 46 by dry etching using the formed dielectric mask pattern 48 as a mask, the remaining photosensitive resist (i.e., dielectric mask pattern 48) is removed by stripping. Thus, the external trench pattern 48 'is formed. That is, as shown in FIG. 4D, the trench forming mask pattern including the outer trench pattern 48 ′ and the inner trench pattern 42 ′ is formed through the above-described process.

Next, dry etching is performed using the trench forming mask patterns 42 'and 48' as a mask to selectively remove a predetermined portion of the silicon substrate 10 (that is, a silicon substrate region where no mask pattern exists). 4E, a trench 121 having a core 11 at its approximately middle portion, that is, a trench 121 having a concave-convex shape having a core 11 at its approximately middle portion, is a silicon substrate 10. It is formed to a predetermined depth inside. In this case, the depth of the trench 121 formed in the silicon substrate 10 may be adjusted according to the capacitance of the capacitor and the area of the cell.

Then, in this embodiment, a portion of the upper end of the core 11 formed integrally with the silicon substrate 10 in the trench is removed to a predetermined thickness, and the storage node is formed along the inner wall of the trench 121 and the outer wall of the core 11. The electrode 123, the capacitor insulating film 125, and the plate electrode 127 are sequentially formed, each of these subsequent processes being substantially the same as the respective processes (ie, FIGS. 3G to 3I) in Embodiment 1 described above. Do. Therefore, detailed description thereof is omitted here for these subsequent processes in order to avoid unnecessary duplication.

Thus, according to this embodiment, as in the above-described embodiment 1, a cored trench capacitor in the form of an approximately W-shaped uneven shape having a core in the middle portion of the trench is formed, i.e., greatly extending the surface area of the storage node electrode. This makes it possible to easily manufacture a cored trench capacitor having a stable capacitance without increasing the trench depth.

Meanwhile, in the present embodiment, when forming a trench forming mask pattern including an outer trench pattern and an inner trench pattern, an inner trench pattern is first formed by using an inner trench pattern mask as shown in FIG. 5, and subsequent steps are performed. Although described as forming an external trench pattern using an external trench pattern mask as shown in FIG. 6, this embodiment is not necessarily limited thereto. Alternatively, the external trench is formed first and the internal trench is later formed. Even if formed, a mask pattern having the same structure as that of the trench forming mask pattern as shown in FIG. 4D can be formed on the silicon substrate.

That is, unlike the present embodiment, even if the outer trench pattern is formed first and the inner trench pattern is formed later to form the final mask pattern for forming the core trench, substantially the same result as in the above-described embodiment 2 can be obtained. have.

Example 3

The present embodiment differs from the above-described Embodiments 1 and 2 by using the prepared cored trench pattern mask (or dual structure trench pattern mask) as shown in FIG. 8. It is formed by a photolithography process. In other words, in this embodiment, a dielectric layer such as a silicon oxide film is laminated on a silicon substrate, a photosensitive resist is applied over the entire surface of the dielectric layer, and then a core having an internal trench pattern and an external trench pattern is prepared using the prepared double structure trench pattern mask. A mask pattern for forming a trench is formed, and a core trench is formed through dry etching using the trench pattern. Therefore, the present embodiment has another effect of more effectively reducing the number of processes for forming the cored trench as compared with the above-described first and second embodiments.

7A-7C are some process diagrams illustrating the formation of a cored dielectric mask pattern when fabricating a cored trench capacitor in accordance with another embodiment of the present invention.

First, in this embodiment, the silicon oxide film 72 is deposited to a predetermined thickness on the entire surface of the silicon substrate 10 by, for example, a CVD method such as low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, and the like. Applying a photoresist to the entire upper surface of the photoresist, and then performing a photolithography process using a dual structure trench pattern mask as shown in Figure 8, as shown in Figure 7a, the upper portion of the silicon oxide film 72 A core dielectric mask pattern 74 'is formed in a portion.

Referring to Fig. 8, reference numeral 82 denotes a region where the photosensitive resist is removed, and reference numerals 84 and 84 'denote regions where the photosensitive resist remains. Accordingly, the resist removal region 82 becomes a region where the storage node electrode 123, the capacitor insulating film 125, and the plate electrode 127 are formed by the following processes, as shown in FIG. The remaining region 84 is a region in which the core 11 formed integrally with the silicon substrate is formed at an approximately middle portion of the trench 121 in the core trench capacitor having a concave-convex shape.

Then, using the core dielectric mask pattern 74 'formed as a mask as a mask, the silicon oxide film 72 stacked below is dry etched to remove a portion thereof, and the core dielectric mask pattern 74' is removed by a stripping process. ), A core trench forming mask pattern 72 'consisting of inner and outer trench patterns is formed as shown in FIG. 7B.

That is, in this embodiment, the silicon oxide film 72 is deposited on the silicon substrate 10, the photosensitive resist is applied, and then a photolithography process using a double structure trench pattern mask as shown in FIG. 8 is performed. Through a simple process, a mask pattern 72 'for forming a core trench having an inner and an outer trench pattern is formed.

Next, by performing dry etching using the core trench forming mask pattern 72 'as a mask, selectively removing a predetermined portion of the silicon substrate 10 (that is, a silicon substrate region where no mask pattern exists), As shown in FIG. 7C, a trench 121 having a core 11 at an approximately middle portion thereof, that is, a trench 121 having a concave-convex shape having a core 11 at an approximately middle portion thereof, is formed inside the silicon substrate 10. It is formed to a predetermined depth. In this case, the depth of the trench 121 formed in the silicon substrate 10 may be adjusted according to the required capacitance of the capacitor and the cell area.

Then, in this embodiment, a portion of the upper end of the core 11 formed integrally with the silicon substrate 10 in the trench is removed to a predetermined thickness, and the storage node is formed along the inner wall of the trench 121 and the outer wall of the core 11. The electrode 123, the capacitor insulating film 125, and the plate electrode 127 are sequentially formed, each of these subsequent processes being performed in each of the above-described processes of Examples 1 and 2 (ie, FIGS. 3G to 3I). Is substantially the same as Therefore, detailed description thereof is omitted here for these subsequent processes in order to avoid unnecessary duplication.

Therefore, according to this embodiment, while reducing the number of manufacturing processes more than the above-described Examples 1 and 2, as in the above-described Examples 1 and 2, the unevenness having a core in the middle of the trench Forming a core trench capacitor in the form of a shape (for example, a roughly W-shaped uneven shape), that is, by expanding the surface area of the storage node electrode largely, a core trench capacitor having stable capacitance without increasing the trench depth is obtained. It can be manufactured easily.

As described above, according to the present invention, a structure of a trench capacitor including a storage node electrode, a capacitor insulating film, and a plate electrode is formed of a core-type trench capacitor having an uneven shape having a core at an intermediate portion thereof, so that the surface area of the storage node electrode is formed. By forming a larger value, a stable capacitance can be sufficiently secured.

Therefore, according to the core trench capacitor of the present invention, even if the thickness of the trench capacitor is reduced as much as possible for high integration, it is possible to suppress the depth of the trench (that is, minimize the depth of the trench), which is extremely difficult to implement technically, so that the trench capacitor for DRAM The production of can be realized more easily.

Claims (9)

A method of manufacturing a trench capacitor for a DRAM formed in a silicon substrate with a structure in which storage node electrodes, capacitor insulating films, and plate electrodes are sequentially formed along inner walls of the trench, Stacking a first dielectric layer on the silicon substrate, applying a photosensitive resist layer, and then performing a photolithography process to form a first dielectric mask pattern; Forming an external trench pattern by dry etching a portion of the first dielectric layer by using the formed first dielectric mask pattern as a mask, and stripping the first dielectric mask pattern; Sequentially forming a second dielectric layer and a polysilicon layer over the formed outer trench pattern and an upper portion of the silicon substrate, and etching back and removing the polysilicon layer existing on the outer trench pattern; Forming an internal trench pattern by removing a portion of the second dielectric through dry etching using the remaining polysilicon film as a mask; Performing a dry etch using the core trench forming mask pattern formed of the formed outer trench pattern and the formed inner trench pattern to form a core trench in the silicon substrate in the form of a W-shaped concave-convex shape having a core therein; process; And And sequentially forming the storage node electrode, the capacitor insulating film, and the plate electrode of a predetermined thickness along an inner wall of the core trench and an outer wall of the core facing the core trench. The method of claim 1, wherein the method further comprises removing the upper end portion of the core formed in the core trench by a predetermined thickness after the core trench is formed. The method of claim 2, wherein an upper end portion of the core is removed by a thickness that accommodates the storage node electrode, the capacitor insulating layer, and the plate electrode. A method of manufacturing a trench capacitor for a DRAM formed in a silicon substrate with a structure in which storage node electrodes, capacitor insulating films, and plate electrodes are sequentially formed along inner walls of the trench, Stacking a first dielectric layer on the silicon substrate, applying a first photosensitive resist layer, and performing a photolithography process using an internal trench pattern mask to form a first dielectric mask pattern; Forming an internal trench pattern by dry etching a portion of the first dielectric layer by using the formed first dielectric mask pattern as a mask, and stripping the first dielectric mask pattern; A second dielectric layer and a second photosensitive resist layer are sequentially formed over the formed inner trench pattern and the upper portion of the silicon substrate, and a photolithography process using an external trench pattern mask is performed to form a second dielectric mask pattern. Process of doing; Forming an external trench pattern by dry etching a portion of the second dielectric layer by using the formed second dielectric mask pattern as a mask and stripping the second dielectric mask pattern; Performing a dry etch using the formed trench pattern of the inner trench pattern and the outer trench pattern to form a core trench having a concave-convex shape having a core therein in the silicon substrate; And And sequentially forming the storage node electrode, the capacitor insulating film, and the plate electrode of a predetermined thickness along an inner wall of the core trench and an outer wall of the core facing the core trench. The method of claim 4, wherein the method further comprises removing a top end portion of the core formed in the core trench by a predetermined thickness after the core trench is formed. The method of claim 5, wherein the upper end of the core is removed by a thickness that accommodates the storage node electrode, the capacitor insulating layer, and the plate electrode. A method of manufacturing a trench capacitor for a DRAM formed in a silicon substrate with a structure in which storage node electrodes, capacitor insulating films, and plate electrodes are sequentially formed along inner walls of the trench, Stacking a dielectric layer on the silicon substrate, applying a photosensitive resist layer, and performing a photolithography process using a dual structure core trench pattern mask to form a mask pattern for a core dielectric; A part of the dielectric layer is dry-etched and removed by using the formed cored dielectric mask pattern as a mask, and the cored dielectric mask pattern is stripped to form a core trench formation mask pattern formed of an outer trench pattern and an inner trench pattern. Forming process; Performing a dry etch using the formed cored trench forming mask pattern to form a cored trench having a concave-convex shape having a core therein in the silicon substrate; And And sequentially forming the storage node electrode, the capacitor insulating film, and the plate electrode of a predetermined thickness along an inner wall of the core trench and an outer wall of the core facing the core trench. 8. The method of claim 7, wherein the method further comprises removing the upper end portion of the core formed in the core trench by a predetermined thickness after the core trench is formed. 9. The method of claim 8, wherein the upper end of the core is removed by a thickness that can accommodate the storage node electrode, the capacitor insulating film, and the plate electrode.