KR20000027832A - Method for forming lower electrode of capacitors - Google Patents

Method for forming lower electrode of capacitors Download PDF

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Publication number
KR20000027832A
KR20000027832A KR1019980045867A KR19980045867A KR20000027832A KR 20000027832 A KR20000027832 A KR 20000027832A KR 1019980045867 A KR1019980045867 A KR 1019980045867A KR 19980045867 A KR19980045867 A KR 19980045867A KR 20000027832 A KR20000027832 A KR 20000027832A
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South Korea
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polysilicon layer
capacitor
lower electrode
oxide film
deposited
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KR1019980045867A
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Korean (ko)
Inventor
은용석
전승준
권오정
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김영환
현대전자산업 주식회사
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Priority to KR1019980045867A priority Critical patent/KR20000027832A/en
Publication of KR20000027832A publication Critical patent/KR20000027832A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for forming a lower electrode of capacitor is provided to improve capacitance of capacitor by forming a charge storage part in the lower electrode. CONSTITUTION: An insulating layer(10) having a contact portion(15) is formed on a substrate. After filling a first polysilicon layer(20) into the contact portion(15), convex/concave portions(30) are formed on the surface of the first polysilicon layer(20) by etching the first polysilicon layer(20) using a first photoresist pattern. An oxide layer(35) is formed on the convex/concave portions of the first polysilicon layer(20). After depositing and etching a second polysilicon layer(40), a lower electrode(A) of capacitor and a charge storage part(50) are simultaneously formed by removing the oxide layer(35) formed between the first and the second polysilicon layers(40).

Description

커패시터의 하부전극형성방법Formation method of lower electrode of capacitor

본 발명은 커패시터(Capacitor)에 관한 것으로서, 특히, 커패시터 하부전극의 제1폴리실리콘층에 요철부위를 형성하고, 연속하여 산화막을 요철부위에 일정한 두께로 적층하여 그 상부면에 제2폴리실리콘층을 적층한 후 식각하여 커패시터 하부전극을 형성하면서 상기 산화막을 제거하여 전하를 저장할 수 있는 전하저장부를 하부전극에 구비하므로 커패시터의 정전용량을 증대시키도록 하는 커패시터의 하부전극형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor, and in particular, an uneven portion is formed on a first polysilicon layer of a capacitor lower electrode, and a second polysilicon layer is formed on the upper surface by successively stacking an oxide film at a constant thickness on the uneven portion. The present invention relates to a method of forming a lower electrode of a capacitor to increase the capacitance of the capacitor because the lower electrode includes a charge storage unit capable of storing charge by removing the oxide layer while forming a capacitor lower electrode by etching the same.

일반적으로, 커패시터는 전하를 저장하여 반도체소자의 동작에 필요한 전하를 저장하게 되는 것으로서, 반도체소자가 고집적화 되어짐에 따라 단위 셀(Cell)의 크기는 작아지면서 소자의 동작에 필요한 정전용량(Capacitance)은 약간 씩 증가하는 것이 일반적인 경향이며, 현재 64M DRAM이상의 소자에서 필요로 하는 정전용량은 셀당 30fF 이상이다.In general, the capacitor stores the charge necessary to operate the semiconductor device. As the semiconductor device becomes highly integrated, the size of the unit cell becomes smaller and the capacitance required for the operation of the device is reduced. A slight increase is a common trend, and the current capacitance required for devices above 64M DRAM is over 30fF per cell.

이와 같이, 반도체소자의 고집적화가 이루어짐에 따라 커패시터 역시 소형화될 것을 요구되어지고 있으나 전하를 저장하는 데 한계에 부딪히게 되어 커패시터는 셀의 크기에 비하여 고집적화시킨 데 어려움이 표출되었으며, 이러한 점을 감안하여 각 업체에서 커패시터의 전하를 저장하기 위한 구조를 다양하게 변화하기에 이르렀으며, 커패시터의 전하를 증가시키는 방법에는 유전상수가 큰 물질을 사용하는 방법, 유전물질의 두께를 낮추는 방법 및 커패시터의 표면적을 늘리는 방법등이 있으며, 최근에는 커패시터의 표면적을 증대시키는 방법이 주로 이용되고 있다.As the semiconductor device is highly integrated, the capacitor is also required to be miniaturized. However, the capacitor has a limitation in storing electric charges, and thus the capacitor is difficult to be integrated with the cell size. Various companies have changed the structure to store the charge of the capacitor in various ways, and the method of increasing the charge of the capacitor is to use a material with a large dielectric constant, to reduce the thickness of the dielectric material and the surface area of the capacitor There is a method of increasing, and in recent years, a method of increasing the surface area of a capacitor is mainly used.

즉, 커패시터의 전하저장전극의 구조를 보면, 크게 전하를 저장하는 전극은 좁은 평면적 위에 여러층을 쌓아서 넓은 커패시터의 면적을 얻고자 하는 적층구조(Stacked Structure)와, 반도체기판에 일정한 깊이의 홈을 형성한 후에 그 부위에 커패시터를 형성하여 전하를 저장하도록 하는 홈 구조(Trench Structure)등으로 크게 대별되어지고 있다.That is, in the structure of the charge storage electrode of the capacitor, the electrode that stores the charge largely has a stacked structure to obtain a large capacitor area by stacking several layers on a narrow plane and a groove having a constant depth in the semiconductor substrate. After the formation, it is largely classified into a trench structure for forming a capacitor at the site and storing charge.

특히, 상기 적층구조(Stacked Structure)는 핀 형상으로 형성된 핀(Fin)타입과, 실린더와 같이 원통형상으로 형성되는 실린더(Cylinder)타입 및 캐비티(Cavity)타입에 변형을 가미한 MPS(Meta-Stable Poly Silicon) 및 벨로즈(Bellows) 등과 같은 변형 커패시터구조등으로 구성되어 커패시터의 충전용량을 증가시키는 노력이 이루어지고 있다.In particular, the stacked structure has a fin-type formed in a pin shape, and a meta-stable poly with a deformation applied to a cylinder type and a cavity type formed in a cylindrical shape such as a cylinder. Efforts have been made to increase the charging capacity of capacitors, which are composed of modified capacitor structures such as silicon) and bellows.

그런데, 상기한 바와 같이, 적층구조는 비교적 공정이 단순하고, 홈구조와 같은 과도한 식각이 불필요하므로 식각에 의한 결함 발생을 줄일 수 있고, 에러에 대하여 강하다는 장점을 지닌 반면에 적층구조는 좁은 평면적 위에 넓은 커패시터면적을 얻어야 하므로 높은 위상차를 피할 수 없고, 점차적으로 반도체소자의 고집적화가 진행됨에 따라 전하를 저장하는 구조를 얻는 데 한계에 부딪히게 되는 문제점을 지니고 있었다.However, as described above, the laminated structure has a relatively simple process and does not require excessive etching, such as a groove structure, thereby reducing the occurrence of defects due to etching, and has the advantage of being strong against errors, while the laminated structure has a narrow planar area. Since a large capacitor area must be obtained above, a high phase difference cannot be avoided, and as the integration of semiconductor devices is gradually progressed, there is a problem in that there is a limit in obtaining a structure for storing charge.

본 발명의 목적은 기판 상에 콘택부위를 형성하고, 이 콘택부위에 제1폴리실리콘층을 증착하여 식각한 후 상부면에 제1감광막을 적층하여 제1폴리실리콘층에 요철부위를 형성하고, 연속하여 산화막을 요철부위에 일정한 두께로 적층하여 그 상부면에 제2폴리실리콘층을 적층한 후 제2감광막을 식각하여 커패시터 하부전극을 형성하면서 상기 산화막을 제거하여 전하를 저장할 수 있는 전하저장부를 하부전극에 구비하므로 커패시터의 정전용량을 증대시키는 것이 목적이다.An object of the present invention is to form a contact portion on the substrate, the first polysilicon layer is deposited and etched on the contact portion and then the first photosensitive film is laminated on the upper surface to form the uneven portion on the first polysilicon layer, Successively, the oxide film is laminated on the uneven portion with a predetermined thickness, and then the second polysilicon layer is laminated on the upper surface thereof. Then, the second photoresist is etched to form a capacitor lower electrode, thereby removing the oxide film and storing a charge therein. Since the lower electrode is provided, the purpose is to increase the capacitance of the capacitor.

도 1 내지 도 6은 본 발명에 따른 커패시터의 하부전극 형성방법을 공정에 거하여 순차적으로 보인 도면이다.1 to 6 are views sequentially showing the method of forming the lower electrode of the capacitor according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : 절연층 15 : 콘택부위10: insulating layer 15: contact portion

20 : 제1폴리실리콘층 25 : 제1감광막20: first polysilicon layer 25: first photosensitive film

30 : 요철부위 35 : 산화막30: uneven portion 35: oxide film

40 : 제2폴리실리콘층 45 : 제2감광막40: second polysilicon layer 45: second photosensitive film

50 : 전하저장부 A : 커패시터하부전극50: charge storage unit A: capacitor lower electrode

이러한 목적은 반도체기판 상에 게이트전극 및 워드라인등을 형성한 후 그 위에 적층된 절연층에 형성된 콘택부위에 제1폴리실리콘층을 형성하는 단계와; 상기 제1폴리실리콘층 상에 일정간격으로 제1감광막을 적층한 후 식각으로 패터닝하여 상부로 노출된 요철부위를 형성하는 단계와; 상기 제1폴리실리콘층의 요철부위에 일정 두께로 산화막을 적층하는 단계와; 상기 결과물의 전면에 제2폴리실리콘층을 적층한 후 제2감광막으로 식각하여 커패시터하부전극을 형성한 후 식각으로 제1,제2폴리실리콘층 사이에 있는 산화막을 식각으로 제거하는 단계로 이루어진 커패시터의 하부전극형성방법을 제공함으로써 달성된다.The object is to form a gate electrode, a word line, etc. on a semiconductor substrate, and then form a first polysilicon layer on the contact portions formed on the insulating layers stacked thereon; Stacking a first photoresist film at a predetermined interval on the first polysilicon layer and patterning the same by etching to form an uneven portion exposed to the top; Stacking an oxide film with a predetermined thickness on the uneven portion of the first polysilicon layer; The second polysilicon layer is stacked on the entire surface of the resultant, and then etched with a second photoresist to form a capacitor lower electrode, and then etching to remove the oxide film between the first and second polysilicon layer by etching. It is achieved by providing a method for forming the lower electrode of.

그리고, 상기 제1폴리실리콘층의 두께는 1500∼3000Å이고, 상기 제1폴리실리콘층의 상부면에 형성되는 요철부위의 식각 깊이는 1000∼2500Å이며, 상기 산화막은 HDP화학기상증착법(High Density Plasma LP-CVD)으로 증착하고, 1000∼2500Å의 두께로 형성되도록 한다.In addition, the thickness of the first polysilicon layer is 1500 ~ 3000Å, the etching depth of the irregularities formed on the upper surface of the first polysilicon layer is 1000 ~ 2500Å, the oxide film is HDP chemical vapor deposition method (High Density Plasma) LP-CVD) to form a thickness of 1000 to 2500 mW.

또한, 상기 산화막을 증착하기 위하여 사용되는 가스는 SiH4/O2/Ar 또는 SiH4/O2/He이며, 증착된 부분에 대하여 식각되는 비율은 25∼45%이고, 상기 제1폴리실리콘층의 요철부위의 홈부분에 적층되는 산화막은 홈깊이의 66.6%정도 증착되며, 상기 제2폴리실리콘층은 500∼2000Å정도로 증착되고, 상기 커패시터하부전극은 한변의 길이가 3㎛∼50㎛인 정사각형, 직사각형 혹은 마름모형 중에 어느 하나인 것이 바람직하다.In addition, the gas used to deposit the oxide film is SiH 4 / O 2 / Ar or SiH 4 / O 2 / He, the ratio of etching to the deposited portion is 25 to 45%, the first polysilicon layer The oxide film deposited on the groove portion of the uneven portion of the film is deposited by about 66.6% of the groove depth, the second polysilicon layer is deposited by about 500 to 2000 microns, and the capacitor lower electrode has a square length of 3 μm to 50 μm on one side. It is preferable that it is either a rectangle or a rhombus.

또한, 상기 제1,제2폴리실리콘층 사이에 잔류된 산화막은 HF 용액 혹은 BOE 용액으로 2∼100초간 제거하는 것이 바람직하다.In addition, the oxide film remaining between the first and second polysilicon layers is preferably removed for 2 to 100 seconds with an HF solution or a BOE solution.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1 내지 도 6은 본 발명에 따른 커패시터의 하부전극 형성방법을 공정에 거하여 순차적으로 보인 도면이다.1 to 6 are views sequentially showing the method of forming the lower electrode of the capacitor according to the present invention.

도 1은 반도체기판 상에 게이트전극 및 워드라인등을 형성한 후 그 위에 적층된 절연층(10)에 형성된 콘택부위(15)에 1500∼3000Å의 두께로 제1폴리실리콘층(20)을 적층하여 식각으로 커패시터의 패턴으로 형성시킨 상태를 도시하고 있다.FIG. 1 illustrates the formation of a gate electrode, a word line, and the like on a semiconductor substrate, and then laminating the first polysilicon layer 20 to a contact region 15 formed on the insulating layer 10 stacked thereon with a thickness of 1500 to 3000 GPa. To form a pattern of capacitors by etching.

그리고, 도 2 및 도 3은 상기 제1폴리실리콘층(20) 상에 일정간격으로 제1감광막(25)을 적층한 후 식각으로 패터닝하여 상부로 노출되고, 식각 깊이가 1000∼2500Å인 요철부위(30)를 형성하는 상태를 도시하고 있으며, 상기 제1폴리실리콘층(20)의 요철부위(30)의 홈부분에 적층되는 산화막(35)은 홈깊이의 66.6%정도 증착되는 것이 바람직하다.2 and 3 show that the first photoresist layer 25 is stacked on the first polysilicon layer 20 at a predetermined interval, and then patterned by etching to expose the upper portion, and the uneven portion having an etching depth of 1000 to 2500Å is formed. 30 shows a state in which the oxide film 35 is laminated on the groove portion of the uneven portion 30 of the first polysilicon layer 20, and is preferably deposited at about 66.6% of the groove depth.

도 4는 상기 제1폴리실리콘층(20)의 요철부위(30)에 일정 두께로 산화막(35)을 적층하는 상태를 도시하고 있으며, 이 산화막(35)은 HDP화학기상증착법(High Density Plasma Chemical Vapor Deposition)으로 증착하고, 1000∼2500Å의 두께로 형성되는 상태를 도시하고 있다.FIG. 4 illustrates a state in which an oxide film 35 is laminated on the uneven portion 30 of the first polysilicon layer 20 to a predetermined thickness, and the oxide film 35 is formed by HDP chemical vapor deposition (High Density Plasma Chemical). Vapor deposition in a thickness of 1000 to 2500 kPa.

이때, 상기 산화막(35)을 증착하기 위하여 사용되는 가스는 SiH4/O2/Ar 또는 SiH4/O2/He이며, 증착된 부분에 대하여 식각되는 비율은 25∼45%로 형성하도록 한다.At this time, the gas used for depositing the oxide film 35 is SiH 4 / O 2 / Ar or SiH 4 / O 2 / He, and the etching rate for the deposited portion is formed to be 25 to 45%.

도 5는 상기 결과물의 전면에 500∼2000Å정도의 두께로 제2폴리실리콘층(40)을 적층한 후 제2감광막(45)을 적층하는 상태를 도시하고 있다.FIG. 5 shows a state in which the second photosensitive film 45 is laminated after the second polysilicon layer 40 is laminated on the entire surface of the resultant with a thickness of about 500 to 2000 kPa.

도 6은 상기 제2폴리실리콘층(40)을 식각하여 요철부위와 교차되는 형상으로 커패시터하부전극(A)을 형성한 후 상기 제1,제2폴리실리콘층(20)(40) 사이에 있는 산화막(35)을 제거하는 상태를 도시하고 있다.6 shows that the second polysilicon layer 40 is etched to form a capacitor lower electrode A in a shape intersecting with the uneven portion, and is located between the first and second polysilicon layers 20 and 40. The state in which the oxide film 35 is removed is shown.

이때, 상기 제1,제2폴리실리콘층(20)(40) 사이에 잔류된 산화막(35)은 HF 용액 혹은 BOE 용액으로 2∼100초간 제거하는 것이 바람직하다.At this time, the oxide film 35 remaining between the first and second polysilicon layers 20 and 40 is preferably removed for 2 to 100 seconds with an HF solution or a BOE solution.

그리고, 상기 커패시터하부전극(A)을 형성한 후에 절연막 및 상부전극을 이루는 폴리실리콘층등을 적층하여 식각하므로 최종적인 커패시터를 형성하도록 한다.After forming the capacitor lower electrode A, an insulating film and a polysilicon layer constituting the upper electrode are stacked and etched to form a final capacitor.

이와 같이 본 발명에 따른 커패시터의 하부전극(A)은 제1,제2폴리실리콘층(20)(40) 사이에 형성된 전하저장부(50)를 이용하여 커패시터의 면적을 증가시키므로 전하를 많이 저장하여 커패시터의 정전용량을 증대시키도록 한다.As described above, the lower electrode A of the capacitor according to the present invention increases the area of the capacitor by using the charge storage unit 50 formed between the first and second polysilicon layers 20 and 40, thus storing a lot of charge. To increase the capacitance of the capacitor.

상기한 바와 같이 본 발명에 따른 커패시터의 하부저극형성방법을 이용하게 되면, 기판 상에 콘택부위를 형성하고, 이 콘택부위에 제1폴리실리콘층을 증착하여 식각한 후 상부면에 제1감광막을 적층하여 제1폴리실리콘층에 요철부위를 형성하고, 연속하여 산화막을 요철부위에 일정한 두께로 적층하여 그 상부면에 제2폴리실리콘층을 적층한 후 제2감광막을 식각하여 커패시터 하부전극을 형성하면서 상기 산화막을 제거하여 전하를 저장할 수 있는 전하저장부를 하부전극에 구비하므로 커패시터의 정전용량을 증대시키도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the method of forming the lower pole of the capacitor according to the present invention is used, a contact portion is formed on a substrate, and a first polysilicon layer is deposited on the contact portion to be etched to form a first photoresist film on the upper surface. To form a concave-convex portion on the first polysilicon layer, and subsequently to deposit an oxide film on a concave-convex portion with a predetermined thickness, to deposit a second polysilicon layer on the upper surface and to etch the second photosensitive film to form a capacitor lower electrode While the oxide film is removed to provide a charge storage portion for storing the charge in the lower electrode is a very useful and effective invention to increase the capacitance of the capacitor.

Claims (8)

반도체소자에서 커패시터를 형성하는 방법에 있어서,In the method of forming a capacitor in a semiconductor device, 반도체기판 상에 게이트전극 및 워드라인등을 형성한 후 그 위에 적층된 절연층에 형성된 콘택부위에 제1폴리실리콘층을 형성하는 단계와;Forming a gate electrode, a word line, and the like on a semiconductor substrate, and then forming a first polysilicon layer on a contact portion formed on the insulating layer stacked thereon; 상기 제1폴리실리콘층 상에 일정간격으로 제1감광막을 적층한 후 식각으로 패터닝하여 상부로 노출된 요철부위를 형성하는 단계와;Stacking a first photoresist film at a predetermined interval on the first polysilicon layer and patterning the same by etching to form an uneven portion exposed to the top; 상기 제1폴리실리콘층의 요철홈 부위 및 요철부위 상부에 산화막을 적층하는 단계와;Stacking an oxide film on the uneven groove portion and the uneven portion of the first polysilicon layer; 상기 결과물의 전면에 제2폴리실리콘층을 적층한 후 제2감광막으로 식각하여 상기 요철부위와 교차되는 형상으로 커패시터하부전극을 형성한 후 식각으로 제1,제2폴리실리콘층 사이에 있는 산화막을 제거하는 단계로 이루어진 것을 특징으로 하는 커패시터의 하부전극형성방법.After stacking the second polysilicon layer on the entire surface of the resultant, the second photoresist layer is etched to form a capacitor lower electrode in a shape intersecting with the uneven portion, and then an oxide layer between the first and second polysilicon layers is etched. The lower electrode forming method of the capacitor, characterized in that consisting of a step of removing. 제 1 항에 있어서, 상기 제1폴리실리콘층의 두께는 1500∼3000Å인 것을 특징으로 하는 커패시터의 하부전극형성방법.The method of claim 1, wherein the thickness of the first polysilicon layer is 1500 to 3000 GPa. 제 1 항에 있어서, 상기 제1폴리실리콘층의 상부면에 형성되는 요철부위의 식각 깊이는 1000∼2500Å인 것을 특징으로 하는 커패시터의 하부전극형성방법.The method of claim 1, wherein the etching depth of the uneven portion formed on the upper surface of the first polysilicon layer is 1000 ~ 2500Å. 제 1 항에 있어서, 상기 산화막은 HDP화학기상증착법으로 증착하고, 1000∼2500Å의 두께로 형성되는 것을 특징으로 하는 커패시터의 하부전극형성방법.The method of claim 1, wherein the oxide film is deposited by HDP chemical vapor deposition and formed to a thickness of 1000 to 2500 mW. 제 1 항 또는 제 4 항에 있어서, 상기 산화막을 증착하기 위하여 사용되는 가스는 SiH4/O2/Ar 또는 SiH4/O2/He이며, 증착된 부분에 대하여 식각되는 비율은 25∼45%인 것을 특징으로 하는 커패시터의 하부전극형성방법.The gas used for depositing the oxide film is SiH 4 / O 2 / Ar or SiH 4 / O 2 / He, and the ratio of etching to the deposited portion is 25 to 45%. The lower electrode forming method of the capacitor, characterized in that. 제 1 항에 있어서, 상기 제1폴리실리콘층의 요철부위의 홈부분에 적층되는 산화막은 홈깊이의 66.6%정도 증착되는 것을 특징으로 하는 커패시터의 하부전극형성방법.The method of claim 1, wherein the oxide film deposited on the groove portion of the uneven portion of the first polysilicon layer is deposited by about 66.6% of the groove depth. 제 1 항에 있어서, 상기 제2폴리실리콘층은 500∼2000Å정도로 증착되는 것을 특징으로 하는 커패시터의 하부전극형성방법.The method of claim 1, wherein the second polysilicon layer is deposited at about 500 to 2000 GPa. 제 1 항에 있어서, 상기 제1,제2폴리실리콘층 사이에 잔류된 산화막은 HF 용액 혹은 BOE 용액으로 2∼100초간 제거하는 것을 특징으로 하는 커패시터의 하부전극형성방법.The method of claim 1, wherein the oxide film remaining between the first and second polysilicon layers is removed with an HF solution or a BOE solution for 2 to 100 seconds.
KR1019980045867A 1998-10-29 1998-10-29 Method for forming lower electrode of capacitors KR20000027832A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050041636A (en) * 2003-10-31 2005-05-04 동부아남반도체 주식회사 Capacitor of semiconductor device and its fabricating method
KR100799129B1 (en) * 2001-12-24 2008-01-29 주식회사 하이닉스반도체 Method of manufacturing capacitor for semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100799129B1 (en) * 2001-12-24 2008-01-29 주식회사 하이닉스반도체 Method of manufacturing capacitor for semiconductor memory device
KR20050041636A (en) * 2003-10-31 2005-05-04 동부아남반도체 주식회사 Capacitor of semiconductor device and its fabricating method

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