KR940011805B1 - Method of fabricating a capacitor with storage electrode - Google Patents

Abstract

The method includes the steps of forming a MOSFET, a BPSG layer (7), a 1st nitride film (8) and a 1st oxide film (9) on the Si substrate to remove the films (9,8,7) by using a contact mask to form a contact hole (11) thereinto, forming a 1st poly-Si layer (12), a 2nd nitride film (13), a 2nd oxide film (14), a 2nd poly-Si layer (15) and a 3rd oxide film (16) thereon, forming a 2nd photoresist pattern (20A) on the film (16) to etch the films (16,15,14) on the drain portion, removing the pattern (20A) to form a 3rd photoresist film (30A) to etch the films (16,15,14,13,12) to form the patterns of the films, removing the film (30A) to deposit and etch a 3rd poly-Si layer (17) thereon to form spacers (17a,17B), and removing the exposed films (13A,9,14A,16A). The surface area of the capacitor electrode is maximized by using the charge storage electrode with the 1st and 2nd poly-Si layer patterns and 3rd poly-Si spacer.

Description

Capacitor charge storage electrode manufacturing method

1 (a) to 1 (j) are cross-sectional views showing a method for manufacturing a charge storage electrode of a DRAM cell according to the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 field oxide film

3: gate oxide film 4: gate electrode

5 source / drain diffusion region 6 insulating layer spacer

7: BPSG layer 8: first nitride film

9: first oxide film 10A: first photosensitive film pattern

11: contact groove 12A: second oxide film pattern

13A: second nitride film pattern 14A: second oxide film pattern

15A: second polysilicon layer pattern 16A: third oxide film pattern

17A, 17B: third polysilicon layer spacer 18: charge storage electrode

20A: second photosensitive film pattern 30A: third photosensitive film pattern

The present invention relates to a method of manufacturing a charge storage electrode of a capacitor in a highly integrated DRAM cell, and more particularly to a method of manufacturing a charge storage electrode that can maximize the surface area of the charge storage electrode of a stacked capacitor.

In general, as the integration is high, the stack capacitor structure of the conventional planar structure reaches its limit. Thus, the capacitor structure is cylindrical, fin structure and the like.

The capacitor structure to be referred to herein below is similar to the cylindrical structure, but an object of the present invention is to provide a method for manufacturing a charge storage electrode of a capacitor having a further increased surface area.

According to the present invention, a MOSFET is formed on a silicon substrate, the BPSG layer 7 is formed flat on the whole, and the first nitride film 8 and the first oxide film 9 are respectively arranged on the BPSG layer 7. Laminating to a thickness and removing the first oxide film 9, the first nitride film 8, and the BPSG 7 from the upper portion of the drain using a charge storage contact mask to form a contact groove 11 having exposed drain. And the first polysilicon layer 12, the second nitride layer 13, the second oxide layer 14, the second polysilicon layer 15, and the third structure on the entire structure including the contact grooves 11. Stacking the oxide film 16 to a predetermined thickness, forming a second photoresist pattern 20A on the third oxide film 16, and then removing the third oxide film 16 of the portion where the photoresist film on the drain is removed, Sequentially etching the second polysilicon layer 15 and the second oxide layer 14, removing the second photoresist layer pattern 20A, and again before storing the charge on the entire structure. A third oxide film 16, a second polysilicon layer 15, a second oxide film 14, a second nitride film 13, in which the third photoresist pattern 30A is formed using a mask, and the photoresist film is removed. Etching the first polysilicon layer 12 to form a pattern of each layer, removing the third photoresist pattern 30A, depositing a third polysilicon layer 17 on the entire structure, and then Etching the third polysilicon layer 17 by an isotropic etching process to form third polysilicon layer spacers 17A and 17B on the outer wall of the pattern of each layer, and exposing the second nitride layer pattern 13A. Removing by wet etching and wet-etching the exposed first oxide layer 9 and the second and third oxide layer patterns 14A and 16A. As a result, the first and second polysilicon layer patterns 12A and 16A) by wet etching to thereby remove the first and second polysilicon layer patterns 12A and 15A and the third pole. The cross-sectional structure of the charge storage electrode 18 with the silicon layer spacers 17A and 17B interconnected is " It is characterized in that the shape is formed.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (a) to 1 (j) are cross-sectional views illustrating a manufacturing step of a charge storage electrode of a DRAM cell according to the present invention.

In FIG. 1 (a), the field oxide film 2 is formed on a predetermined portion of the P-type silicon substrate 1, the gate oxide film 3 and the word silicon polysilicon layer 4A are laminated on the entire structure. The gate electrode 4 is formed by removing a predetermined portion of the polysilicon layer 4A by a word line pattern process, and the source / drain diffusion region 5 is formed by an ion implantation process in the exposed silicon substrate 1. Next, an insulating layer spacer 6 is formed on the sidewall of the gate electrode 4, and the BPSG layer 7, the first nitride film 8, and the first oxide film 9, for example, a TEOS layer, have a predetermined thickness on the entire structure. It is sectional drawing of the state which respectively laminated | stacked.

In order to contact the source storage region 5 with the charge storage electrode to be formed later in FIG. 1 (b), the photosensitive layer 10 is coated on the first oxide layer 9 and the first photosensitive layer 10 of the contact region is removed. It is sectional drawing of the state which formed the 1st photosensitive film pattern 10A.

FIG. 1 (c) shows the source diffusion region 5 by sequentially removing the lower first oxide film 9, first nitride film 8 and BPSG 7 using the first photoresist pattern 10A as a mask. It is sectional drawing of the state which formed the exposed contact groove 11 and removed the photosensitive film pattern 10A.

1 (d) shows the first polysilicon layer 12, the second nitride film 13, the second oxide film 14, the second polysilicon layer 15, and the third oxide film 16 on the entire structure, respectively. It is sectional drawing of the state laminated | stacked by predetermined thickness.

In FIG. 1E, a second photoresist pattern 20A is formed on the third oxide layer 16 to remove a predetermined portion of the upper portion of the drain diffusion region 5, and the third oxide layer 16 of the region where the photoresist layer is removed. 2 is a cross-sectional view of the second polysilicon layer 15 and the second oxide film 14 sequentially etched.

In FIG. 1 (f), after the second photoresist layer pattern 20A is removed, the third photoresist layer pattern 30A is formed on the third oxide layer 16 using the charge storage electrode mask, and the photoresist layer is removed. The oxide layer 16, the second polysilicon layer 15, the second oxide layer 14, the second nitride layer 13, and the first polysilicon layer 12 are sequentially etched to form the third oxide layer pattern 16A, It is sectional drawing of the state which formed the 2nd polysilicon layer pattern 15A, the 2nd oxide film pattern 14A, the 2nd nitride film pattern 13A, and the 1st polysilicon layer pattern 12A.

FIG. 1 (g) illustrates the third polysilicon layer 17 having a predetermined thickness over the entire top of the third oxide pattern 16A to remove the third photosensitive pattern 30A and form a charge storage electrode. It is sectional drawing of the laminated state.

In FIG. 1 (h), the third polysilicon layer 17 is etched by an anisotropic etching process to form the third oxide layer pattern 16A, the second polysilicon layer pattern 15A, the second oxide layer pattern 14A, and the second layer. A third polysilicon layer spacer 17A is formed on the outer wall of the nitride film pattern 13A and the first polysilicon layer pattern 12A, and at the same time, the third oxide film pattern 16A, the second polysilicon layer pattern 15A, A cross-sectional view of the third polysilicon layer spacer 17B formed on the inner sidewall of the second oxide layer pattern 14A, wherein the first polysilicon layer pattern 12A, the second polysilicon layer pattern 15A, and the third layer are formed. It shows that the polysilicon spacers 17A and 17B are interconnected.

FIG. 1 (i) is a cross-sectional view of the second nitride film pattern 13A exposed by the above process by wet etching, for example, to show that the upper surface of the first polysilicon layer pattern 12A is exposed.

The first polysilicon layer pattern 12A and the second polysilicon are removed by wet etching the first oxide film pattern 16A and the oxide film pattern 14A exposed after the process of FIG. 1 (i) or FIG. 1 (i). The charge storage electrode 18 having the structure in which the layer pattern 15A and the third polysilicon layer spacers 17A and 17B are interconnected is " Shows a cross section of ".

After the process, a capacitor is formed by stacking a dielectric layer and a conductive layer for a plate electrode on an exposed surface of the charge storage electrode.

Another embodiment of the present invention is to prevent the bottom portion of the first polysilicon layer pattern 12A from being exposed by performing a process step without forming the first oxide layer 9 formed on the first nitride layer 8. .

As described above, according to the present invention, the charge storage electrode having the maximum surface area can be formed by the first and second polysilicon layer patterns and the third polysilicon layer spacer, and the method of manufacturing the charge storage electrode is an oxide film or a nitride film. And it can be easily formed using the difference in the etching selectivity of the polysilicon layer.

Claims (4)

In the method of manufacturing a capacitor of a DRAM cell, a MOSFET is formed on a silicon substrate, the BPSG layer 7 is formed flat on the whole, and the first nitride film 8 and the first oxide film are formed on the BPSG layer 7. 9) stacking each layer to a predetermined thickness, and removing the first oxide film 9, the first nitride film 8, and the BPSG layer 7 on the drain by using the charge storage contact mask, respectively, to expose the drain. Forming the grooves 11, the first polysilicon layer 12, the second nitride film 13, the second oxide film 14, and the second polysilicon layer on the entire structure including the contact grooves 11; (15) stacking the third oxide film 16 to a predetermined thickness, and forming a second photoresist film pattern 20A on the third oxide film 16, and then removing the photoresist film on the drain portion. Sequentially etching the trioxide layer 16, the second polysilicon layer 15, and the second oxide layer 14, removing the second photoresist layer pattern 20A, and then again The third photoresist layer 30A is formed on the upper portion of the tank by using the charge storage electrode mask, and the third oxide layer 16, the second polysilicon layer 15, the second oxide layer 1, Etching the second nitride film 13 and the first polysilicon layer 12 to form a pattern of each layer, removing the third photoresist layer pattern 30A, and removing the third polysilicon layer 17 on the entire structure. After the deposition, the third polysilicon layer 17 is etched by an anisotropic etching process to form third polysilicon layer spacers 17A and 17B on the outer wall in the pattern of each layer, and the exposed second Removing the nitride film 13A by wet etching and removing the exposed first oxide film 9 and the second and second oxide film patterns 14A and 16A by wet etching, thereby providing the first and second polysilicon. The cross-sectional structure of the charge storage electrode 18 in which the layer patterns 12A and 15A and the third polysilicon layer spacers 17A and 17B are interconnected is " "Charge storage electrode manufacturing method of a capacitor, characterized in that formed in the shape. The method of claim 1, wherein only the first nitride film 8 is stacked on the BPSG layer 17 to a predetermined thickness, and then the contact grooves 11 are formed using a charge storage contact mask. Method of manufacturing a charge storage electrode of a capacitor, characterized in that the process proceeds as follows. The third polysilicon layer spacers 17A and 17B are formed on the inner sidewalls of the third oxide layer pattern 16, the second polysilicon layer pattern 15A, and the second oxide layer pattern 14A. The polysilicon layer spacer 17B is formed, and the third oxide film pattern 16A, the second polysilicon layer pattern 15A, the second oxide film pattern 14A, the second nitride film pattern 13A, and the first polysilicon layer A third polysilicon layer spacer (17A) is formed on the outer wall of the pattern (12A). The lower first nitride film 8 is used as an etch stop barrier layer when the first oxide film 9 and the second and third oxide film patterns 14A and 16A are removed by wet etching. The charge storage electrode manufacturing method of the capacitor.