KR910008122B1 - Semiconductor memory device having stacked capacitor and method of fabricating thereof - Google Patents

Abstract

The semiconductor memory device having double stacked capacitor structure is manufactured by forming a dielectric layer even at the side wall of contact hole formed at cell plate electrode (16) above the drain electrode (6). When charge storage electrode (10,14) is connected with drain electrode. This method provides sufficient capacitance through increase in capacitor surface area to reduce memory cell.

Description

Semiconductor memory device having double stacked capacitor structure and manufacturing method thereof

1 is a cross-sectional view of a semiconductor memory device having a double stacked capacitor structure manufactured according to a conventional method.

2A to 2G are cross-sectional views showing the fabrication process of a semiconductor memory device having a double stacked capacitor structure according to the present invention.

3A to 3G are cross-sectional views illustrating a manufacturing process of a semiconductor memory device having a double stacked capacitor structure in accordance with an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 device isolation oxide film

3: gate oxide films 4 and 4 ': gate electrode and gate electrode line

5 and 17: oxide spacer 6 and 6 ': source and drain regions

7 and 20: oxide film 8 and 16: cell plate electrode

9, 12, and 15: dielectric films 10 and 14: charge storage electrode

13: conductive material spacer 13 ': conductive material

11 and 19: photosensitive material 18: nitride film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a double stacked capacitor structure surrounded by cell plate electrodes up and down around a charge storage electrode, and a method of manufacturing the same. Particularly, a cell plate electrode is used to connect a charge storage electrode to a drain electrode. The present invention relates to a semiconductor memory device having a double stacked capacitor structure in which a dielectric film is also formed on the groove wall surface to increase the capacitor capacity when formed in the trench.

As DRAM semiconductor memory devices have increased in density, capacitor structures have been largely classified into trench and stacked structures, and various structures have been developed so far. In the case of the stacked capacitor structure, the area of the unit cell is reduced due to the increase in the density, and thus the limit is reached in terms of the capacitance of the capacitor. In order to overcome the limitation on the capacitor capacity, the cell plate electrode is centered on the charge storage electrode in the unit structure. In order to increase the capacity of the capacitor by constructing a double stacked capacitor structure surrounding the top and bottom.

In order to construct the structure of the two-layer stacked capacitor, the charge storage electrode must be connected to the drain electrode through the cell plate electrode. Therefore, the size of the contact for contacting the charge storage electrode and the drain electrode was excluded from the surface area of the capacitor electrode.

In the conventional method of forming a double stacked capacitor, a contact (groove) is formed in the cell plate electrode portion on the drain electrode to contact the charge storage electrode and the drain electrode, and then an oxide spacer is formed on the sidewall (cell plate sidewall) of the contact. By forming, the charge storage electrode was connected to the drain electrode while preventing contact between the cell plate electrode and the charge storage electrode. Therefore, the surface area of the capacitor electrode is reduced by this contact size.

Therefore, the present invention forms a capacitor dielectric film on the sidewall (cell plate sidewall) of the contact after forming a contact on the cell plate electrode on the drain electrode in the process of connecting the charge storage electrode and the drain electrode to increase the capacitor capacity in the same area. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a double stacked capacitor structure and a method of manufacturing the same.

Compared to the conventional method, the present invention can increase the capacitor capacity by the side wall surface area of the contact.

Hereinafter, described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view showing a semiconductor memory device having a double stacked capacitor structure formed in accordance with a conventional method. The device isolation oxide film 2 is formed on a silicon substrate 1, and the gate oxide film 3 and the gate conductive material are formed. After forming sequentially, the gate electrode and the gate electrode lines 4 and 4 'are formed by a mask pattern process, and impurities are implanted into the source and drain regions 6 and 6' by ion implantation, and then the oxide film 7 is removed. Forming a double stacked capacitor on the drain region 6 ', the primary plate electrode 8, the capacitor dielectric film 9, and the charge storage electrode 10 on the drain region 6'. The dielectric film 15 and the plate electrode 16 are stacked to form a contact. A contact (groove) is formed in the cell plate electrode 8, and an oxide spacer 17 is formed on the contact wall. 10 is connected to the drain region 6 ' It is shown.

However, the present invention is to fabricate a double stacked capacitor with increased capacitance by forming a dielectric film on the contact wall formed on the conventional cell plate electrode 8, which will be described with reference to FIGS. 2A to 2G.

FIG. 2A sequentially forms the gate oxide film 3 and the gate conductive material in order to form the device isolation oxide film 2 on the silicon substrate 1, and then forms a pattern to form the gate electrode and the gate electrode lines 4 and 4 '. Is a cross-sectional view of the oxide spacer 5 formed on the side wall of the gate electrode 4 after forming the source and drain regions 6 and 6 'of the LDD (Lightly Doped Drain) region by an ion implantation method. .

2B is a cross-sectional view of the oxide film 7 deposited at a predetermined thickness to insulate the gate electrode 4 and the cell plate electrode 8 from each other.

2C illustrates the formation of a primary cell plate electrode 8 by depositing a conductive material for a cell plate electrode on the oxide film 7 and forming a pattern, and then forming a capacitor dielectric film 9 and forming a charge storage electrode. A drain contact mask is formed of the photosensitive material 11 on the drain region 6 'to deposit the conductive material 10' and to connect the conductive material 10 'for the charge storage electrode and the drain region 6'. One state is shown.

FIG. 2D shows the conductive material 10 ', the capacitor dielectric film 9, the cell plate electrode 8, and the oxide film 7 in the portion where the photosensitive material 11 is removed, and then etched again. A cross-sectional view of completely removing the photosensitive material 11 and depositing the capacitor dielectric layer 12 and the conductive material 13 'as a whole, wherein the conductive material 13' is formed on a sidewall of the cell plate electrode 8 of the contact portion. It is deposited to protect the dielectric film.

FIG. 2E shows an anisotropic etching of the conductive material 13 'on the sidewall of the contact portion to form the spacer 13, and then the capacitor on the upper portion of the conductive material 10' and the drain region 6 'of the charge storage electrode. A cross-sectional view of the dielectric film 12 etched by anisotropic etching.

FIG. 2F shows a state in which the charge storage electrode conductive material 14 'is deposited to connect the charge storage electrode conductive material 10' and the drain region 6 '.

FIG. 2G is a cross-sectional view of a state in which the secondary cell plate electrode 16 is formed after the mask pattern is formed to form the charge storage electrodes 10 and 14, the secondary capacitor dielectric layer 15 is formed.

After the above process, an insulator is formed, a bit line is connected to the source region 6, and a protective layer is formed to complete the semiconductor memory device.

3A to 3G are exemplary embodiments for forming a dielectric in the contact region according to the present invention, and the manufacturing processes are the same as those of FIGS. 2A and 2B, and thus will be omitted.

FIG. 3A is a cross-sectional view of the first cell plate conductive material 8 'deposited at a predetermined thickness over the entire area after the process of FIG. 2B.

3B illustrates the formation of the primary cell plate electrode 8 and the primary cell plate electrode 8 of a predetermined portion of the drain region 6 'to connect the charge storage electrode to the drain region 6'. The oxide film 7 is etched to form a drain contact, and a cross-sectional view of a state in which the primary capacitor dielectric film 9 is formed.

3C shows a photosensitive material for an etch back process for depositing a conductive material 10 ′ for a charge storage electrode, depositing a nitride film 18 thereon, and leaving the nitride film 18 only at the bottom of the contact. ) (Or Polyimide or SOG) is shown.

3d illustrates that the etch selectivity of the photosensitive material 19 (or polymide or SOG) and the nitride film 18 is etched back to leave the nitride film 18 only at the bottom of the contact, and then the oxide film 20 It is sectional drawing of state to have grown.

In FIG. 3E, only the nitride film 18 in the bottom portion of the contact is etched, and then the conductive material 10 'for the charge storage electrode in the bottom portion is etched using the oxide film 20 as a mask. 10 is a cross-sectional view of the oxide film 20 used as the mask layer over the capacitor layer and the capacitor dielectric film 9 on the drain region 6 '.

FIG. 3f shows that the charge preservation electrodes 10 and 14 are formed by depositing the conduction material for the charge assist electrode to connect the conductive material 10 'for the charge storage electrode and the drain region 6', and then forming a mask pattern. It is a cross section of the condition.

FIG. 3G is a cross-sectional view of the second cell plate electrode 16 formed after the second capacitor dielectric film 15 is formed.

By using the manufacturing method as described above, a capacitor dielectric film is formed on the sidewalls of the cell plate electrodes of the drain contact portion, thereby increasing the surface area of the charge storage electrode, thereby increasing the capacitor storage capacity as compared with the conventional structure.

Claims (5)

A method of manufacturing a semiconductor memory device, comprising forming a MOSFET on a silicon substrate 1 and forming a double stacked capacitor connected to the drain region 6 'of the MOSFET, wherein the double stacked capacitor is formed. The step of forming a semiconductor device comprises: forming a primary cell plate electrode 8, a dielectric film 9, and a conductive material 10 'for charge storage electrodes on the drain region 6'; Forming a contact groove on a predetermined portion of the conductive material 10 ', the dielectric film 9, the primary cell plate electrode 8, and the drain region 6' of the insulator 7. Forming a dielectric film 12 and a conductive material 13 'on the conductive material 10' for the charge storage electrode, and forming the conductive material spacer 13 on the contact side wall by anisotropic etching; Etching back the exposed dielectric film 12 above and below the electrode conductive material 10 '; The charge storage electrode conductive material 14 'is formed over the entire region to connect the charge storage electrode conductive material 10' to the drain region 6 ', and then the charge storage electrodes 10 and 14 are subjected to a mask pattern process. ), Forming a dielectric film 15 on the charge storage electrodes 10 and 14, and forming a conductive material for the secondary cell plate electrode on the dielectric film 15. A method of manufacturing a semiconductor memory device having a double stacked capacitor structure, comprising forming a secondary cell plate electrode (16) by a mask pattern process to form a dielectric on the contact side walls. 2. The process of claim 1, wherein the forming of the double stacked capacitor comprises forming a primary plate electrode 8 over the drain 6 'and forming a primary plate electrode 8 on the drain region 6'. And forming a contact groove in a portion of the insulator (7), and forming a dielectric (9) and a conductive material (10 ') for the charge storage electrode on the contact and the primary cell plate electrode (8), respectively. And removing a portion of the conductive material 10 'for the charge storage electrode and the dielectric layer 9 under the contact, and the conductive material 10' for the charge storage electrode 10 'and the drain region 6'. Forming and connecting a conductive material for the charge storage electrode and forming the charge storage electrodes 10 and 14 by a mask pattern process, and forming a dielectric 15 on the charge storage electrodes 10 and 14. The conductive material for the secondary cell plate electrode is formed and the secondary cell plate electrode 16 is formed by a mask pattern process. A method for fabricating a semiconductor memory device having a stacked capacitor structure of the second comprising the steps: 3. The method of claim 2, wherein the removing of the portion of the conductive material 10 ′ for the charge storage electrode and the dielectric 9 under the contact is performed on the nitride film 18 over the conductive material 10 ′ for the charge storage electrode. ) And the photosensitive material 19 or polyamide or SOG), and the photosensitive material 19 on the conductive material 10 'for the charge preserving electrode, leaving only the lower nitride film 18 by the etch back process. Removing the nitride film 18, growing an oxide film 20 over the exposed conductive material 10 'for the charge storage electrode, and using the oxide film 20 as an etch barrier layer. (18) and etching the conductive material 10 'for the lower portion of the charge preserving electrode, and removing the oxide film 20 and the dielectric film 9 under the contact. A method of manufacturing a semiconductor memory device having a capacitor structure. In a semiconductor memory device in which a MOSFET is formed on a silicon substrate and a double stacked capacitor is formed over the MOSFET drain region 6 ', the double stacked capacitor structure has a cell plate electrode 8 and 16 having a charge storage electrode 10. And a capacitor dielectric film 9 and 15 formed between the electrodes, and the charge storage electrodes 10 and 14 are connected on the drain region 6 ', and the primary cell plate. A semiconductor memory device having a double stacked capacitor structure, which is connected through a contact formed in an electrode (8), and the contact side wall has a dielectric film (12) formed to increase the capacitor surface area per unit area. 5. The semiconductor memory device according to claim 4, wherein the charge storage electrode upper dielectric film (15) and the lower dielectric film (9) are connected to the dielectric film (12) on the contact side wall.

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