JPH07118521B2 - Semiconductor memory device having two-layer laminated capacitor structure and method of manufacturing the same - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a two-layer laminated capacitor structure and a method for manufacturing the same, and particularly to a large number of electrodes formed in the two-layer laminated capacitor structure. The present invention relates to a semiconductor memory device having a two-layer laminated capacitor structure in which a dielectric film is also formed on a wall surface of the contact hole when forming a contact hole for interconnecting each other, and a manufacturing method thereof. is there.

[Prior Art] DRAM semiconductor memory devices have been categorized into trench type and laminated type structures due to an increase in the degree of integration, and various structures have been developed to date. In the case of the multilayer capacitor structure, the area of the unit cell is reduced due to the increase in the degree of integration, and the capacity side of the capacitor reaches its limit. In order to overcome the limitation on the capacitance of the capacitor, as an example, a method of forming a plate electrode in a two-layer capacitor structure sandwiched vertically with a charge storage electrode as a center, and as another example, a first and a second method A method of forming a secondary charge storage electrode in a two-layer laminated capacitor structure in which sandwiched vertically around a plate electrode has been proposed.

The conventional method of forming a two-layer laminated capacitor is to form a contact hole at a certain portion of the plate electrode on the drain electrode in order to contact the charge storage electrode and the drain electrode of the above-mentioned example, or to form the contact hole of the above-mentioned other example. When a contact hole is formed in a certain portion of the plate electrode above the primary charge storage electrode to connect the secondary charge storage electrode and the primary charge storage electrode to each other, a sidewall of the contact hole (a side wall of the plate and the electrode is formed). By forming an oxide film spacer on
Short circuit between plate electrode and charge storage electrode (short: Sho
While preventing the rt), the respective electrodes and the like to be contacted were brought into contact with each other.

[Problems to be Solved by the Invention] However, by forming an oxide film spacer on the side surface of the contact hole, the oxide film spacer cannot be used as a dielectric, so that the effective surface area of the capacitor is reduced by the side wall of the oxide film spacer. did.

Therefore, according to the present invention, a dielectric film is formed instead of the insulating film spacer on the sidewall of the contact hole in order to increase the capacitance of the capacitor, rather than the same two-layer laminated capacitor structure as that of the above-described various conventional embodiments. It is an object of the present invention to provide a semiconductor memory device having a two-layer laminated capacitor having an increased effective area of the capacitor and a manufacturing method thereof.

Therefore, according to the present invention, a capacitor capacitance larger than the surface integral of the dielectric formed on the side surface of the contact hole can be obtained as compared with the conventional two-layer laminated capacitor structure.

[Means for Solving the Problems] In order to achieve such an object, one feature of the present invention is that a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an upper portion thereof is formed. In a method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure configured to be electrically connected to a MOSFET having an insulating oxide film formed thereon and the MOSFET drain region, the two-layer laminated capacitor is formed. The process includes forming a first plate electrode on the insulating oxide film above the gate electrode line through the drain region above a portion of the upper portion of the gate electrode, and forming a portion of the upper portion of the first plate electrode above the first plate electrode. After forming the first dielectric film, a conductive material layer for the first charge storage electrode is formed on the entire surface, and the conductive material for the first charge storage electrode is formed on the drain region. A step of forming a part of the first dielectric film, the first plate electrode and the insulating oxide film, and forming a conductive material for the second dielectric film and the spacer on the entire surface, Forming a conductive material spacer on the wall surface of the contact hole by anisotropically etching the conductive material; and exposing the exposed second dielectric film on the conductive material layer for the first charge storage electrode and the drain region. Then, a conductive material layer for the second charge storage electrode is formed on the exposed whole surface, and the conductive material layer for the charge storage electrode is masked with the first and other conductive material layers connected to each other. Forming a charge storage electrode by a process, and electrically connecting the charge storage electrode to the drain region through a contact hole having a dielectric film formed on a side wall thereof; The third dielectric film is formed on the pole and the second plate electrode is formed on the third dielectric film.

In order to achieve such an object, another feature of the present invention is a MOSFET in which a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on them. In the method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure configured to be electrically connected to the drain region of the MOSFET, the step of forming the two-layer laminated capacitor includes: Forming a first plate electrode on the insulating oxide film above the gate electrode line through the upper part, and a part of the first plate electrode and the insulating oxide film formed above the gate region in a contact mask pattern A step of sequentially etching to form a contact by a treatment, and forming a contact on the first plate electrode and the contact hole. Forming a body film and forming a conductive material layer for the first charge storage electrode on the exposed whole surface; and removing a nitride film on the conductive material layer for the first charge storage electrode. A step of growing a thermal oxide film on the exposed conductive material layer for the first charge storage electrode and a step of etching the nitride film remaining in the contact hole using the thermal oxide film as a mask layer. Removing the thermal oxide film and the first dielectric exposed under the contact hole after etching the conductive material layer for the first charge storage electrode under the exposed contact hole. The conductive material layer for the first oxidation storage electrode and the conductive material layer for the second charge storage electrode are formed on the drain region, and the conductive material layer for the first and second charge storage electrodes are connected to each other. The mask pattern process First
A charge storage electrode is formed over a part of the upper part of the dielectric film,
Accordingly, the charge storage electrode is electrically connected to the drain region through the contact hole having the dielectric film formed on the side wall, and the second dielectric film is formed on the charge storage electrode. The second plate electrode is formed on the upper part of the second plate electrode.

In order to achieve such an object, according to another feature of the present invention, a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on them. In the method of manufacturing a semiconductor memory device having a MOSFET and a two-layer laminated capacitor structure configured to be electrically connected to the drain region of the MOSFET, the step of forming the two-layer laminated capacitor includes: Forming a first charge storage electrode on the insulating oxide film and the exposed drain region by removing a part of the insulating oxide film by a patterning process; and forming a first charge storage electrode on the first charge storage electrode. Forming a dielectric film,
Forming a plate electrode on the top of the gate electrode, forming a second dielectric film on the plate electrode, and forming a conductive material layer for a second charge storage electrode on the top of the second dielectric film; A part of the conductive material layer for the second charge storage electrode, the second dielectric film, the plate electrode and the first dielectric film formed on the upper part of the substrate is sequentially etched by a contact pattern process to form a contact hole. Forming a second dielectric film and a conductive material for spacers on the entire surface, and forming a conductive material spacer on the wall surface of the contact hole by anisotropically etching the conductive material for spacers; After removing the exposed third dielectric film on the top of the conductive material layer for the second charge storage electrode and the bottom of the contact hole, the conductive layer for the third charge storage electrode is exposed on the entire exposed surface. Of the conductive material layers for the second and third charge storage electrodes, which are connected to each other, to form a second charge storage electrode by a mask patterning process. Is electrically connected to the drain region through a dielectric film.

In order to achieve such an object, another feature of the present invention is to provide a MOSFET in which a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed thereon. In the method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure configured to be electrically connected to the drain region of the MOSFET, the step of forming the two-layer laminated capacitor includes: insulating the upper portion of the drain region. Forming an oxide film for the upper part and a first charge storage electrode on the exposed drain region; and forming a first dielectric film on the first charge storage electrode,
Forming a plate electrode on the upper part of the gate electrode line and sequentially etching a part of the plate electrode and the first dielectric film on the gate electrode line by a contact mask pattern process to form a contact hole. Forming a second dielectric film on the plate electrode and the contact and forming a conductive material layer for the second charge storage electrode on the exposed whole surface; and the second charge storage electrode. After forming a nitride film on the conductive material layer for the electrode, only the nitride film on the conductive material layer for the etch-back electrode is removed to remove the remaining nitride film, and the exposed second charge storage electrode is used. Forming a thermal oxide film on the conductive material layer of the above, and using the thermal oxide film as a mask layer to etch the nitride film remaining in the contact hole to expose the contact layer. Etching the conductive material layer for the second charge storage electrode on the bottom of the contact hole, and then removing the thermal oxide film and the second dielectric film exposed on the bottom of the contact hole; and A conductive material layer for the third charge storage electrode is formed on the formed entire surface, and the conductive material layers for the second and third charge storage electrodes are connected to each other by a mask pattern process to form the second charge storage electrode. And the second charge electrode is electrically connected to the drain region through the contact hole having the dielectric film formed on the side wall and the first charge storage electrode. Is characterized by.

In order to achieve such an object, another feature of the present invention is that a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on the gate electrode and the gate electrode line. MOSF with a film formed
In a semiconductor memory device comprising an ET and a two-layer multilayer capacitor electrically connected to a lane region of the MOSFET, the second-layer multilayer capacitor includes a portion of an upper portion of the gate electrode and an upper portion of a gate electrode line. A first plate electrode formed on the insulating oxide film, a contact hole having a side wall and a lower part formed above the drain region via the first plate electrode, and an upper part of the first plate electrode. And a first dielectric film formed on a side wall of the contact hole, a first plate electrode having the first dielectric film formed thereon, and a contact hole having a first dielectric film formed on the side wall. A charge storage electrode formed on the drain region via the drain storage region, and electrically connected to the drain storage region through the drain storage region. Wherein the second dielectric film formed, from being constituted by a second plate electrode formed on top of the second dielectric film.

In order to achieve such an object, another feature of the present invention is that a gate electrode and a gate electrode line source and drain regions are formed on a silicon substrate, and an insulating oxide film is formed on the gate electrode and the gate electrode line. MOSF with a film formed
A semiconductor memory device comprising an ET and a two-layer laminated capacitor electrically connected to a drain region of the MOSFET, wherein the two-layer laminated capacitor is a part of an upper portion of the gate electrode and an upper portion of a gate electrode line. And a first charge storage electrode formed on the insulating oxide film and a part of an upper part of the drain region, and on the first charge storage electrode except for a lower part of a contact hole formed later on the gate electrode line. The formed first dielectric film, the upper part of the gate electrode and the upper part of the insulating oxide film of the upper part of the gate electrode line, and the plate electrode formed on the upper part of the first dielectric film, and the gate electrode A contact hole having a side surface side and a lower portion, and a second hole formed on the side wall of the upper portion of the plate electrode and the contact hole. A second charge storage electrode is formed on the dielectric film and on the first charge storage electrode exposed at the bottom of the contact hole and on the second dielectric film, thereby forming a side surface of the second charge storage electrode. It is characterized in that it is electrically connected to the drain region through the first charge storage electrode through a contact hole having a dielectric film formed on the wall.

〔Example〕

Hereinafter, it will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a charge storage electrode (14) formed by a conventional method.
FIG. 4A is a cross-sectional view showing a semiconductor memory device having a two-layer laminated capacitor structure in which A) is sandwiched by first and second plate electrodes (8A and 16). The structure will be briefly described. An element isolation oxide film (2) is formed on a part of an upper portion of a silicon substrate (1), and a gate oxide film (3), a gate electrode, and a gate electrode line (4 and 4 ') are formed. Further, by ion implantation, an insulating oxide film (7) is formed on all sides of the gate electrode (4) except a part of the upper part of the silicon substrate (6 ') region, and MOSF is formed.
Make up ET (25). Further, a two-layer laminated capacitor (30) electrically connected to the drain region (6 ') of the MOSFET (25) is formed. The two-layer laminated capacitor (30) has a first plate electrode (8) on the insulating oxide film (7).
A), capacitor dielectric film (9), charge storage electrode (14
A), the dielectric film (15) and the second plate electrode (16) are sequentially laminated. Oxide film spacer (17) on the side wall at a certain part of the plate electrode (8A)
A contact hole (31) in which is formed and the charge storage electrode (14A) on the upper side is connected to the drain region (6 ') of the MOSFT (25) through the contact hole (31). There is.

However, the conventional structure as described above has the drawbacks mentioned at the beginning. Therefore, the present invention provides a method for forming a semiconductor memory device having a two-layer laminated capacitor structure in which a dielectric film is formed around the wall surface of the contact hole to increase the effective area of the capacitor. 2A to 2G will be described as a reference.

In FIG. 2A, an element isolation oxide film (2) is formed on a part of a silicon substrate (1), and a gate oxide film (3), a gate electrode and a gate electrode line ( 4 and 4 ') to form the gate electrode (4)
After forming source and drain regions (6 and 6 ') in the silicon substrate (1) on both sides of the gate electrode by ion implantation, oxide film spacers are formed on both sides of the gate electrode and gate electrode lines (4 and 4'). It is a sectional view of the state where (5) was formed.

FIG. 2B shows that the insulating oxide film (7) is deposited to a constant thickness on the entire exposed area to insulate the gate electrode (4) from the first plate electrode (8A) which is to be deposited or formed later.
It is a sectional view of the state where SFET (25) was constituted.

In FIG. 2C, a conductive material layer (8) for a plate electrode is deposited on the insulating oxide film (7), and a part of the gate electrode (4) is formed on the drain region (6 ') in a patterning process. Forming a first dielectric film (9) on the first plate electrode (8A) on the insulating oxide film (7) up to the gate electrode line (4 ') via A conductive material layer (10) for one charge storage electrode is sequentially deposited. Further, a photosensitive layer (11) is formed on the conductive material layer (10) for the first charge storage electrode to interconnect the conductive material layer (10) for the first charge storage electrode and the drain region (6 '). After coating, the contact mask (32) is formed by removing a certain portion of the photosensitive film (11) above the drain region (6 ').

FIG. 2D shows the conductive material layer (10) for the first charge storage electrode, the first dielectric film (9), the first plate electrode (8A) and the oxide film in the portion where the photosensitive film (11) is removed. (7) are sequentially etched to form a contact hole (31), the photosensitive film (11) is completely removed, and then the conductive material layer (10) for the first charge storage electrode and the contact hole are formed. (31)
The second dielectric film (12) on the conductive material layer (1) for the spacer.
FIG. 3 is a sectional view showing a state in which 3 ′) are sequentially deposited. Here, the conductive material layer for spacers (13 ') is formed in the contact hole (3) of the first plate electrode (8A) in the contact portion.
It is deposited to protect the second dielectric film (12) formed on the wall surface (31A) of 1).

FIG. 2E shows that the conductive material layer (13 ') for the spacer is anisotropically etched to form the conductive material spacer (13) around the wall surface of the contact hole (31), and then the first charge is formed. Upper part of conductive material layer (10) for storage electrode and drain region (6 ')
FIG. 6 is a cross-sectional view showing a state where the exposed second dielectric film (12) is etched.

FIG. 2F shows the exposed conductive material layer (10) for the charge storage electrode and the contact hole (31) for connecting the conductive material layer (10) for the first charge storage electrode and the drain region (6 ′). FIG. 9 is a cross-sectional view showing a state in which a conductive material layer (14) for the second charge storage electrode is further deposited on the lower portion (31B) of FIG.

FIG. 2G shows that after the third dielectric film (15) is formed on the first and second charge storage electrodes (14A), the second plane electrode () is formed on the third dielectric film (15). 16) to form 2
FIG. 3 is a cross-sectional view of a state in which a layer laminated capacitor (40) is formed.

In the above-described embodiment of the present invention, the dielectric film (12) is formed on the side wall (31A) of the contact hole (31), and the dielectric film (1) is formed.
2) To protect the contact hole (31) side wall (31)
After forming the conductive material spacer (13) on the structure (A), the charge storage electrode (14A) is formed on the above structure and the charge storage electrode of the two-layer laminated capacitor (40) through the contact hole (31). This is a method of connecting (14A) to the drain region (6 ') of the MOSFET (25).

FIGS. 3A to 3G below show a method of forming a dielectric film around the wall surface of a contact hole according to another embodiment of the present invention, and as a result, the structure is substantially the same as that shown in FIG. 2G. However, each manufacturing method is different.

FIG. 3A is a sectional view showing a state in which the conductive material (8) for the first plate is deposited with a constant thickness over the entire exposed area after the manufacturing process of the MOSFET (25) of FIG. 2B.

FIG. 3B is a part of the upper part of the gate electrode (4) by the patterning process, and the first plate electrode (8A) is formed on the insulating oxide film above the gate electrode line (4 ') through the upper part of the drain region (6'). ) Is formed, and the charge storage electrode (14A) is formed later.
In order to connect the drain region (6 ') to the drain region (6'), a contact hole (31) is formed except for a portion of the first plate electrode (8A) and the insulating oxide film (7) above the drain region (6 '). FIG. 6 is a cross-sectional view showing a state in which a first dielectric film (9) is formed on the exposed first plate electrode (8A) and drain region (6 ′).

FIG. 3C shows that the conductive material layer (10) for the first charge storage electrode is deposited on the dielectric film (9) and a part of the insulating oxide film (7), and the nitride film is formed on the conductive material layer (10). Deposit (18).
Furthermore, since the nitride film (18) is left only inside the contact hole (31), the photosensitive film (19) (or Polyimide or SOG) is used.
It shows a state in which is applied.

FIG. 3D shows the first charge in the contact hole (31) after the etching back process is performed so that the etching selectivity of the photosensitive film (19) (or Polyimide or SOG) and the nitride film (18) are the same. A state in which the nitride film (18) is left only on the conductive material layer (10) for the storage electrode and then grown on the conductive material layer (10) for the first charge storage electrode exposed in the above process. FIG.

FIG. 3E was exposed in the above process after etching only the nitride film (18) under the contact hole (31) (31B) using the thermal oxide film (20) formed above as a mask. After the contact hole (10) is etched, the thermal oxide film (20) and the contact hole are formed by using the conductive material layer (10) for the first charge storage electrode and the drain region (6 ') as an etching stop point. It is a sectional view of the state where the exposed 1st dielectric film (9) of the lower part (31B) of (31) was etched.

FIG. 3F shows a mask pattern process after depositing a conductive material layer (10) for the first charge storage electrode and a conductive material layer (14) for the second charge storage electrode on the drain region (6 '). FIG. 6 is a cross-sectional view showing a state in which a charge storage electrode (14A) is formed.

FIG. 3G shows that after forming a second dielectric film (15) on the charge storage electrode (14A) and contacting it with the first dielectric film (9), the first and second dielectric films of the respective first and second dielectric films are formed. Membrane (9 and 15)
FIG. 6 is a cross-sectional view of a state in which a two-layer laminated capacitor (40) having a second plate electrode (16) formed thereon is formed.

In the above embodiment of the present invention, since the dielectric film (9) is formed around the side wall (31A) of the contact hole (31), the photosensitive film (19) and the nitride film are formed as described in FIGS. 3D and 3E. By applying an etch back process in which the nitride film (18) is left only in the lower portion (31B) of the contact hole (31) after making the etching selection ratio of (18) the same, the wall surface of the contact hole (31) ( 31A) is a process method of forming a dielectric film (9).

FIG. 4 shows that the cell plate electrode (60) manufactured by the conventional method has first and second charge storage electrodes (58 and 66A).
FIG. 9 is a cross-sectional view of one example of a semiconductor memory device having a two-layer laminated capacitor structure (80) according to the present invention. The structure will be briefly described. An element isolation oxide film (52) is formed on a part of an upper portion of a silicon substrate (51), a gate oxide film (53), and a gate electrode and a gate electrode line (54 and 5) are provided at a position separated from the gate oxide film (53).
4 ') is formed. In addition, the gate electrode (5
4) Source and drain regions (56 and 56 ') are formed in the silicon substrate (51) on both sides, and an insulating oxide film (57) is formed over the entire drain (56') region except a part thereof. Then, a MOSFEF (75) is formed to form a two-layer laminated capacitor (80) electrically connected to the drain region (56 ') of the MOSFET (75). The above two-layer laminated capacitor (8
0) is a first charge storage electrode (58) connected to the drain region (56 '), a first dielectric film (59), a plate electrode (6)
0), the second dielectric film (61) and the second charge storage electrode (66
A), a contact hole (71) having a side wall with an oxide film spacer (67) is formed at a certain portion of the plate electrode (60), and the second charge storage electrode (66A) is formed.
Is connected to the first charge storage electrode (58) through the contact hole (71). In the above structure, the oxide film spacer (67) is formed on the wall surface of the contact hole formed to interconnect the first and second charge storage electrodes (58, 66A), thereby limiting the increase of the capacitance of the capacitor. Will be done.

Therefore, in another embodiment of the present invention, the oxide film spacer (6) formed on the wall surface of the contact hole (71) in FIG.
By forming a dielectric film (64) instead of 7), the capacity of the capacitor is ultimately increased.
This will be described in detail with reference to FIGS. 5A to 5G.

In FIG. 5A, an element isolation oxide film (52) is formed on a part of the upper part of a silicon substrate (51), and the gate oxide film (53) and the gate electrode (54) both side surfaces are separated by a predetermined distance. After forming the source and drain regions (56 and 56 ') in the silicon substrate (51), the oxide film spacers (55) are formed on both sides of the gate electrode and the gate electrode lines (54 and 54'). FIG.

Figure 5B shows gate electrodes and gate electrode lines (54 and 5
An insulating oxide film (57) having a constant thickness is formed to insulate the charge storage electrode (58) formed later from 4 ').
Form a MOSFET (75). Further, after removing a part of the insulating oxide film (57) above the drain region (56 ') by a patterning process, the charge storage electrode (58) and the exposed drain region (56') are electrically connected. FIG. 6 is a cross-sectional view showing a state in which a first dielectric film (59) is formed on the first charge storage electrode (58) by connecting.

FIG. 5C shows that the plate electrode (60) is formed on the first dielectric film (59) and the second dielectric film (61) is formed on the plate electrode (60), and then the conductive material layer for the second charge storage electrode is formed. (62 ') first
The photosensitive material (63) is coated on the second charge storage electrode conductive material layer (62 ') to connect to the charge storage electrode (58), and then the first charge storage electrode on the gate electrode line (54'). (58) A sectional view of the state in which the contact mask (72) has been formed except for the photosensitive film (63) on the upper side.

FIG. 5D shows the conductive material layer (62 ′) for the charge storage electrode, the second dielectric film (61), in a portion where the photosensitive film (63) is removed.
The plate electrode (60) and the first dielectric film (59) are sequentially etched to form a contact hole (71), the photosensitive film (63) is completely removed, and the contact hole (7) is formed.
1) A third dielectric film (64) is formed on the conductive material layer (62 ') for the second charge storage electrode and the contact hole (71) to form a dielectric film on the side wall, and the third dielectric film is formed. Spacer conductive material (65 ') on top and side of body membrane (64)
It is sectional drawing of the state which deposited.

In FIG. 5E, the spacer conductive material (65 ') is anisotropically etched to form the wall (71) of the contact hole (71).
Forming a conductive material spacer (65) on A),
The third dielectric film (64) formed on the wall surface of the contact hole (71) is protected. Further, the third dielectric film (64) above the conductive material layer (62 ') for the second charge storage electrode and the third dielectric below the contact hole (71) (71B) exposed by the above process. Excludes the membrane (64).

In FIG. 5F, in order to connect the conductive material layer (62 ') for the second charge storage electrode and the first charge storage electrode (58),
A conductive material layer 66 for the third charge storage electrode is deposited on the entire exposed area.

FIG. 5G illustrates a two-layer laminated capacitor (80) formed by forming a second charge storage electrode (66A) by a mask pattern process on the conductive material layers (62 ′ and 66) for the second and third charge storage electrodes. It is sectional drawing of the state formed. As can be seen from the above, the first and second charge storage electrodes (58 and 66)
A) has a structure in which the plate electrode (60) is sandwiched around, but the side surface (71) of the contact hole (71) is interconnected through the contact hole (71).
It can be seen that a dielectric film (64) is formed in A).

On the other hand, FIGS. 6A to 6G are still another embodiment of the present invention, and the steps up to FIG. 6A are the same as the steps of FIGS. 5A and 5B described above. Describe the process.

FIG. 6A is a sectional view showing a state in which a conductive material layer (60 ') for a plate electrode is deposited on the first dielectric film (59) in the next step of FIG. 5B.

In FIG. 6B, the conductive material layer (6
Plate electrode (6
0) is formed, and the second charge storage electrode (6) formed in the next step is formed.
In order to connect 2) to the first charge storage electrode (58), the plate electrode (60) above the gate electrode line (54 ') and a certain portion of the first dielectric film (59) are sequentially etched and contacted. FIG. 9 is a cross-sectional view showing a state in which a hole (71) is formed and a second dielectric film (61) is formed in the plate electrode (60) and the contact hole (71).

FIG. 6C shows a conductive film (62 ') for the second charge storage electrode, a nitride film (68), and a photosensitive film for performing an etch back process on the second dielectric film (61). (69)
(Or Polyimide, or SOG) is a cross-sectional view of a state of being sequentially formed.

In FIG. 6D, the above-mentioned photosensitive film (69) (or Polyimid
e, or SOG) and the nitride film (68) are subjected to an etch back step with an equal etching selection ratio to form a conductive material layer (6) for the second charge storage electrode in the contact hole (71).
2 ') The nitride film (68) is left only on the upper part and the other portions of the nitride film (68) are removed.

After that, a thermal oxide film (70) is grown on the conductive material layer (62 ') for the second charge storage electrode, which is exposed in the above process. Here, when the thermal oxide film (70) is grown, the nitride film (68) under the contact hole (71) is used as a barrier layer so that the oxide film does not grow under the contact hole.

6E shows a nitride film 68 along the width of the contact hole 71 in FIG. 6D and a conductive material layer 6 for the second charge storage electrode.
2 ′) are sequentially removed, and then the entire thermal oxide film (70) and the second dielectric film (61) under the contact hole (71) are removed.
FIG. 4 is a cross-sectional view showing a state in which a part of FIG. Here, the thermal oxide film (70) is used as an etching barrier layer when etching the nitride film (68) and the conductive material layer (62 ') for the second charge storage electrode.
When the thermal oxide film (70) and the second dielectric film (61) are etched, the conductive material layer (62 ') for the second charge storage electrode and the first charge storage electrode (58) are stopped. Used for area.

FIG. 6F shows the conductive material layer (6) for the second charge storage electrode exposed for connecting to the first charge storage electrode (58).
2 ') and a contact hole (71) inside a conductive material layer (66) for the third charge storage electrode is a cross-sectional view of a state.

FIG. 6G shows that the conductive material layers (62 ′ and 66) for the second and third charge storage electrodes are used as the second charge storage electrode (66A) in the mask pattern process, and are used as the first charge storage electrode (58).
FIG. 6 is a cross-sectional view of a state in which the two-layer laminated capacitor (80) is completed after being connected to the.

Here, it should be noted that although the structures of the two-layer laminated capacitors completed in the third and fourth embodiments of the present invention are the same, the first and second charge storage electrodes (58 and 66).
There is a difference in the method for forming the dielectric film also on the side wall of the contact hole when A) is interconnected via the plate electrode (60).

Further, although the description is omitted in the present specification,
After forming insulating layers on each other after the process of FIGS. 5G and 6G, a bit line is connected to the source region (6) to form a protective layer, and a DRAM (Dynamic Random Access Mem) is formed.
It becomes possible to form a semiconductor memory device having a mory structure.

〔The invention's effect〕

As can be seen from the various embodiments of the present invention described above, when forming a two-layer laminated capacitor structure, a predetermined number of electrodes are placed in the middle and the upper and lower electrodes are interconnected to form sidewalls of contact holes. Forming a thin dielectric film instead of a spacer also has a remarkable effect of increasing the capacitance of a capacitor in a cell structure having the same area.

[Brief description of drawings]

FIG. 1 is an embodiment of a sectional view of a semiconductor memory device having a two-layer laminated capacitor structure manufactured by a conventional method. 2A to 2G are sectional views showing a process of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure according to the present invention. 3A to 3G are cross-sectional views showing a process of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure according to one embodiment of the present invention. FIG. 4 is an embodiment diagram of a semiconductor memory device having a two-layer laminated capacitor structure manufactured by a conventional method. 5A to 5G are sectional views showing a process of manufacturing a semiconductor memory device having a two-layer capacitor structure according to another embodiment of the present invention. FIGS. 6A to 6G show a second embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor memory device having the layer-multilayer capacitor. 1, 51: Silicon substrate, 2, 52: Element isolation oxide film 3, 53: Gate oxide film 4, 4 ′: Gate electrode and gate electrode line 5, 55: Oxide film spacer 6, 6 ′: Source and drain region 7 , 20, 57, 70: oxide films 8A, 16: first and second plate electrodes 9, 12, 15: first, second and third dielectric films 14A: charge storage electrode, 13, 65: conductive material spacer 11, 19, 63, 69: Photosensitive film, 18, 68: Nitride film 54, 54 ': Gate electrode and gate electrode line 56, 56': Source and drain region 58: Primary charge storage electrode 62, 66A: Secondary Charge storage electrode 59, 61, 64: first, second and third dielectric film 60: plate electrode

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/04

Claims (9)

[Claims] 1. A MOSFET in which a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on these regions, and the MOSFET.
2 configured to be electrically connected to the drain region of
In the method of manufacturing a semiconductor memory device having a multilayer capacitor structure of two layers, the step of forming the two-layer multilayer capacitor includes: insulating oxidation of a gate electrode line upper part through a part of an upper part of the gate electrode and a drain region upper part. Forming a first plate electrode on the film, forming a first dielectric film on a portion of the first plate electrode, and then forming a conductive material layer for the first charge storage electrode on the entire surface. And forming a contact hole in a part of the conductive material layer for the first charge storage electrode, the first dielectric film, the first plate electrode and the insulating oxide film, which is formed on the drain region. Forming a conductive material for the second dielectric film and the spacer on the entire surface, and forming a conductive material spacer on the wall surface of the contact hole by anisotropically etching the conductive material for the spacer. And removing the conductive material layer for the first charge storage electrode, the exposed second dielectric film on the conductive material spacer and the drain region, and then depositing the second charge storage layer on the entire exposed surface. A conductive material layer for an electrode is formed, and a charge storage electrode is formed from the conductive material layers for the first and second charge storage electrodes, which are connected to each other, by a mask pattern process. Electrically connecting to the drain region through a contact hole having a dielectric film formed on a wall; forming a third dielectric film on the charge storage electrode; and forming a second plate electrode on the third dielectric film. Characterized by forming,
A method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure. 2. The step of forming the contact hole includes the steps of applying a photoresist film on the conductive material layer for the first charge storage electrode and removing a portion of the photoresist film formed on the drain region. Forming a contact mask by using a conductive material for the first charge storage electrode, a first dielectric film, and
2. The semiconductor memory device having a two-layer laminated capacitor structure according to claim 1, further comprising a step of sequentially removing the first plate electrode and the oxide film, and a step of removing all of the remaining photoresist film. Manufacturing method. 3. A MOSFET in which a gate electrode, a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on these regions, and the MOSFET.
2 configured to be electrically connected to the drain region of
In the method of manufacturing a semiconductor memory device having a layer-stacked capacitor structure, the step of forming the two-layer stacked capacitor includes forming a second layer on the insulating oxide film above the gate electrode line through an upper portion of a drain region above the gate electrode. Forming one plate electrode; forming a contact hole by sequentially etching a part of the first plate electrode and the insulating oxide film formed on the gate region by a contact mask pattern process; Forming a first dielectric film on the first plate electrode and a contact hole and forming a conductive material layer for the first charge storage electrode on the exposed whole surface; and the first charge storage electrode. Forming a nitride layer on the conductive material layer for the first charge storage electrode, and forming the nitride layer on the conductive material layer for the first charge storage electrode inside the contact hole. Etching back the nitride film from above so that it is left only in the region; growing a thermal oxide film on the conductive material layer for the first charge storage electrode exposed by the etching back; The oxide film is used as a mask layer to etch the nitride film remaining in the contact hole to etch the conductive material layer for the first charge storage electrode on the lower portion of the exposed contact hole, and Removing the thermal oxide film and the first dielectric film exposed under the contact hole; and a conductive material layer for the first charge storage electrode and a conductive material layer for the second charge storage electrode on the drain region. Forming a charge storage electrode by applying the conductive material layers for the first and second charge storage electrodes, which are connected to each other, to a part of an upper portion of the first dielectric film by a mask patterning process, Therefore, electrically connecting the charge storage electrode to the drain region through a contact hole having a dielectric film formed on a side wall, and forming a second dielectric film on the charge storage electrode. A method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure, wherein a second plate electrode is formed on an upper portion. 4. Forming a nitride film on the conductive material layer for the first charge storage electrode, and forming the nitride film on the conductive material layer for the first charge storage electrode inside the contact hole. The step of etching back the nitride layer from above to leave only the nitride layer and the photoresist layer on the conductive material layer for the first charge storage electrode is sequentially performed, and then the photoresist layer and the nitride layer are sequentially coated. 4. The method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure according to claim 3, wherein the etch back step is performed with the same etching selection ratio. 5. A MOSFET in which a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on these, and the MOSF.
In a method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure configured to be electrically connected to a drain region of ET, the step of forming the two-layer laminated capacitor includes the insulating oxide film in the drain region. Forming a first charge storage electrode on the insulating oxide film and the exposed drain region, and patterning a part of the first charge storage electrode; and forming a first dielectric on the first charge storage electrode. Forming a film,
Forming a plate electrode on the plate electrode, and forming a second dielectric film on the plate electrode,
A conductive material layer for the second charge storage electrode is formed on top of it,
The conductive material layer for the second charge storage electrode, the second dielectric film, and a portion of the first dielectric film formed on the gate electrode line are sequentially etched by a contact pattern process to form a contact hole. Forming a third dielectric film and a conductive material for spacers on the entire surface, and forming a conductive material spacer on the wall surface of the contact hole by anisotropically etching the conductive material for spacers; The conductive material layer for the third charge storage electrode is formed on the entire exposed surface after removing the exposed third dielectric film on the top of the conductive material layer for the second charge storage electrode and the bottom of the contact hole. And forming an upper charge storage electrode by a mask pattern process from the conductive material layers for the second and third charge storage electrodes connected to each other, thereby forming the upper charge storage electrode. An electrode on the side surface wall via a dielectric film characterized by being adapted to electrically connect to the drain region, a method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure. 6. The step of forming the contact hole comprises applying a photoresist film on the conductive material layer for the second charge storage electrode, and forming a predetermined portion of the photoresist film on the gate electrode line. Forming a contact mask except for the conductive film, the conductive material layer for the second charge storage electrode, the second dielectric film, the plate electrode and the first dielectric film along the contact mask from which the photosensitive film is partially removed. 6. The method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure according to claim 5, further comprising the steps of sequentially removing a part of the above, and removing all of the remaining photosensitive film. 7. A MOSFET in which a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on these, and the MOSF.
In a method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure configured to be electrically connected to a drain region of an ET, the step of forming the two-layer laminated capacitor includes the insulating oxidation of the drain region. Forming a first charge storage electrode on the film and the exposed drain region; and forming a first dielectric film on the first charge storage electrode,
Forming a plate electrode on the gate electrode line, and forming a contact hole by sequentially etching a part of the plate electrode and the first dielectric film formed on the gate electrode line by a contact mask pattern process. A second dielectric film is formed on the plate electrode and inside the contact hole, and a second dielectric film is formed on the exposed whole surface.
Forming a conductive material layer for the charge storage electrode, and forming a nitride layer on the conductive material layer for the second charge storage electrode, and then nitriding the conductive material layer for the second charge storage electrode. Forming a thermal oxide film on the exposed conductive material layer for the second charge storage electrode except the remaining nitride film, and using the thermal oxide film as a mask layer. The nitride film remaining in the contact hole is etched to etch the conductive material layer for the second charge storage electrode on the exposed lower portion of the contact hole, and then the thermal oxide film and the contact hole are removed. Removing the second dielectric layer exposed at the bottom, and forming a conductive material layer for a third charge storage electrode on the exposed entire surface, and connecting the second and third layers to each other.
An upper charge storage electrode is formed from a conductive material layer for the charge storage electrode by a mask pattern process, so that the first charge storage electrode is formed through a contact hole having a dielectric film formed on a side wall of the upper charge storage electrode. And a method of manufacturing a semiconductor memory device having a two-layer laminated capacitor structure, which is electrically connected to the drain region. 8. The step of leaving only the nitride film on the conductive material layer for the second charge storage electrode includes sequentially depositing a nitride film and a photosensitive film on the conductive material layer for the second charge storage electrode. 8. The method according to claim 7, further comprising performing an etch back process after applying the same to the photosensitive film and the nitride film with the same etching selection ratio.
A method of manufacturing a semiconductor memory device having a layer-multilayer capacitor structure. 9. A MOSFET in which a gate electrode and a gate electrode line, a source and a drain region are formed on a silicon substrate, and an insulating oxide film is formed on the gate electrode and the gate electrode line, and a drain of the MOSFET. In a semiconductor memory device including a two-layer laminated capacitor electrically connected to a region, the two-layer laminated capacitor includes a part of an upper portion of the gate electrode and an insulating oxide film and a drain on an upper portion of a gate electrode line. A first charge storage electrode formed on a part of an upper portion of the region; and a first dielectric formed on the first charge storage electrode except for a lower portion of a contact hole formed later on the gate electrode line. A film, a plate electrode formed on the insulating film above the gate electrode and a part of the gate electrode line and on the first dielectric film, and the gate electrode. A contact hole formed on the side of the plate electrode above the electrode line and having a side wall and a lower side; a second dielectric film formed on the side wall of the plate electrode above and the contact hole; A second charge storage electrode is formed on an upper part of the first charge storage electrode and an upper part of the second dielectric film exposed to a lower part of the second charge storage electrode, thereby forming a dielectric film on the side wall of the second charge storage electrode. A semiconductor memory device having a two-layer laminated capacitor structure, characterized in that it is electrically connected to the drain region through the first charge storage electrode through the contact hole.