JPH036857A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To suppress the difference in level between a memory cell part and a peripheral circuit part and facilitate formation and processing of a wiring by a method wherein a transistor has a channel region formed on the side surface of a trench which is formed in a semiconductor main surface along its thickness direction and source/drain regions formed on the semiconductor main surface and on the bottom of the trench and at least a part of a capacitor is formed in the trench. CONSTITUTION:As the switching transistor and stacking type capacitor of a memory cell are formed in a trench 103', the difference in level between the memory cell part and a peripheral circuit part can be suppressed. Owing to the suppression of the difference in level, the poor step coverage of, for instance, a silicide film which is used as a wiring 115 on the stepped part can be avoided. Therefore, formation and processing of the wiring 115 are facilitated.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a stacked memory consisting of one transistor and one capacitor. The present invention relates to a semiconductor device in which a memory cell section composed of cells and a peripheral circuit section are H, and a method for manufacturing the same.

- (Prior Art) Conventionally, there is a DRAM, for example, as a semiconductor device having a memory cell section and a peripheral circuit section. With the miniaturization of the memory cell part of this DRAM, as a way to further increase the storage capacity with a fixed plane area, a stack type structure in which a charge storage electrode/drain region is stacked on top of the switching transistor of the memory cell has been developed. There are memory cells.

This stacked memory cell will be explained below with reference to the drawings.

FIG. 6 is a cross-sectional view of a DRAM having a memory cell section composed of conventional stacked memory cells and a peripheral circuit section.

As shown in FIG. 6, first, in the memory cell portion, a field oxide film 502 is selectively formed on the surface of a semiconductor substrate 501 as an element isolation region. Source/drain regions 503 having a conductivity type opposite to that of the semiconductor substrate 501 are formed in the element regions separated by the field oxide film 502 . A gate oxide film 504 is formed on this source/drain region 503 and a channel region existing between the source/drain region 503. On this gate oxide film 504, a gate (word line) 505 of a switching transistor is formed. An insulating film 509' is formed on the gate (word line) 505 of this switching transistor.

A charge storage electrode 506 is formed in contact with one of the source/drain regions 503. A dielectric @507 is formed on the charge storage electrode 506 as a dielectric of the capacitor. A counter electrode 508 is formed on this dielectric 8507. Furthermore, an interlayer insulating film 509 is formed, including over this counter electrode 508. A contact hole 510 is opened to the other source 7 and drain region 503 through this interlayer insulating film 509. A wiring (bit line) 511 connected to the other source/drain region 503 via this contact hole 510 is formed. on the other hand,
In the peripheral circuit section, a source/drain region 503' having a conductivity type opposite to that of the semiconductor substrate 501 is formed in an element region within the semiconductor substrate 501. This source/drain region 503' and the source/drain region 503'
A gate oxide H3O4= is formed on the channel region existing between. This gate oxide film 504
A gate 505' is formed on the gate 505'. On this game) 505, there is an insulating film 509 as an interlayer 8 film.
is formed. A contact hole 510' is opened through this interlayer insulating film 509 to the source/drain region 503-. This contact hole 510'
A wiring 511 is formed to be connected to the source/drain region 503' via the source/drain region 503'.

According to such a conventional DRAM having a memory cell section composed of stacked memory cells and a peripheral circuit section, an insulating film 509' is formed on the gate (word line) 505 of the switching transistor. , on which are a charge storage electrode 506, a dielectric H3O7, and a counter electrode 50.
8 to form a capacitor, it is possible to increase the storage capacity per unit area in the memory cell portion.

However, according to such a conventional DRAM having a memory cell section configured with stacked memory cells and a peripheral circuit section, first, in the memory cell section,
On top of the switching transistor, a storage electrode 506,
A dielectric film 507 and a counter electrode 508 are stacked. Therefore, the height of the substrate 501 in the thickness direction is
Roughly speaking, it is taller than a normal transistor structure because of the two electrodes and dielectric film. On the other hand, in the peripheral circuit section, nothing is stacked on top of the transistor (normal transistor structure). Therefore, the height of the substrate 501 in the thickness direction is thinner than the memory cell portion. Here, a difference in height, that is, a step difference, occurs between the memory cell section and the peripheral circuit section. In this way, when a difference in level occurs between the memory cell section and the peripheral circuit section, it becomes difficult to form and process the wiring 511. This problem is particularly noticeable in the memory cell section, the peripheral circuit section, and, for example, bit lines arranged between them.

(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and provides a semiconductor device having a memory cell section configured of stacked memory cells and a peripheral circuit section. A semiconductor device that can reduce the level difference between the memory cell section and the peripheral circuit section, and facilitate the formation and processing of wiring, especially the formation and processing of the wiring arranged between the two. The purpose is to provide a manufacturing method thereof.

[Structures of the Invention] (Means for Solving the Problems) According to a semiconductor device according to the present invention, in the semiconductor device having a memory cell consisting of one transistor and one capacitor, the transistor is arranged on the main surface of the semiconductor. On the other hand, the side of the groove formed in the thickness direction (4) has the semiconductor main surface and a source/drain region formed on the bottom surface of the groove inside the second groove, and the capacitor has: The capacitor is of a laminated structure type having a charge storage electrode/drain region, and is characterized in that at least a part of the capacitor is formed inside a groove formed in the thickness direction with respect to the semiconductor main surface.

The manufacturing method also includes a step of forming a first groove in the thickness direction with respect to the main surface of the semiconductor on the surface of the semiconductor substrate, and a step of filling the inside of the first groove with a first insulating film. , a part of this first insulating film is removed, and the main surface of the semiconductor is exposed again.
a step of forming a second groove in the thickness direction; The method is characterized by comprising a step of forming a transistor having a source/drain region, and a step of forming a capacitor having a charge storage electrode/drain region inside the second trench.

(Function) In the semiconductor device and its manufacturing method as described above, a switching transistor of a memory cell and a layered structure type Since the capacitor is formed, the height in the thickness direction of the substrate is reduced in the memory cell portion. Therefore, the level difference in the thickness direction of the substrate between the memory cell section and the peripheral circuit section is reduced.

(Example) Hereinafter, a semiconductor device and a manufacturing method thereof according to an example of the present invention will be described with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. 1(a) to 1(e) and FIGS. 2(a) to 2(e).

FIGS. 1(a) to 1(e) are plan views showing a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to 2(e) are FIGS. 1A and 1B are cross-sectional views taken along the line A-A' shown in FIGS. 1A to 1E in the order of manufacturing steps.

Further, in FIGS. 1(a) to 1(e) and FIGS. 2(a) to 2(e), the reference numerals correspond to each other.

First, as shown in FIGS. 1(a) and 2(a), for example, a p-type semiconductor substrate 1 shown in FIG.
A field oxide film 102 is selectively formed as an element isolation region on the surface of 01 by selective oxidation, for example, to a thickness of 4000 mm.
Approximately 5,000 people will be formed. On the surface of the p-type semiconductor substrate 101 on which the field oxide film 102 is formed, grooves 103 are formed in a lattice pattern, which are dug in the thickness direction of the substrate 101 with respect to the main surface of the semiconductor, for example, by photolithography using photoresist. It is formed with a width of about 0.7 to 1.0 μm. Next, a CVD oxide film 104 is formed over the entire surface by, for example, the CVD method.
, with a thickness of about 5,000 to 7,000 people. The CVD oxide film 104 is then etched back by, for example, RIE to fill the groove 103.

Next, as shown in FIG. 1(b) and FIG. 2(b), a switching transistor of a memory cell and a capacitor are formed in the CVD oxide film 104 embedded in the l71i 103. The CVD oxide film 104 located in the area is removed, for example, by photolithography using photoresist, and a new groove 103' is formed.

Next, as shown in FIG. 1(C) and FIG. 2(c), a gate oxide film 105 is formed in the groove 103' shown in FIG. 2(c) by, for example, a thermal oxidation method. do. Next, a polysilicon layer 106 that will become the gate (word line) of the switching transistor of the memory cell is formed over the entire surface by, for example, the CVD method. Next, this polysilicon layer 106 is patterned into a predetermined word line shape, for example, by photolithography using photoresist. next,
N-type impurities are ion-implanted into a predetermined source/drain formation region using, for example, an ion implantation method to form the source/drain.
A drain region 107 is formed. In FIG. 1(C) and FIG. 2(c), the bottom of the trench 103' and the element region separated by the field oxide film 102,
A source/drain region 107 is formed on the surface of the element region where the trench 103'' is not formed.

Therefore, the transistor formed here is
A channel region will be formed on the 3' side.

Next, as shown in FIG. 1(d) and FIG. 2(d), a CVD oxide film 108 for insulating the gate (word line) of the switching transistor of the memory cell is formed by, for example, the CVD method. is formed to a thickness of about 1000λ. Next, the CVD oxide film 108 deposited on the bottom surface of the trench 103'' and the gate oxide film 105 formed on the bottom surface of the trench 103'' are removed, and the source/drain region 105 is removed.
A contact portion 109' for 07 is formed.

Next, a polysilicon layer 109 that will become a charge storage electrode is formed on the entire surface by, for example, a CVD method to a thickness of about 500 to 2,000 layers, and in order to make this polysilicon layer 109 conductive, for example, an ion implantation method is used. Arsenic (A, s), which is an n-type impurity, is ion-implanted. and,
This polysilicon layer 109 and the source/drain region 1
07 is electrically connected. Next, the polysilicon layer 109 electrically connected to the source/drain region 107 is deposited with a predetermined amount of charge by, for example, photolithography using photoresist. Butter it into the shape of IS pole. Next, a dielectric film 1 that will become the dielectric of the capacitor is applied to the entire surface.
form 10. Next, a polysilicon layer 111 that will become a counter electrode is formed on the entire surface by, for example, the CVD method to a thickness of 100 mm.
Approximately 0 to 4,000 people will be formed. The polysilicon layer 111 existing on this source/drain region 107
Next, for example, by photolithography using photoresist, an opening 112 is formed in a region where a contact hole for a bit line is to be formed.

Next, as shown in FIGS. 1(e) and 2(e), a CVD oxide film 113, which will become the interlayer insulating film shown in FIG. 2(e), is formed on the entire surface by, for example, the CVD method. , thickness 2
Approximately 000 to 5000 people will be formed. Through this CVD oxide film 113, the source/drain region 107 is
A contact hole 114 is then opened. Next, a silicide film 1 that will become a wiring (bit line), for example, is deposited on the entire surface including the inside of this contact hole 114 by, for example, sputtering.
form 15. Next, this silicide film 115 is patterned into a predetermined wiring (bit line) shape, for example, by photolithography using photoresist. In this way, the memory cell portion of the semiconductor device according to the first embodiment of the present invention is formed. Further, in FIG. 2(e), transistors in the peripheral circuit section of the semiconductor device according to the first embodiment of the present invention are illustrated for comparison of their respective heights. Next, the transistors in this peripheral circuit section will be explained. In the p-type semiconductor substrate 101, a source/
A drain region 107'' is formed.
Drain region 107' and source/drain region 107
A CVD oxide film 113 is formed as an interlayer insulating film on the entire surface of the gate oxide film 105' on the channel region existing between the gate oxide film 105' and the gate oxide film 105'. Through this CVD oxide film 113, a contact hole 114'' is opened for the source/drain region 107''.
Wiring 11 made of, for example, a silicide film, connected to 07
5 is formed. It goes without saying that such a method for forming the transistors in the peripheral circuit section uses the above-described manufacturing process for the memory cell section, so that the transistors are formed in substantially the same steps as those for the memory cell section.

According to the memory cell portion of the semiconductor device according to the first embodiment of the present invention, the switching transistor of the memory cell and the stacked capacitor are formed in the trench 103'. part and 2nd
The level difference with the peripheral circuit section shown in FIG. 6(e) is reduced compared to the conventional example shown in FIG. Since the step difference is reduced in this way, the step coverage of the silicide film that becomes the wiring 115, for example, does not deteriorate in the step portion. Therefore, the formation and processing of the wiring 115 can be facilitated.

Particularly, processing is facilitated in, for example, bit lines disposed between the memory cell section and the peripheral circuit section. Moreover, the reliability of wiring is also improved.

Next, a second embodiment will be described with reference to FIGS. 3(a) to 3(e) and FIGS. 4(a) to 4(e).

3(a) to 3(e) are plan views showing a semiconductor device according to a second embodiment of the present invention in the order of manufacturing steps, and FIG. 4'(a) to 4(e) is shown in Figure 3(a).
FIG. 3 is a cross-sectional view taken along the line B-B- shown in FIGS. 3(e) and 3(e) in the order of manufacturing steps.

Further, in FIGS. 3(a) to 3(e) and FIGS. 4(a) to 4(e), reference numerals correspond to each other.

First, as shown in FIGS. 3(a) and 4(a), for example, a p-type semiconductor substrate 2 shown in FIG.
A first field oxide film 202 is selectively formed on the surface of 01 as an element isolation region by, for example, selective oxidation. Next, on the surface of the p-type semiconductor substrate 201 on which the first field oxide film has been formed, a groove 203 is dug in the thickness direction of the substrate 201 with respect to the main surface of the semiconductor by, for example, photolithography using photoresist. , formed in a grid pattern. Next, a second field oxide film 202' is selectively formed, for example, by selective oxidation, on the bottom surface of the trenches 203, which are dug in a grid pattern and run in the direction in which the bit lines are formed. .

Next, as shown in FIG. 3(b) and FIG. 4(b), a CVD oxide film 204 is formed over the entire surface by, for example, the CVD method.
form. Next, this CVDp conversion! 204 is etched back by, for example, the RIE method to embed it in the trenches 203 dug in a lattice pattern, as in the first embodiment.

Next, as shown in FIG. 3(C) and FIG. 4(c), the CVD oxide film buried in the groove 203 running in the direction in which the word line is formed, of the CVD oxide film 204. 204 is removed by, for example, photolithography using photoresist, and a new groove 203' is formed.

Next, as shown in FIGS. 3(d) and 4(d), a gate oxide film 205 is formed in the trench 203 by, for example, a thermal oxidation method. Here, FIG. 4(d) shows a gate oxide film 205 formed on the bottom surface of the trench 203' by thermal oxidation. Next, apply CV to the entire surface, for example.
A polysilicon layer 206, which will become the gate (word line) of the switching transistor of the memory cell, is formed by method D. Next, this polysilicon layer 206 is coated with, for example, RI.
The groove 20 is etched back using the E method.
Embed within 3″.

Next, as shown in FIG. 3(e) and FIG. 4(e), the polysilicon layer 20 is buried in the filler 203'.
6, the polysilicon layer 206 located in the region where the capacitor of the memory cell is to be formed is removed, for example, by photolithography using photoresist, and a new groove 206 is formed again.
03' is formed. Next, an n-type impurity is ion-implanted into a predetermined source/drain formation region by, for example, an ion implantation method to form a source/drain region 207. Thereafter, although not shown, a charge storage electrode connected to the source/drain region 207, a dielectric film, and a counter electrode are formed in the trench 203' by the same steps as in the first embodiment. Furthermore, a semiconductor device according to the second embodiment is manufactured by forming an interlayer insulating film, opening contact holes at predetermined locations of the device, and providing predetermined wiring.

In this way, in the first embodiment, the source/drain regions 107 formed at the bottom of the trench 103' are separated from each other by
The source/drain region 2 formed at the bottom of the groove 203 is
07 may be separated from each other by a field oxide film 202 selectively formed at the bottom of the trench 203.

According to the memory cell portion of the semiconductor device according to the second embodiment, as in the first embodiment, the memory cell portion and
In addition to reducing the level difference with the peripheral circuit section, since the word line is formed from the polysilicon layer 206 buried in the trench 203, there is no need for photolithography, that is, mask alignment, when forming the word line. disappears. Therefore, word lines can be formed in a self-aligned manner.

Next, a third embodiment will be described with reference to FIGS. 5(a) to 5(c).

FIGS. 5(a) to 5(c) are cross-sectional views showing a semiconductor device according to a third embodiment of the present invention in the order of manufacturing steps.

The initial manufacturing process of the semiconductor device according to the third embodiment is shown in FIG. 1(C) and FIG. 2(C) of the first embodiment.
The manufacturing process is the same as that described above. The following steps will be explained with reference to the drawings.

First, as shown in FIG. 5(a), a field oxide film is selectively formed as an element isolation region on the surface of a p-type semiconductor substrate 301 by selective oxidation, for example, by the manufacturing process described in the first embodiment. 302 is formed. Next, a p-type semiconductor substrate 30 on which this field oxide film 302 is formed
Grooves (not shown in the third embodiment) that are dug in the thickness direction of the substrate 301 on the main surface of the semiconductor are formed in the shape of a lattice on one surface, for example, by photolithography using photoresist. . Next, the entire surface is coated, for example, by CVD method.
CVD oxide film (not shown in the third embodiment)
form. Next, this CVD oxide film (not shown in the third embodiment) is removed by, for example, RIE method.
The grooves (not shown in the third embodiment) are filled by etching back. Next, this groove (
Of the CVD oxide film (not shown in the third embodiment) embedded in the CVD oxide film (not shown in the third embodiment), the region where the switching transistor of the memory cell and the capacitor are formed is The CVD oxide film (not shown in the third embodiment) is removed, for example, by photolithography using photoresist, and new grooves 303' are formed.
form. Next, a gate oxide film 305 is formed in this groove 303' by, for example, a thermal oxidation method. Next, a polysilicon layer 306 that will become the gate (word line) of the switching transistor of the memory cell is formed over the entire surface by, for example, the CVD method. Next, this polysilicon layer 306
are patterned into a predetermined word line shape, for example, by photolithography using photoresist. Next, an n-type impurity is ion-implanted into a predetermined source/drain formation region by, for example, an ion implantation method to form a source/drain region 307. Next, for example, by CVD method, a CVD oxide film 30 is formed to insulate the gate (word line) 306 of the switching transistor of the memory cell.
form 8. Next, C deposited inside the groove 303'
The VD oxide film 308 and the gate oxide film 305 formed on the bottom surface of the pad 303' are selectively etched, for example, by photolithography using photoresist. After this, by continuing etching, II.
303-A new groove 303' is formed again in the p-type semiconductor substrate 301 located at the bottom.

Next, as shown in FIG. 5(b), for example, CV
By method D, a polysilicon layer 309 that becomes a charge storage electrode is formed.
form. Next, in order to make this polysilicon layer 309 conductive, arsenic (As), which is an n-type impurity, is ion-implanted by, for example, an ion implantation method. At this time, by diffusing arsenic, which is an n-type impurity ion-implanted into the polysilicon layer 309, into the p-type semiconductor substrate 301, source/drain regions are formed on the side and bottom surfaces of the trench 303''. 307' is formed and integrated with the source/drain region 307. Next, the polysilicon layer 309 electrically connected to the source/drain regions 107 and 107' is photographed using, for example, photoresist. It is patterned into a predetermined shape of a charge storage electrode by an etching method. Next, a dielectric film 310 that will become the dielectric of the capacitor is formed on the entire surface. Next, for example, C
A polysilicon layer 311 that will become a counter electrode is formed by a VD method. Next, in the polysilicon layer 311 existing on the source/drain region 307, for example, by photolithography using photoresist, an opening 312 is formed in a region where a contact hole for a bit line is to be opened. Drill a hole.

Next, as shown in FIG. 5(C), for example, CV
A CVD oxide film 313, which will become an interlayer insulating film, is formed by method D. Next, a contact hole 31 is inserted into the source/drain region 307 through this CVD oxide film 313.
4. Drill a hole.

Next, a silicide film 315 that will become a wiring (bit line), for example, is formed on the entire surface, including inside the contact hole 314, by, for example, sputtering. Next, this silicide film 315 is formed into a predetermined pattern by photolithography using, for example, photoresist. J! (bit line) pattern. In this way, the memory cell portion of the semiconductor device according to the third embodiment of the present invention is formed.

According to the memory cell portion of the semiconductor device according to the third embodiment, as in the first embodiment, the memory cell portion and
In addition to reducing the level difference with the peripheral circuit section,? A groove 303' is further formed in R303-, and a capacitor is formed by spanning both grooves, so compared to the first embodiment,
The storage capacity per unit area can be increased.

Also, charge storage 8! Since the contact area between electrode 309 and source/drain regions 307 and 307' is increased, contact resistance can be reduced.

In addition, in this third embodiment, the source/source formed at the bottom of R303-, the side surface and bottom of 303'
Of course, the drain regions 307 and 307' may be separated from each other by a field oxide film selectively formed in the trench, as described in the second embodiment.

[Effects of the Invention] As explained above, according to the present invention, in a semiconductor device having a memory cell section configured of stacked memory cells and a peripheral circuit section, the memory cell section and the peripheral circuit section are connected to each other. It is possible to reduce the level difference in the thickness direction of the board between the
Provided are a semiconductor device and a method for manufacturing the same that can facilitate the formation and processing of wiring, particularly the formation and processing of wiring disposed between the two.

[Brief explanation of the drawing]

1(a) to 1(e) are plan views showing a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps;
FIGS. 2(a) to 2(e) are cross-sectional views shown in the order of manufacturing steps along the line A-A- shown in FIGS. 1(a) to 1(e), and FIG. 3(a) to 3(e) are plan views showing the semiconductor device according to the second embodiment of the present invention in the order of manufacturing steps, and FIG. ) to 3(e) are cross-sectional views shown in the order of manufacturing steps along the line B-B', and FIGS. 5(a, ) to 5(C) are the third embodiment of the present invention. FIG. 6 is a sectional view showing a semiconductor device according to the prior art in the order of manufacturing steps. 101...p-type semiconductor substrate, 102...field oxide film, 1.03, 103-...groove, 104...C
VD oxide film, 105, 105"...gate oxide film, 1
06...Polysilicon layer (word line) 106----
Gate, 107, 107-- Source/drain region, 108... CVD oxide film, 109... Polysilicon layer (charge storage electrode) 110... Dielectric film, 11
DESCRIPTION OF SYMBOLS 1... Polysilicon layer (counter electrode), 112... Opening part, 113... CVD oxide oxide interlayer insulating film), 114
．． 114--Contact hole, 115--Silicide film (wiring) 201--P type semiconductor substrate, 202.2
02-...Field oxide film, 203°203'...
- Groove, 204...CVD oxide film, 205...gate oxide film, 206...polysilicon layer (word line), 20
7... Source/drain region, 301... P-type semiconductor substrate, 302... Field oxide film, 303', 3
03'... Groove, 305... Gate oxide film, 306...
・Polysilicon layer (word m), 307307 ・・
・Source/drain region, 308-CVD oxide film, 30
9... Polysilicon layer (charge storage electrode), 310...
・Dielectric film, 311...polysilicon layer (counter electrode)
, 312... Opening part, 313... CVD oxide film (interlayer insulating film), 314... Contact hole, 315... Silicide film (wiring), 501... P-type semiconductor substrate, 50
2...Field oxide film, 503.503-source/
Drain region, 504504゛...gate oxide film, 50
5...Word line (ge-h), 505-...gate, 5
06... Charge storage electrode, 507... Dielectric film, 50
8... Counter electrode, 509.509-... CVD oxide film (interlayer insulating film), 510.510-... Contact hole, 5] 1... Wiring.

Claims (4)

[Claims] (1) In a semiconductor device having a memory cell consisting of one transistor and one capacitor, the transistor has a channel region formed on a side surface of a groove formed in the thickness direction with respect to the main surface of the semiconductor; The capacitor has a main surface of the semiconductor and a source/drain region formed on the bottom surface of the groove, and the capacitor has a multilayer structure having a charge storage electrode, a dielectric film, and a counter electrode. A semiconductor device, at least a portion of which is formed inside a groove formed in a thickness direction with respect to the semiconductor main surface. (2) further comprising a second groove formed in the thickness direction with respect to the main surface of the semiconductor substrate at the bottom of the groove formed in the thickness direction with respect to the main surface of the semiconductor substrate; 2. The semiconductor device according to claim 1, wherein a part of the type capacitor is further formed inside the second groove. (3) In a method of manufacturing a semiconductor device having a memory cell consisting of one transistor and one capacitor, a step of forming a first groove in the thickness direction with respect to the main surface of the semiconductor on the surface of the semiconductor substrate; A step of filling the inside of this first trench with a first insulating film, and removing a part of this first insulating film, and forming a second trench in the thickness direction on the main surface of the semiconductor again. a transistor having a channel region formed inside the second trench on a side surface of the second trench, a source/drain region on at least the bottom surface of the second trench and a main surface of the semiconductor; and a step of forming a capacitor having a charge storage electrode, a dielectric film, and a counter electrode at least inside the second groove. . (4) A transistor having a channel region formed on the side surface of the second trench, a source/drain region on the bottom surface of the second trench, and a main surface of the semiconductor is provided inside the second trench. After the forming step, there is further a step of forming a third groove inside the second groove in the thickness direction with respect to the main surface of the semiconductor, and a step of forming both this third groove and the second groove. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming a capacitor having a charge storage electrode, a dielectric film, and a counter electrode inside the semiconductor device.