TW201445704A - Semiconductor device and method of manufacturing therefor - Google Patents

Abstract

Provided is a twin plug forming process in which a contact hole that is between word lines (10b, 10c) and is enclosed by a bit line (16) is filled with a second conducting material and separated in the second direction, wherein without forming a conventional dummy word line, a diffusion layer separation trench (29) is formed by further etching the surface of a semiconductor substrate exposed between twin plugs, and the trench is filled with a diffusion layer separation insulating film (30) to separate a diffusion layer, and separate contact plugs (25b, 25c).

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

With the miniaturization of the semiconductor device, a method of forming a fine contact plug has been reviewed. The method described in Patent Document 1 is a method of dividing and refining a conductive material formed in a large contact hole in advance, and is extremely effective because there is a large margin in the processing margin. The method.

Fig. 16 is a view showing the construction of a semiconductor device 500 caused by Japanese Laid-Open Patent Publication No. 2011-243960. The semiconductor device 500 caused by the prior art example is a DRAM, FIG. 16(a) is a plan view, and FIG. 16(b) is a Y1-Y1' cross-sectional view of FIG. 16(a), and FIG. 16(c) is a cross-sectional view. Fig. 16(a) is a cross-sectional view taken along line X1-X1' of Fig. 16(a), and Fig. 16(d) is a cross-sectional view taken along line X2-X2' of Fig. 16(a).

First, a semiconductor device 500 of the prior art example will be described with reference to FIG.

The semiconductor device 500 is a memory cell constituting a DRAM. in On the semiconductor substrate 1, the element isolation region 2 continuously extending in the X' direction and the active region 1A extending continuously in the X' direction are alternately spaced at equal intervals in the Y direction. It is configured as a plural. The element isolation region 2 is formed by separating an insulating film from an element buried in the trench. The first buried word line (hereinafter referred to as a first word line) 10a, which is continuously extended in the Y direction, is disposed across the plurality of element isolation regions 2 and the plurality of active regions 1A. 2 buried word line (hereinafter referred to as second word line) 10b, third buried word line (hereinafter referred to as third word line) 10c, and fourth buried word line (hereinafter, Called the fourth character line) 10d. Further, the first embedded dummy word line (hereinafter referred to as a first dummy word line) 10e is disposed so as to be sandwiched by the second word line 10b and the third word line 10c. The first dummy word line 10e is provided with element separation by keeping the parasitic transistor DTr1 in an OFF state between the cell Tr2 to Tr3 adjacent to each other in the extending direction of the active region 1A. And the continuous strip-shaped active region 1A is divided into functions of a plurality of independent active regions. Specifically, the active region 1A located on the left side of the first dummy word line 10e is the first active region 1Aa', and the active region 1A positioned at the right side is the second active region 1Ab'. segmentation.

The first active region 1Aa' includes a second capacity contact region 27b disposed adjacent to the left side of the first dummy word line 10e, and a second capacity contact region 27b disposed adjacent to the second capacity contact region 27b. The word line 10b and the first bit line contact region 17c disposed adjacent to the second word line 10b and adjacent to the first bit line contact region 17c The first character line 10a to be placed and the first capacity contact region 27a disposed adjacent to the first word line 10a are formed. The first dielectric crystal Tr1 is formed by the first capacitance contact region 27a, the first word line 10a, and the first bit line contact region 17c, and the first bit line contact region 17c and the second word line are formed. 10b and the second capacity contact region 27b constitute the second transistor crystal Tr2.

The second active region 1Ab' includes a third capacity contact region 27c that is disposed adjacent to the right side of the first dummy word line 10e, and a third capacity contact region 27c that is disposed adjacent to the third capacity contact region 27c. The word line 10c and the second bit line contact region 17b disposed adjacent to the third word line 10c and the fourth character arranged adjacent to the second bit line contact region 17b The line 10d and the fourth capacity contact region (not shown) disposed adjacent to the fourth word line 10d are formed. The third transistor crystal region Tr3 is formed by the third capacity contact region 27c, the third word line 10c, and the second bit line contact region 17b, and the second bit line contact region 17b and the fourth word line are formed. 10d and a fourth capacity contact region (not shown) constitute a fourth transistor Tr4 (not shown).

The memory cell of the prior art example is configured by arranging the above-described first active region 1Aa and second active region 1Ab in a plurality of places in the X direction via the first dummy word line 10e.

At the semiconductor substrate 1, a groove for a word line which also serves as a gate electrode of the transistor is provided. At the bottom of each of the trenches, a gate insulating film 6 covering the inner surface of each of the word line trenches is provided, and a metal film 8 such as a barrier film 7 or a tungsten film is provided. First character line 10a, second word line 10b, dummy word line 10e, third word line, and fourth word line 10c. Here, for convenience of explanation, the word line passing through the first active region 1Aa' is referred to as a first word line 10a and a second word line 10b, and the word line passing through the second active region 1Ab' is referred to. The third word line 10c and the fourth word line 10d are formed. However, each of the active areas has two word lines, and dummy elements are arranged between the active areas. . Further, a cap insulating film 11 which covers each of the word lines and is buried in each of the grooves is provided. The semiconductor pillar positioned on the left side of the first word line 10a is the first capacitance contact region 27a, and the impurity diffusion layer 26a serving as one of the source/drain electrodes is provided on the semiconductor pillar. The semiconductor pillar positioned between the first word line 10a and the second word line 10b is the third BL contact region 17c, and the impurity diffusion of the other source/drain is provided thereon. Layer 12c. Further, the semiconductor pillar positioned on the right side of the second word line 10b is the second capacitance contact region 27b, and the impurity diffusion layer 26b serving as one of the source/drain electrodes is provided on the semiconductor pillar. Further, the semiconductor pillar positioned on the left side of the third word line 10c is the third capacitance contact region 27c, and the impurity diffusion layer 26c serving as one of the source/drain electrodes is provided on the semiconductor pillar. Further, the semiconductor pillar positioned on the right side of the third word line 10c is the second BL contact region 17b, and the impurity diffusion layer 12b serving as the other source/drain is provided on the semiconductor pillar.

A second bit line (BL) 16b connected to the second impurity diffusion layer 17b is provided on the cap insulating film 11 covering the upper surface of each word line, and is provided in the second BL contact region 12b. 3BL contact area The third bit line (BL) 16c connected to the third impurity diffusion layer 17c is provided at 12c. Each of the bit lines is provided with a polysilicon layer 13 including a bit contact plug connected to the impurity diffusion layer, and a bit metal layer 14 formed thereon and a cover insulating film further formed thereon. 15. A liner insulating film 19 is provided on the sidewall of each of the main lines in such a manner as to cover the side walls 18 and the bit lines. The buried insulating film 19 is provided with a buried insulating film 20 for embedding a recessed space formed between adjacent BLs. The insulating film 20 and the lining film 19 are buried, and the capacitance contact portion 25 is provided. The capacity contact portion 25 is connected to the first, second, and third capacity contact regions 27a, 27b, and 27c, and the first, second, and third capacity contact plugs 25a, 25b, and 25c are connected, respectively. The cap insulating film 11 on the dummy word line 10e is provided with a separation insulating film 30' for separating the second and third capacitance contact plugs 25b and 25c. The second capacity contact plug 25b of the first element isolation region 1Aa' separated by the dummy word line 10e and the third capacitance contact plug 25c of the second element isolation region 1Ab' are one. The large contact plug 25 is formed as a double plug formed by division, and has a separation insulating film 30' at a divided surface thereof. Contact pads 33 are connected to the upper portions of the first, second, and third capacity contact plugs 25a, 25b, and 25c, respectively. The stopper film 34 is provided in such a manner as to cover the capacity contact plug 33. On the capacity contact plug 33, a lower electrode 35 is provided. A capacity insulating film 36 that continuously covers the inner wall and the outer wall surface of the lower electrode 35 is provided, and an upper electrode 37 is provided on the capacity insulating film 36 to constitute a capacitor.

In the above prior art, the elements of the first active region 1Aa' and the second active region 1Ab' are separated by the first dummy word line 10e. In this configuration, it is necessary to open the capacity contact hole above the first dummy word line 10e which is formed first, and embed the polysilicon plug, and then perform the second capacity contact plug by etch back. The separation of 25b and the third capacity contact plug 25c. Therefore, the second capacity contact region 27b and the second capacity contact plug 25b and the third capacity contact region 27c and the third capacity contact plug are caused by the difference in the size of the dummy word line or the offset at the time of the overlap. There is a possibility that the contact area of the plug 25c is lowered, and there is still room for improvement.

In the present invention, the diffusion layer separation trench is formed by self-integration at the semiconductor substrate by etching at the time of formation of the double plug, and the decrease in the contact area between the capacitance contact plug and the capacitance contact region is suppressed.

That is, according to one embodiment of the present invention, there is provided a semiconductor device characterized by comprising: a plurality of element isolation regions extending in a first direction on a semiconductor substrate; and a package An active region interposed between the element isolation regions and extending in the first direction; and two roots 1 extending in a second direction intersecting the first direction and arranged at a predetermined interval a pair of complex grooves; and a pair of buried word lines embedded in the groove; and extending in a third direction different from the first and second directions, and being embedded with the aforementioned character a bit connecting the first diffusion layer of the active region between the pairs a line connecting the first diffusion layer to the bit line to the second diffusion layer facing the active region in the first direction via each of the buried word line pairs a contact portion; and an active region interposed between the pair of buried word lines; and the active region between the contact portions on both sides of the buried region and the contact portion An integral diffusion layer separation insulating film which is insulated and separated between the second diffusion layers.

According to still another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a plurality of element isolation regions extending in a first direction on a semiconductor substrate, and planning a process of extending the active region existing in the first direction between the element separation regions; and forming the extension in a second direction intersecting the first direction, and at the first pitch and the first section a second trench having a longer distance from the second element pitch to form a shallower plurality of first trenches; and a first conductive material buried in the first trench of the plurality of gates via a gate insulating film And the process of forming the two first pair of word lines at a lower position than the surface of the semiconductor substrate; and forming the groove on the word line a process of embedding the insulating film; and forming an active region between the trench formed by the first pitch on the insulating film, and extending in a difference from the first and second directions 3 directions And a process of forming a bit line of the upper insulating film; and forming a mask pattern formed on the pair of the two word lines and extending in the second direction to form the second pitch The active area between the trenches is exposed, and the opening is a method of defining a contact hole between the bit lines and the mask pattern; and embedding the second conductive material in a manner of filling the contact hole until a position lower than an upper portion of the mask pattern And forming a side wall at a side wall of the mask pattern to form an opening portion for exposing an upper surface of the second conductive material; and etching the second conductive material by using the sidewall as a mask The second conductive material is divided into two in the second direction, and the semiconductor substrate is etched to form a diffusion layer separation trench; and the diffusion layer separation trench is buried and a diffusion layer is formed over the entire surface. The insulating film is etched back after the diffusion layer separation insulating film is exposed so that the mask pattern and the second conductive material are exposed, and the second conductive material is etched back until the bit line is formed. The second insulating film is formed below the height of the upper insulating film, and the insulating layer is separated by the diffusion layer in the contact hole. The material into the electrical contact plugs of the project.

According to one embodiment of the present invention, the elements of the prior art which are caused by the dummy word lines are separated, and the diffusion layer is separated by self-integration at the semiconductor substrate by etching during the formation of the double plug. The groove serves to suppress a decrease in the contact area between the capacity contact plug and the capacity contact region.

1‧‧‧Semiconductor substrate

1A‧‧‧Active area

1Aa‧‧‧1st active area

1Ab‧‧‧2nd active area

2‧‧‧Component separation area

2a‧‧‧lining nitride film

2b‧‧‧矽Oxide film

3‧‧‧Sand oxide film

4‧‧‧hard mask

5‧‧‧The groove of the word line

6‧‧‧Gate insulation film

7‧‧‧Block film

8‧‧‧Metal film

10a, 10b, 10c, 10d‧‧‧ character lines

10e‧‧‧Fake word line

11‧‧‧Cap insulation film

12‧‧‧N type impurity diffusion layer

13‧‧‧Polysilicon film

14‧‧‧Tungsten film

15‧‧‧矽Nitride film

16‧‧‧ bit line

17‧‧‧ bit line contact area

18‧‧‧矽Nitride film

19‧‧‧ lining film

20‧‧‧SOD film

21b‧‧‧Cap oxide film

22‧‧‧ Mask polycrystalline silicon film

23‧‧‧ Capacity contact hole

24‧‧‧ nitride film sidewall

25‧‧‧Polysilicon plug

26, 26a~26c‧‧‧N type impurity diffusion layer

27a~27c‧‧‧Capacity contact area

28‧‧‧矽Nitride film

29‧‧‧Diffusion separation trench

30‧‧‧Diffusion layer separation insulating film

31‧‧‧Block film

32‧‧‧Metal film

33‧‧‧Capacity contact gasket

34‧‧‧stop film

35‧‧‧lower electrode

36‧‧‧ Capacity insulating film

37‧‧‧Upper electrode

100‧‧‧Semiconductor device

Fig. 1(a) is a schematic plan view showing a semiconductor device 100 which is one of the embodiments of the present invention, and Fig. 1(b) is Fig. 1 (a) Y1-Y1' sectional view, Fig. 1(c) is the X1-X1' sectional view of Fig. 1(a), and Fig. 1(d) is the X2-X2' sectional view of Fig. 1(a) .

2 to FIG. 15 are diagrams showing a series of manufacturing engineering cross-sectional views of the semiconductor device 100 of the present embodiment. In each of the drawings, (a) is a schematic plan view, and (b) is (a). The Y1-Y1' cross-sectional view, (c) is the X1-X1' cross-sectional view of (a), and (d) is the X2-X2' cross-sectional view of (a).

16(a) is a schematic plan view showing a semiconductor device 500 of the prior art example, and FIG. 16(b) is a Y1-Y1' cross-sectional view of FIG. 16(a), and FIG. 16(c) is FIG. (a) is a X1-X1' cross-sectional view, and Fig. 16(d) is a X2-X2' cross-sectional view of Fig. 16(a).

Hereinafter, the preferred embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiments of the present invention, and includes those skilled in the art that can be used in the present invention. It is suitable for the composition of the changes within the scope.

(Embodiment 1)

The semiconductor device 100 according to the present embodiment is a DRAM. Fig. 1(a) is a schematic plan view, and Fig. 1(b) is a Y1-Y1' cross-sectional view of Fig. 1(a), Fig. 1(c) The figure is the X1-X1' cross-sectional view of Fig. 1(a), and Fig. 1(d) is the X2-X2' cross-sectional view of Fig. 1(a). 2 to 15 are the semiconductor device 100 of the embodiment. A series of manufacturing engineering profiles are shown. In each figure, (a) is a schematic plan, (b) is a Y1-Y1' profile of (a), and (c) is a (a) X1 -X1' sectional view, (d) is the X2-X2' cross-sectional view of (a).

First, a description will be given of a semiconductor device 100 of the present embodiment with reference to Fig. 1 .

The semiconductor device 100 is a memory cell that constitutes a DRAM. On the semiconductor substrate 1, the element isolation region 2 continuously extending in the X' direction (first direction) and the active region 1A extending continuously in the X' direction are in the Y direction (second direction) The above is interactively arranged at equal intervals and equal pitches. The element isolation region 2 is formed by separating an insulating film from an element buried in the trench. The first buried word line (hereinafter referred to as a first word line) 10a, which is continuously extended in the Y direction, is disposed across the plurality of element isolation regions 2 and the plurality of active regions 1A. 2 buried word line (hereinafter referred to as second word line) 10b, third buried word line (hereinafter referred to as third word line) 10c, and fourth buried word line (hereinafter, Called the fourth character line) 10d. Further, the diffusion layer separation groove 29 is disposed so as to be sandwiched by the second word line 10b and the third word line 10c. In the diffusion layer separation trenches 29, the diffusion layer separation insulating film 30 in which a tantalum nitride film or the like is buried is provided, and is provided with a function of dividing the continuous strip-shaped active region 1A into a plurality of mutually independent active regions. By. Specifically, the active region 1A located on the left side of the diffusion layer separation groove 29 is the first active region 1Aa, and is located at the active region 1A on the right side, and serves as the second active region. Domain 1Ab. Further, the extension is present in the X direction (in the third direction), and the first to third bit lines (BL) 16a to 16c are provided.

The first active region 1Aa includes a second capacity contact region 27b disposed adjacent to the left side of the diffusion layer separation trench 29, and a second word line disposed adjacent to the second capacitance contact region 27b. 10b, and a contact region 17c (third BL contact region) between the third BL 16c and the first character arranged adjacent to the third BL contact region 17c, which is disposed adjacent to the second word line 10b, and a first character arranged adjacent to the third BL contact region 17c The line 10a and the first capacity contact region 27a disposed adjacent to the first word line 10a are formed. The first transistor contact region 27a, the first word line 10a, and the third BL contact region 17c constitute the first transistor crystal Tr1, and the third BL contact region 17c and the second word line 10b are in contact with the second capacity. The region 27b constitutes the second transistor Tr2.

The second active region 1Ab includes a third capacity contact region 27c disposed adjacent to the right side of the diffusion layer separation trench 29, and a third word line disposed adjacent to the third capacitance contact region 27c. 10c, and a contact region 17b (second BL contact region) disposed between the second BL 16b adjacent to the third word line 10c, and a fourth character arranged adjacent to the second BL contact region 17b The line 10d and the fourth capacity contact region (not shown) disposed adjacent to the fourth word line 10d are formed. The third transistor crystal region Tr3 is formed by the third capacity contact region 27c, the third word line 10c, and the second BL contact region 17b, and the second BL contact region 17b and the fourth word line 10d are not shown. The fourth capacity contact region constitutes the fourth transistor Tr4.

The memory cell of the present embodiment is configured by arranging the above-described first active region 1Aa and second active region 1Ab in a plurality of places in the X direction (third direction) via the diffusion layer separation groove 29. By.

The gate insulating film 6 is covered by the inner surface of the groove for the word line which is also provided as the gate electrode of the transistor on the bottom of each of the trenches, and is provided with The first word line 10a, the second word line 10b, the third word line 10c, and the fourth word line 10d of the metal film 8 such as the barrier film 7 and the tungsten film. Further, a cap insulating film 11 which covers each of the word lines and is buried in each of the grooves is provided. The semiconductor pillar positioned on the left side of the first word line 10a is the first capacitance contact region 27a, and the impurity diffusion layer 26a serving as one of the source/drain electrodes is provided on the semiconductor pillar. The semiconductor pillar positioned between the first word line 10a and the second word line 10b is the third BL contact region 17c, and the impurity diffusion of the other source/drain is provided thereon. Layer 12c. Further, the semiconductor pillar positioned on the right side of the second word line 10b is the second capacitance contact region 27b, and the impurity diffusion layer 26b serving as one of the source/drain electrodes is provided on the semiconductor pillar. Further, the semiconductor pillar positioned on the left side of the third word line 10c is the third capacitance contact region 27c, and the impurity diffusion layer 26c serving as one of the source/drain electrodes is provided on the semiconductor pillar. Further, the semiconductor pillar positioned to the right of the third word line 10c is the second BL contact region 17b, and the impurity diffusion layer 12b serving as the other source/drain is provided on the semiconductor pillar.

At the first active region 1Aa, the impurity diffusion layer 26a and the gate are used. The pole insulating film 6 and the first word line 10a and the impurity diffusion layer 12c constitute the first transistor Tr1. Moreover, the second transistor Tr2 is configured by the impurity diffusion layer 12c and the gate insulating film 6, the second word line 10b, and the impurity diffusion layer 26b. The cap insulating film 11 is provided so as to cover the upper surfaces of the word lines 10a and 10b. The cap insulating film 11 is provided with a third BL 16c connected to the impurity diffusion layer 12c at the third BL contact region 17c. In the second active region 1Ab, the third transistor Tr3 is formed by the impurity diffusion layer 26c, the gate insulating film 6, the third word line 10c, and the impurity diffusion layer 12b. In addition, the fourth transistor Tr4 is formed by the impurity diffusion layer 12b, the gate insulating film 6, the fourth word line 10d, and an impurity diffusion layer (not shown). The cap insulating film 11 is provided so as to cover the upper surfaces of the word lines 10c and 10d. The cap insulating film 11 is provided in the second BL contact region 17b and is provided with a second BL 16b connected to the impurity diffusion layer 12b.

Each of the bit lines is provided with a polysilicon layer 13 including a bit contact plug connected to the impurity diffusion layer, and a bit metal layer 14 formed thereon and a cover insulating film further formed thereon. 15. A liner insulating film 19 is provided on the sidewall of each of the main lines in such a manner as to cover the side walls 18 and the bit lines. The buried insulating film 19 is provided with a buried insulating film 20 for embedding a recessed space formed between adjacent BLs. The insulating film 20 and the lining film 19 are buried, and the capacitance contact portion 25 is provided. The capacity contact portion 25 is connected to the first, second, and third capacity contact regions 27a, 27b, and 27c, and the first, second, and third capacity contact plugs 25a, 25b, and 25c are connected, respectively. In the first 1. The upper portion of the second and third capacity contact plugs 25a, 25b, and 25c are connected to the capacity contact pads 33, respectively. The stopper film 34 is provided so as to cover the capacity contact pad 33. On the capacity contact pad 33, a lower electrode 35 is provided. A capacity insulating film 36 that continuously covers the outer wall surface from the inner wall of the lower electrode 35 is provided, and an upper electrode 37 is provided on the capacity insulating film 36 to constitute a capacitor. The upper electrode 37 may be a laminate of a plurality of films, and may include a first upper electrode of titanium nitride or the like which is formed conformally on the capacity insulating film 36, and fill the voids. A packed layer (second upper electrode) in which a polycrystalline germanium or the like is buried, or a flat electrode (third upper electrode) made of a metal such as tungsten, which is a connection portion with the upper wiring, or the like.

In the semiconductor device 100, the diffusion layer separation trench 29 is formed when the second capacitance contact plug 25b and the third capacitance contact plug 25c are separated, and the insulating film 30 is separated by the diffusion layer in the trench. For the purpose of embedding, the first active region 1Aa and the second active region 1Ab are separated from each other. Specifically, the second capacity contact plug 25b and the third capacity contact plug 25c are separated by etch back. Thereafter, the exposed semiconductor device 1 is etched by dry etching to form a diffusion layer separation trench 29. Further, the diffusion layer separation insulating film 30 is buried in the inside of the trench to separate the elements. In the prior art, this element is separated by a buried dummy word line 10e formed at the same time as the buried word line 10 is formed. In this configuration, it is necessary to form the buried word line and open the capacity contact portion 23 thereon to separate the second capacity contact plug 25b and the third capacity contact plug 25c. therefore, The second capacity contact region 27b and the second capacity contact plug 25b, the third capacity contact region 27c, and the third capacity contact plug may occur due to a difference in the size of the buried dummy word line or an offset at the time of overlap. The case where the contact area of 25c is lowered. In the present invention, since the connection between the second capacity contact region 27b and the second capacity contact plug 25b and the connection between the third capacity contact region 27c and the third capacity contact plug 25c are performed, The diffusion layer separation trenches 29 are formed in the same manner, so that the decrease in the contact area due to the variation in the size or overlap of the buried dummy word lines does not occur.

Hereinafter, a method of manufacturing the semiconductor device 100 shown in FIG. 1 will be described with reference to FIGS. 2 to 15.

First, as shown in FIG. 2, on the semiconductor substrate 1, an insulating film containing a tantalum oxide film which is present in the first direction (X' direction) is formed by a well-known STI method. The buried component separation region 2 is made. Thereby, the active region 1A formed by the semiconductor substrate 1 surrounded by the element isolation region 2 is formed. In addition, although the element isolation region 2 has a laminated structure in which the lining nitride film 2a and the tantalum oxide film 2b are shown, it is not limited thereto.

Next, on the entire surface of the semiconductor substrate 1, a pad oxide film 3 made of a tantalum oxide film is formed, and through the pad oxide film 3, a well N (not shown) region and a P well region are formed by a known method. .

Next, a tantalum oxide film or the like is deposited on the semiconductor substrate 1, and a hard mask 4 extending in the Y direction and used to form a plurality of grooves 5 of a predetermined width is patterned by a photoresist (not shown). . Between the grooves 5 formed The partition is alternately set to the first pitch P1 and the second pitch P2 which is longer than P1. Usually, the second pitch P2 is set to be about twice as large as the first pitch P1, but is not limited thereto.

Next, as shown in FIG. 3, the semiconductor substrate 1 is etched by dry etching, and a trench 5 is formed. The groove 5 (5a and 5b or 5c and 5d) is a groove for the word line as in the prior art, and between the two pairs of grooves (between 5b and 5c), a dummy word line of the prior art is formed. The groove is used, but in the present invention, the groove for the dummy word line is not formed. At this time, by etching the tantalum oxide film of the element isolation region 2 to be deeper than the semiconductor substrate 1, it can be set as a saddle fin structure (refer to the dummy word line 10e of the prior art). The saddle fin is not necessarily required to be set, and the groove depth at the active region 1A and the element separation region 2 may be set to be slightly equal. Thereby, the active region 1A is divided into a first portion which is sandwiched between the pair of grooves 5a and 5b (or 5d and 5e), and a second portion which is sandwiched between the grooves 5b and 5c. The first portion is a region to which a bit line is connected, and the second portion is a region to which a capacitance contact plug is connected after the diffusion layer separation groove 29 is formed.

Thereafter, a gate insulating film 6 is formed on the active region 1A of the semiconductor substrate 1 by thermal oxidation, a nitridation process, or the like. By thermal oxidation, the lining nitride film of the element isolation region 2 is also partially oxidized, and the tantalum oxide film is converted into a hafnium oxide film by a subsequent nitridation process. Thereby, the gate insulating film 6 is also continuously formed on the insulating film of the element isolation region 2 and the hard mask 4.

Further, as shown in FIG. 4, a barrier film 7 of titanium nitride or the like is generally used. The metal film 8 or the like of tungsten or the like is deposited by, for example, a CVD method, and etched back, whereby the word lines 10a, 10b, 10c, and 10d are formed in the grooves 5a, 5b, 5c, and 5d.

Next, as shown in FIG. 5, generally, the remaining metal film 8 and the inner walls of the grooves 5a to 5d are covered, for example, by a CVD method, by a ruthenium nitride film or the like. Lining film. On the lining film, a tantalum oxide film is deposited. Thereafter, CMP is performed to planarize the surface until the liner film is exposed. Further, the exposed liner film is removed, and the hard mask 4 and the tantalum oxide film are etched back to a predetermined height. Thereby, the buried word line buried by the cap insulating film 11 is formed. The cap insulating film 11 can also be formed to cover the hard mask 4 in the case where the remaining hard mask 4 is thin, and is in contact with the bit line and the capacity to be formed by the subsequent engineering. A sufficient distance is ensured between the diffusion layers that are plugged together.

Next, as shown in FIG. 6, generally, one portion of the hard mask 4 is removed using a photolithography technique and a dry etching technique, and a contact region with each bit line is formed, and a third BL contact region 17c is formed in FIG. 7B and A bit contact portion that is connected to the upper surface of the second BL contact region 17b. The bit contact portion is formed as a linear opening pattern extending in the same direction (Y direction) as the word line 10. The surface (first portion) of the semiconductor substrate 1 is exposed at a portion where the pattern of the bit contact portion and the active region intersect. After the formation of the bit contact portion, an N-type impurity (arsenic or the like) is ion-implanted, and an N-type impurity diffusion layer 12 is formed in the vicinity of the surface of the crucible. The formed N-type impurity diffusion layer 12 functions as a source and a drain region of the transistor. After that, for example, by the CVD method A laminated film of a polycrystalline germanium film 13, a tungsten film 14, a germanium nitride film 15, or the like is formed. Thereafter, a line shape extending in a direction (X direction) crossing the word line 10 is patterned using a photolithography technique and a dry etching technique to form a bit line 16. The polysilicon film 13 and the N-type impurity diffusion layer 12 underlying the bit line are connected at a portion of the surface of the germanium exposed in the bit contact portion. At the portion shown in Fig. 6(c), the second BL16b and the N-type impurity diffusion layer 12b are connected, and the third BL16c and the N-type impurity diffusion layer 12c are connected.

Next, as shown in FIG. 7, after forming the tantalum nitride film 18 covering the sides of the respective bit lines 16, the hard mask 4 of the tantalum oxide film, the pad oxide film 3, and the cap are etched. One portion of the insulating film 11 is removed, and etch back is performed such that the surface of the cap insulating film 11 is substantially the same level as the surface of the semiconductor substrate 1.

Next, as shown in FIG. 8, generally, a lining film 19 covering the upper surface thereof is formed by, for example, a ruthenium nitride film or the like using a CVD method. The SOD film 20 as a coating film is deposited so as to fill the space between the bit lines, and then annealed in a high-temperature steam (H ₂ O) atmosphere to be modified into a solid. membrane. After CMP is performed and planarized until the upper surface of the lining film 19 is exposed, a ruthenium oxide film formed by, for example, a CVD method is formed as the cap oxide film 21, and the surface of the SOD film 20 is formed. cover. Further, a mask polysilicon film 22 is formed on the cap oxide film 21.

Next, as shown in FIG. 9, generally, a photo contact hole 23 is formed using a photolithography technique and a dry etching technique. Specifically, using light lithography The technique is patterned into a linear shape, and the brim oxide film 21 and the mask polysilicon film 22 are used as a capacitive contact portion hard mask. The capacity contact portion hard mask is formed as a linear opening pattern extending in the same direction (Y direction) as the word line and opening the second portion of the active region.

The capacity contact hole 23 is formed through the SOD film 20 and the lining film 19 by a dry etching technique. The semiconductor substrate 1 (second portion) is exposed at a portion where the capacitance contact hole 23 and the active region 1A intersect. Next, a tantalum nitride film is formed, for example, by a CVD method, and etched back to form a nitride film sidewall 24.

Next, as shown in FIG. 10, in the inside of the capacity contact hole 23, polycrystalline germanium doped with an N-type impurity (phosphorus or the like) is buried, for example, by a CVD method. Next, the polysilicon is etched back and the polysilicon remains as a height which does not completely fill the inside of the capacity contact hole 23, thereby forming the polysilicon plug 25. At this time, the mask polysilicon film 22 is also removed. An N-type impurity diffusion layer 26 is formed in the vicinity of the surface of the second portion by the N-type impurity doped in the polysilicon plug 25. The formed N-type impurity diffusion layer 26 functions as a source and a drain region of the transistor.

Next, as shown in FIG. 11, generally, the tantalum nitride film 28 is formed in such a manner as to cover the remaining polysilicon plugs 25 in the capacitance contact holes.

Next, as shown in FIG. 12, in general, the tantalum nitride film 28 is etched back to form a nitride film sidewall 28S. Thereafter, the nitride film sidewall 28S is used as a mask, and the polysilicon plug 25 is dry etched. Specifically, the second capacitance that is connected to the N-type impurity diffusion layer 26 can be The quantity contact plug 25b and the third capacity contact plug 25c are separated in the X direction. Further, in this state, each of the polysilicon plugs 25 is connected to the bit line 16 under the nitride film side wall 28S and connected in the Y direction. The semiconductor substrate 1 is exposed between the second capacity contact plug 25b and the third capacitance contact plug 25c.

Here, in the present embodiment, as shown in FIG. 12, the exposed semiconductor substrate 1 is further etched by dry etching to form the diffusion layer separation trench 29. The diffusion layer separation groove 29 is formed to be equal to or higher than the depth of the word line 10, but may be appropriately adjusted within a range up to the same depth as the element isolation region 2. Thereby, the polysilicon plug 25 is self-integratedly separated into the capacitance contact plugs 25a, 25b, and 25c, and the N-type impurity diffusion layer 26 is self-integratedly separated into the impurity diffusion layers 26a, 26b, and 26c.

Next, as shown in FIG. 13, the diffusion layer separation trench 29 is buried by a tantalum nitride film or the like, and covers the sidewall 矽 nitride film 28S and the capacitance contact plugs 25a, 25b, and 25c. The diffusion layer separation insulating film 30 is formed.

Next, as shown in FIG. 14, the diffusion layer separation insulating film 30 and the sidewall 矽 nitride film 28S are polished by CMP to be planarized until the upper surface of the cap insulating film 15 on the bit line 16 is exposed. until. Thereby, the polysilicon plug 25 is separated in the Y direction by the bit line 16. Thereafter, the polysilicon plug 25 is etched back, and the capacitive contact is completed by the polysilicon remaining at the lower portion of the capacitance contact hole 23. Plugs 25a, 25b, 25c.

Next, as shown in FIG. 15, generally, a portion of the capacity contact hole where the capacitance contact plug 25 is not buried is used, and a barrier film 31 of titanium nitride or the like, tungsten or the like is used by a CVD method. A wiring material layer such as the metal film 32 is buried. Next, the capacitive contact pads 33 are formed using photolithography and dry etching techniques. A vapor film of cobalt telluride or the like may be formed on the upper surface of the capacity contact plug 25 to lower the contact resistance with the capacity contact pad 33.

Thereafter, as shown in FIG. 1, the stopper film 34 is formed using a tantalum nitride film in such a manner as to cover the capacity contact pad 33. On the capacity contact pad 33, the capacitor element lower electrode 35 is formed by titanium nitride or the like. Thereafter, after the capacity insulating film 36 is formed so as to cover the surface of the lower electrode 35, the capacitor element upper electrode 37 is formed by titanium nitride or the like. Thereafter, although not shown, the multilayer wiring is formed by repeating the wiring forming process to form the semiconductor device 100.

In the embodiment of the method for manufacturing a semiconductor device, the diffusion layer separation groove 29 is formed when the second capacitance contact plug 25b and the third capacitance contact plug 25c are separated, and the groove is formed by the groove. The diffusion layer separates the insulating film 30 to be buried, and the first active region 1Aa and the second active region 1Ab are separated from each other. Specifically, the second capacity contact plug 25b and the third capacity contact plug 25c are separated by etch back. Thereafter, the exposed semiconductor substrate 1 is etched by dry etching to form a diffusion layer separation trench 29. Further, the diffusion layer separation insulating film 30 is buried in the inside of the trench to separate the elements. Prior art In this case, the element is separated by a buried dummy line formed at the same time as the buried word line WL10 is formed. In this configuration, the dummy dummy word line is formed first, and the capacity contact hole 23 is opened thereon to separate the second capacity contact plug 25b and the third capacity contact plug 25c. Therefore, the second capacity contact region 27b and the second capacity contact plug may occur due to the difference in the size of the buried dummy word line or the overlap of the overlap of the mask (side wall 28S) when the contact plug is separated. The possibility that the contact area of 25b and the third capacity contact region 27c and the third capacity contact plug 25c is lowered. In the present invention, since the contact hole 23 which opens the second portion of the active region between the adjacent pairs of word lines is formed, the polysilicon plug 25 and the N-type diffusion layer 26 which become the capacitance contact plugs are formed. And the diffusion layer separation trench 29 separating the diffusion layer 26 is formed by self-alignment simultaneously with the division of the polysilicon plug 25, and therefore, the system does not cause the dummy word due to the prior art. The diffusion layer 26b (second capacitance contact region 27b) and the second capacitance contact plug 25b and the diffusion layer 26c (the third capacitance contact region 27c) caused by the difference in the size of the element line or the overlap with the mask The case where the contact area of the third capacity contact plug 25c is lowered.

Further, in the present embodiment, the etch back of the polysilicon plug 25 (Fig. 14) and the subsequent formation of the contact pad 33 (Fig. 15) are not absolutely necessary. In the present invention, the contact plug formed in one contact hole 23, that is, two contact plugs which are opposed to each other in the X direction by the diffusion layer separation insulating film 30 (in the figure) , is 25b and 25c), because it is possible to utilize the inclined surface of the hard cover of the capacity contact portion, Further, since the distance between the centers of the upper portions is formed to be wider than the distance between the centers of the lower portions, even if the capacitors under the capacitors are formed on the capacitance contact plugs, the interval between the capacitors can be sufficiently ensured.

1‧‧‧Semiconductor substrate

2‧‧‧Component separation area

2a‧‧‧lining nitride film

2b‧‧‧矽Oxide film

6‧‧‧Gate insulation film

7‧‧‧Block film

8‧‧‧Metal film

10a, 10b, 10c, 10d‧‧‧ character lines

12b, 12c‧‧‧ impurity diffusion layer

16a~16c‧‧‧1st to 3rd bit line (BL)

17b‧‧‧2BL contact area

17c‧‧‧3BL contact area

21‧‧‧Cap oxide film

24‧‧‧ nitride film sidewall

25a, 25b, 25c‧‧‧ capacity contact plugs

26a~26c‧‧‧N type impurity diffusion layer

28S‧‧‧ nitride film sidewall

29‧‧‧Diffusion separation trench

30‧‧‧Diffusion layer separation insulating film

Claims (15)

A semiconductor device comprising: a plurality of element isolation regions extending in a first direction on a semiconductor substrate; and being sandwiched between the element isolation regions and extending in the first direction An active region; and a pair of buried word pairs extending in a second direction intersecting the first direction and arranged at a predetermined interval; and extending in the foregoing a bit line connected to the first diffusion layer of the active region between the pair of buried word lines in the third direction different from the first direction and the second direction; and a connection to the bit line The first diffusion layer is connected to the second diffusion layer in the active region in the first direction via the buried word line pair; and embedded in the buried layer In the active region between the pair of word lines, the diffusion between the contact portions on both sides of the buried region and the second diffusion layer of the active region to which the contact portion is connected is insulated and separated The layer separates the insulating film. The semiconductor device according to the first aspect of the invention, wherein the diffusion layer separation insulating film is disposed between the respective bit lines in the second direction. The semiconductor device according to claim 1, wherein the bottom of the diffusion layer separation insulating film is set to be buried from the above The depth from the bottom of the word line to the bottom of the aforementioned element separation region. The semiconductor device according to claim 1, wherein the contact plug separates the insulating film and the diffusion layer via the diffusion layer alternately between the bit lines along the third direction. The insulating film having a different insulating film is separated for a plurality of configurations. The semiconductor device according to claim 1, wherein the diffusion layer separation insulating film comprises a hafnium nitride film. The semiconductor device according to any one of the first aspect of the present invention, wherein the contact portion of the two opposing surfaces in the third direction is separated from the insulating layer by the diffusion layer. The distance between the centers is wider than the distance between the centers below. The semiconductor device according to claim 6, wherein the contact portion has a capacitance contact pad on the upper surface of the contact portion, and further includes a capacitor, and the capacitor is provided to be connected to the capacitance contact pad. The lower electrode and the upper electrode are opposed to the upper electrode via the capacity insulating film. A method of manufacturing a semiconductor device, comprising: forming a plurality of element isolation regions extending in a first direction on a semiconductor substrate, and planning to extend between the element isolation regions and extending in the one direction Engineering of the active region; and forming the extension in the second direction intersecting the first direction, and at the first pitch and the second pitch longer than the first pitch a process of alternately forming a plurality of first trenches that are shallower than the element isolation region; and a step of embedding the first conductive material in the first trench of the plural first via the gate insulating film; and the first conductive material The material is etched back to a position lower than the surface of the semiconductor substrate to form a pair of word lines; and an engineering for forming an insulating film for embedding the first groove on the word line And forming an active region between the groove formed by the first pitch on the insulating film, and extending in a third direction different from the first and second directions, and having an upper portion An operation of a bit line of the insulating film; and a mask pattern formed on the pair of the two word lines and extending in the second direction to form an activity between the grooves formed by the second pitch The area is exposed, and the opening is defined in a manner of a contact hole between the bit lines and the mask pattern; and a manner of filling the contact hole to a position lower than an upper portion of the mask pattern a project to embed a second conductive material; Forming a sidewall on a sidewall of the mask pattern to form an opening for exposing an upper surface of the second conductive material; and etching the second conductive material by using the sidewall as a mask a process in which the conductive material is divided into two in the second direction, and the semiconductor substrate is etched to form a diffusion layer separation trench; and The diffusion layer separation trench is buried and the diffusion layer separation insulating film is formed over the entire surface; and the diffusion layer separation insulating film is etched back in such a manner that the mask pattern and the second conductive material are exposed Thereafter, the second conductive material is etched back until the height of the upper insulating film is equal to or lower than the height of the upper insulating film, and the insulating layer is separated by the diffusion layer in the contact hole. The work of the contact plug formed by the conductive material. The method of manufacturing a semiconductor device according to the eighth aspect of the invention, wherein the diffusion layer separation groove has a bottom surface between a bottom surface of the first groove and a bottom surface of the element isolation region. And formed. The method of manufacturing a semiconductor device according to the invention of claim 8, wherein the diffusion layer separation insulating film comprises a hafnium nitride film. The method of manufacturing a semiconductor device according to claim 8, wherein the mask pattern is formed such that the contact hole is formed in an inclined shape that widens from the bottom portion toward the upper portion in the third direction. The method of manufacturing a semiconductor device according to the eighth aspect of the invention, wherein the third direction is a direction orthogonal to the second direction. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein in the forming a contact plug, the diffusion layer is separated from the insulating film, the mask pattern, and the front surface. The second conductive material is etched back until the height of the insulating film above the bit line. The method of manufacturing a semiconductor device according to claim 13, further comprising: further etching back the contact plug which is separated by separating the insulating film by the diffusion layer It becomes lower than the insulating film on the bit line and the upper surface of the mask pattern; and the third conductive material is formed on the entire surface, and the third conductive material is on the bit line in the second direction The upper portion is divided to form a contact pad which is partially extended on the aforementioned mask pattern or the diffusion layer separation insulating film. The method of manufacturing a semiconductor device according to claim 14, further comprising: forming a lower electrode connected to the contact pad and opposing a lower electrode via a capacitance insulating film; Engineering of the capacitor to the upper electrode.