JP2013219179A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve improvement in a data retention property and increase in current of a memory cell transistor.SOLUTION: A semiconductor device manufacturing method according to a present embodiment comprises: a step of forming element isolation regions on a semiconductor substrate to form active regions each of which is surrounded by the element isolation regions and composed of a semiconductor substrate; a step of etching the semiconductor substrate to form trenches for embedded dummy word lines and trenches for embedded word lines; a step of forming a first gate insulation film for a parasitic transistor on the active regions of the semiconductor substrate including the trenches for the embedded dummy word lines and the trenches for the embedded word lines; a step of removing the first gate insulation film which covers the trenches for the embedded word lines with remaining the first gate insulation film for the parasitic transistor; and a step of forming a second insulation film for a memory cell transistor in the trenches for the embedded word lines after removal of the first gate insulation film. In particular, a film thickness of the first gate insulation film is thicker than a film thickness of the second gate insulation film.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  An example of a semiconductor device will be described with reference to FIGS. FIG. 10 is a plan view showing a DRAM memory cell as the semiconductor device 100. FIG. 11 is a cross-sectional view taken along the line BB of FIG. 10 and shows the structure at the time when the formation of the capacitor is completed.

  Referring to FIG. 10, on the XY plane of a semiconductor (silicon) substrate, the element isolation region 12 and the active region 13 that continuously extend in the X ′ direction that forms an angle with respect to the X direction are related to the Y direction. Alternatingly arranged with equal width. Two adjacent buried word lines (hereinafter referred to as word lines) WL1 and WL2 that extend continuously in the Y direction across the element isolation region 12 and the active region 13 are arranged to face each other. Two first and second embedded dummy word lines (hereinafter referred to as dummy word lines) DWL1 and DWL2 are arranged adjacent to both sides of the two first and second word lines WL1 and WL2. Yes. In the active region between the first dummy word line DWL1 and the first word line WL1, the first capacitor contact region 27a in which the first capacitor contact plug 27b is disposed is located. In addition, a BL (bit line) contact region 22a is located in the active region between the two adjacent first and second word lines WL1 and WL2. Further, in the active region between the second word line WL2 and the second dummy word line DWL2, the second capacitor contact region 27c in which the second capacitor contact plug 27d is disposed is located. A BL 23a extending in the X direction perpendicular to the Y direction and connected to the BL contact region 22a in each active region 13 extending in the X 'direction is disposed.

  The first cell transistor Tr1 is configured by the first capacitor contact region 27a, the first word line WL1, and the BL contact region 22a. The BL contact region 22a, the second word line WL2, and the second capacitor contact region 27c constitute the second cell transistor Tr2.

  In the above configuration, the width D in the X direction of each of the first dummy word line DWL1, the first word line WL1, the second word line WL2, and the second dummy word line DWL2, the first capacitance contact region 27a, and the BL contact The width W in the X direction of each of the region 22a and the second capacitor contact region 27c has the same value.

  Next, a description will be given with reference to FIG. The semiconductor substrate 11 is provided with a groove 14b for forming a word line that also serves as a gate electrode of the transistor. Also, a dummy word line groove 14a is provided for isolating elements by keeping the parasitic transistors DTr1 and DTr2 in an off state between cell transistors adjacent to each other in the extending direction of each active region 13. The first dummy word line DWL1, the first word line WL1, the second word line WL2, and the second dummy are interposed through the gate insulating film 15 covering the inner surfaces of the respective dummy word line grooves 14a and word line grooves 14b. A word line DWL2 is provided at the bottom of each trench. These gate insulating films 15 are all equal in thickness. A cap insulating film 17 is provided so as to cover the upper surface of each word line and each dummy word line and to bury each groove.

  The semiconductor pillar located between the first dummy word line DWL1 and the first word line WL1 serves as a first capacitor contact region 27a, and an impurity diffusion layer 19a serving as one of source / drain is provided on the upper surface thereof. The semiconductor pillar located between the first word line WL1 and the second word line WL2 becomes a BL contact region 22a, and an impurity diffusion layer 18 serving as the other of the source / drain is provided on the upper surface thereof. Further, the semiconductor pillar located between the second word line WL2 and the second dummy word line DWL2 becomes a second capacitor contact region 27c, and an impurity diffusion layer 19b serving as one of source / drain is provided on the upper surface thereof. .

  The impurity diffusion layer 19a, the gate insulating film 15, the first word line WL1, and the impurity diffusion layer 18 constitute a first cell transistor Tr1. The impurity diffusion layer 18, the gate insulating film 15, the second word line WL2, and the impurity diffusion layer 19b constitute a second cell transistor Tr2. As described in FIG. 10, the width of each of the first dummy word line DWL1, the first word line WL1, the second word line WL2, and the second dummy word line DWL2 in the X ′ direction and the first capacitor contact region The widths in the X ′ direction of the 27a, the BL contact region 22 and the second capacitor contact region 27c are all equal.

  A first interlayer insulating film 21 is provided on the entire surface so as to cover the upper surface of the semiconductor substrate 11. On the first interlayer insulating film 21, a BL (bit line) 23a connected to the impurity diffusion layer 18 in the BL contact region 22a is provided. A cover insulating film 23b is provided on the upper surface of the BL 23a. A liner insulating film 24 is provided on the entire surface so as to cover the side wall of the BL 23a. On the liner insulating film 24, an embedded insulating film 25 is provided to embed a recessed space formed between adjacent BLs. A second interlayer insulating film 26 is provided on the buried insulating film 25.

  Through the second interlayer insulating film 26, the buried insulating film 25, the liner insulating film 24, and the first interlayer insulating film 21, the upper surfaces of the first and second capacitor contact regions 27a and 27c, that is, the impurity diffusion layers 19a and 19b are formed. First and second capacitor contact plugs 27b and 27d connected to each other are provided. A capacitor contact pad 28 is connected on the first and second capacitor contact plugs 27b and 27d. A third interlayer insulating film 29 is provided so as to cover the capacitor contact pad 28. A cylinder hole 30 is provided in the third interlayer insulating film 29 on the capacitor contact pad 28, and a lower electrode 31 is provided so as to cover the inner surface of the cylinder hole 30. A capacitor is formed by providing a capacitor insulating film 32 covering the inner surface of the lower electrode 31 and an upper electrode 33 on the capacitor insulating film 32 (Non-Patent Document 1).

T.A. Schloesser, et al, "A6F2 Burried Wordline DRAM Cell for 40nm and Beyond", pp. 809-812, IEDM 2008

  In the semiconductor device described above, the first dummy word line DWL1, the first word line WL1, and the second word are interposed via the gate insulating film 15 covering the inner surfaces of the respective dummy word line trenches 14a and the word line trenches 14b. A line WL2 and a second dummy word line DWL2 are provided at the bottom of the trench. All the gate insulating films 15 have the same thickness. Therefore, the threshold voltage at which the dummy word line parasitic transistors DTr1 and DTr2 are turned on is the same as the threshold voltage of the cell transistors Tr1 and Tr2. Therefore, the semiconductor device described above cannot supply a voltage necessary for maintaining sufficient element isolation, and cannot improve the data retention characteristics of the cell transistors Tr1 and Tr2 and increase the current. Have the problem of

  The present invention is intended to provide a semiconductor device and a method for manufacturing the same that are effective in solving such problems.

  According to an aspect of the present invention, an element isolation region is formed on a semiconductor substrate, an active region made of the semiconductor substrate surrounded by the element isolation region is formed, and the semiconductor substrate is etched and embedded Forming a dummy word line groove and a buried word line groove; forming a first gate insulating film for a parasitic transistor in the buried dummy word line groove; and Forming a second gate insulating film for the memory cell transistor in the trench, wherein the film thickness of the first gate insulating film is made larger than the film thickness of the second gate insulating film. A method for manufacturing a semiconductor device is provided. The thickness of the first gate insulating film is larger than the thickness of the second gate insulating film because the semiconductor substrate includes the buried dummy word line trench and the buried word line trench. Forming the first gate insulating film for the parasitic transistor on the active region, and leaving the first gate insulating film for the parasitic transistor and covering the trench for the buried word line Removing the first gate insulating film; and forming the second gate insulating film for the memory cell transistor in the trench for the buried word line after removing the first gate insulating film; , Can be realized.

  According to another aspect of the present invention, a semiconductor substrate, two adjacent embedded word lines formed on the semiconductor substrate so as to extend in parallel to each other, and the two embedded word lines interposed therebetween Embedded dummy word lines formed on the semiconductor substrate so as to extend in parallel with the buried word lines on both sides, respectively, and the buried dummy word lines are for forming parasitic transistors. Formed through a first gate insulating film at the bottom of a trench for a buried dummy word line formed in the semiconductor substrate, the buried word line is for forming a memory cell transistor, and is formed on the semiconductor substrate. The second gate insulating film is formed at the bottom of the formed buried word line trench, and the thickness of the first gate insulating film is the second gate insulating film. Wherein a greater than the thickness of the membrane is provided.

  According to the present invention, the thickness of the first gate insulating film formed in the buried dummy word line trench is configured to be larger than that of the second gate insulating film formed in the buried word line trench. Therefore, the threshold voltage at which the dummy word line parasitic transistor is turned on becomes high, and the parasitic transistor is not turned on even if the voltage supplied is set higher than that of the memory cell transistor. Thereby, the data retention characteristics of the memory cell transistor can be improved and the current can be increased.

It is a top view which shows the memory cell of DRAM as a semiconductor device by embodiment of this invention. It is AA sectional drawing of FIG. 1, and shows the structure at the time of completion | finish of capacitor formation. FIG. 3 is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 1 and FIG. FIG. 4 is a cross-sectional view for explaining a step following the step in FIG. 3. FIG. 5 is a cross-sectional view for explaining a step following the step in FIG. 4. FIG. 6 is a cross-sectional view for explaining a step following the step in FIG. 5. FIG. 7 is a cross-sectional view for explaining a step following the step in FIG. 6. FIG. 8 is a cross-sectional view for explaining a step following the step in FIG. 7. FIG. 9 is a cross-sectional view for explaining a step following the step in FIG. 8. 1 is a plan view showing a memory cell of a DRAM as an example of a semiconductor device. It is BB sectional drawing of FIG. 10, and shows the structure at the time of completion | finish of capacitor formation.

Example 1
With reference to FIGS. 1-9, the manufacturing method of the semiconductor device 10 by embodiment of this invention is demonstrated. FIG. 1 is a plan view showing a memory cell of a DRAM as the semiconductor device 10. FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1 and shows the structure at the time when the formation of the capacitor is completed. In FIG. 1 and FIG. 2, the same reference numerals are given to the same elements as those in FIG. 10 and FIG. 3 to 9 sequentially show the manufacturing steps of the main part of the semiconductor device 10 in cross-sectional views.

  In FIG. 1, a semiconductor device 10 constitutes a DRAM memory cell. In FIG. 1, an X ′ direction that forms an angle with the X direction in the XY plane on the semiconductor substrate is set. On a semiconductor (silicon) substrate 11 (FIG. 2), element isolation regions 12 extending continuously in the X ′ direction and active regions 13 extending continuously in the X ′ direction alternately in the Y direction. A plurality are arranged at equal intervals and at equal pitches. The element isolation region 12 is composed of an element isolation insulating film embedded in the trench. In FIG. 1, a first embedded word line (hereinafter referred to as a first word line) WL1 and a second embedded word extending continuously in the Y direction across a plurality of element isolation regions 12 and a plurality of active regions 13. A line (hereinafter referred to as a second word line) WL2 and a third embedded word line (hereinafter referred to as a third word line) WL3 are arranged.

  Also, a first embedded dummy word line (hereinafter referred to as a first dummy word line) DWL1 and a second embedded dummy word line (hereinafter referred to as a second dummy word line) sandwiching the first word line WL1 and the second word line WL2. DWL2 is arranged. Each dummy word line DWL is configured in the same structure as each word line WL, but the continuous band-shaped active region 13 is divided into a plurality of independent active regions by keeping the parasitic transistors DTr1 and DTr2 in an off state. It has the function to do. Specifically, the active region 13 located between the first dummy word line DWL1 and the second dummy word line DWL2 becomes the first active region 13a, and the active region 13 located on the right side of the second dummy word line DWL2 is the first active region 13a. 2 active region 13b.

  The first active region 13a includes a first capacitor contact region 27a disposed adjacent to the first dummy word line DWL1, a first word line WL1 disposed adjacent to the first capacitor contact region 27a, and a first A first BL contact region 22a disposed adjacent to the word line WL1, a second word line WL2 disposed adjacent to the first BL contact region 22a, and a second disposed adjacent to the second word line WL2. And a capacitor contact region 27c.

  The first capacitor contact region 27a, the first word line WL1, and the first BL contact region 22a constitute a first cell transistor Tr1, and the first BL contact region 22a, the second word line WL2, and the second capacitor contact. The second cell transistor Tr2 is configured by the region 27c.

  In the above configuration, the width D in the X direction of each of the first dummy word line DWL1, the first word line WL1, the second word line WL2, and the second dummy word line DWL2, the first capacitance contact region 27a, and the first BL The width W in the X direction of each of the contact region 22a, the second capacitor contact region 27c, and the third capacitor contact region 27e has the same value.

  The memory cell of this embodiment is configured by arranging a plurality of the configurations of the first active region 13a in the X ′ direction via the dummy word line DWL.

  The second dummy word line DWL2 has a function of electrically isolating the capacitor contact regions constituting the two cell transistors arranged adjacent to each other. That is, the second dummy word line DWL2 is located at a position sandwiched between the second capacitor contact region 27c constituting the second cell transistor Tr2 and the third capacitor contact region 27e constituting the third cell transistor Tr3. It becomes the composition arranged. Therefore, the second dummy word line DWL2 electrically isolates the capacitive contact regions (27c, 27e) constituting the two cell transistors arranged adjacent to each other by keeping the parasitic transistor DTr2 in the off state. It has a function. The first dummy word line DWL1, the first word line WL1, the second word line WL2, the second dummy word line DWL2, and the third word line WL3 each have a center line in the Y direction passing through the center point in the X direction. These center lines are arranged at equal pitch intervals.

  Next, description will be made with reference to the sectional view of FIG. The semiconductor substrate 11 is provided with a trench 14b for a word line that also serves as a gate electrode of the transistor. Further, a dummy word line groove 14a is provided between the cell transistors adjacent to each other in the extending direction of each active region 13 to keep the parasitic transistor in an off state to isolate the element. The first dummy word line DWL1, the first word line WL1, the second word line WL2, the first dummy word line DWL1, the first word line WL2, the second word line WL2, the second word line WL2, and the second word line WL2, respectively. Two dummy word lines DWL2 and a third word line WL3 are provided at the bottom of each trench. The gate insulating film 15a covering the dummy word line trench 14a is thicker than the gate insulating film 15b covering the word line trench 14b.

  Further, a cap insulating film 17 is provided so as to cover the upper surface of each word line and each dummy word line and to bury each groove. The semiconductor pillar located between the first dummy word line DWL1 and the first word line WL1 serves as a first capacitor contact region 27a (FIG. 1), and an impurity diffusion layer 19a serving as one of source / drain is provided on the upper surface thereof. ing. The semiconductor pillar located between the first word line WL1 and the second word line WL2 becomes the first BL contact region 22a (FIG. 1), and the impurity diffusion layer 18 which is the other one of the source / drain is provided on the upper surface thereof. ing. The semiconductor pillar located between the second word line WL2 and the second dummy word line DWL2 serves as a second capacitor contact region 27c (FIG. 1), and an impurity diffusion layer 19b serving as one of source / drain is formed on the upper surface thereof. Is provided. Further, the semiconductor pillar located between the second dummy word line DWL2 and the third word line WL3 becomes the third capacitor contact region 27e, and an impurity diffusion layer 19c serving as one of the source / drain is provided on the upper surface thereof. .

  The impurity diffusion layer 19a, the gate insulating film 15b, the first word line WL1, and the impurity diffusion layer 18 constitute a first cell transistor Tr1 (FIG. 1). The impurity diffusion layer 18, the gate insulating film 15b, the second word line WL2, and the impurity diffusion layer 19b constitute a second cell transistor Tr2 (FIG. 1). Further, the impurity diffusion layer 19c, the gate insulating film 15b, the third word line WL3, and the impurity diffusion layer (not shown) constitute a third cell transistor Tr3 (FIG. 1).

  A first interlayer insulating film 21 is provided on the entire surface so as to cover the upper surface of the semiconductor substrate 11. On the first interlayer insulating film 21, a BL (bit line) 23a connected to the impurity diffusion layer 18 in the first BL contact region 22a (FIG. 1) is provided. A cover insulating film 23b is provided on the upper surface of the BL 23a. A liner insulating film 24 is provided on the entire surface so as to cover the side wall of the BL 23a. On the liner insulating film 24, an embedded insulating film 25 is provided to embed a recessed space formed between adjacent BLs. A second interlayer insulating film 26 is provided on the buried insulating film 25.

  Upper surfaces of the first, second, and third capacitor contact regions 27a, 27c, and 27e (FIG. 1) penetrating through the second interlayer insulating film 26, the buried insulating film 25, the liner insulating film 24, and the first interlayer insulating film 21. That is, first, second and third capacitor contact plugs 27b, 27d and 27f connected to the impurity diffusion layers 19a, 19b and 19c, respectively, are provided. A capacitor contact pad 28 is connected to the first, second, and third capacitor contact plugs 27b, 27d, and 27f. A third interlayer insulating film 29 is provided so as to cover the capacitor contact pad 28. A cylinder hole 30 is provided in the third interlayer insulating film 29 on the capacitor contact pad 28, and a lower electrode 31 is provided so as to cover the upper surface of the capacitor contact pad 28 and the inner surface of the cylinder hole 30. A capacitor insulating film 32 is provided so as to cover the inner surface of the lower electrode 31, and an upper electrode 33 is provided on the capacitor insulating film 32 to constitute a capacitor.

  In the semiconductor device described above, the first dummy word line DWL1 and the second dummy word line DWL2 are provided at the bottom of the groove 14a via the gate insulating film 15a covering the inner surface of the dummy word line groove 14a. The first word line WL1, the second word line WL2, and the third word line WL3 are provided at the bottom of the groove 14b through the gate insulating film 15b covering the inner surface of the word line groove 14b. In particular, the gate insulating film 15a is thicker than the gate insulating film 15b. Therefore, the threshold voltage at which the dummy word line parasitic transistors DTr1 and DTr2 (FIG. 1) are turned on increases, and the parasitic transistors DTr1 and DTr2 do not turn on even if the supplied voltage is set higher than the cell transistors Tr1 and Tr2. . Thereby, the data retention characteristics of the cell transistors Tr1 and Tr2 can be improved and the current can be increased.

  Next, a method for manufacturing the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 to 9 show AA cross-sectional views in FIG.

  First, an element isolation region embedded with an insulating film made of a silicon oxide film is formed on a semiconductor substrate by a well-known STI (Shallow Trench Isolation) method. Thus, an active region that is surrounded by the element isolation region and made of a semiconductor substrate is formed.

  Next, a pad oxide film 2 made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 11, and an N well region and a P well region are formed through the pad oxide film 2 by a known method. Thereafter, a silicon nitride film or the like is deposited on the semiconductor substrate 11, and a hard mask 3 for forming a dummy word line groove and a word line groove is patterned with a resist (not shown) (FIG. 3). .

  Next, as shown in FIG. 4, the semiconductor substrate 11 is etched by dry etching to form a dummy word line groove 14a and a word line groove 14b.

  Next, as shown in FIG. 5, a gate insulating film 15a for the parasitic transistors DTr1 and DTr2 is formed on the active region of the semiconductor substrate 11 by using a thermal oxidation and nitridation process or the like.

  Next, as shown in FIG. 6, the dummy word line groove 14a is masked with the resist 5, leaving the gate insulating film 15a for the parasitic transistors DTr1 and DTr2, and covering the word line groove 14b. The gate insulating film 15a is removed with a hydrofluoric acid-containing solution. Thereafter, the resist 5 is removed.

  Next, as shown in FIG. 7, the gate insulating film 15b for the cell transistors Tr1 and Tr2 is formed on the semiconductor substrate 11 after the gate insulating film 15a for the parasitic transistors DTr1 and DTr2 is removed with a hydrofluoric acid-containing solution. . At this time, the gate insulating film 15a for the parasitic transistors DTr1 and DTr2 is made thicker than the gate insulating film 15b for the cell transistors Tr1 and Tr2.

  Next, as shown in FIG. 8, tungsten or the like is deposited by, for example, CVD (Chemical Vapor deposition) and etched back to form dummy word lines DWL1 and DWL2 in the two grooves 14a, respectively. Word lines WL1, WL2, and WL3 are formed in the two grooves 14b, respectively. Then, although not shown, a liner insulating film is formed by, for example, a CVD method so as to cover the remaining tungsten and the inner walls of the dummy word line groove 14a and the word line groove 14b. . Subsequently, a buried insulating film 17 is deposited on the liner insulating film. Thereafter, CMP (Chemical Mechanical Polishing) is performed to planarize the surface until the liner insulating film is exposed, and then the silicon nitride film for mask and the buried insulating film 17 and a part of the liner insulating film are removed by etching. The surface of the buried insulating film 17 is set to be approximately the same height as the upper surface of the silicon pillar of the semiconductor substrate 11. Thereby, a buried word line and a buried wiring for element isolation are formed.

  Then, a silicon oxide film or the like is formed as the first interlayer insulating film 21 using, for example, a CVD method so as to cover the semiconductor substrate 11.

  Next, as shown in FIG. 9, by using a photolithography technique and a dry etching technique, a part of the first interlayer insulating film 21 is removed, and a bit contact connected to the upper surface of the first BL contact region 22a is formed. The bit contact is formed as a line-shaped opening pattern extending in the same direction as the word lines WL1, WL2, WL3 (Y direction in FIG. 1). At the intersection of the bit contact pattern and the active region, the surface of the semiconductor substrate 11 is exposed. After forming the bit contact, an N-type impurity (such as arsenic) is ion-implanted to form an N-type impurity diffusion layer in the vicinity of the silicon substrate surface. The formed N-type impurity diffusion layer functions as a source / drain region (impurity diffusion layer 18) of the transistor.

  Thereafter, a laminated film such as a polysilicon film, a tungsten film, or a silicon nitride film is formed by, for example, a CVD method. Then, a BL (bit line) 23a is formed by patterning into a line shape using a photolithography technique and a dry etching technique. The BL 23a is formed as a pattern extending in a direction intersecting the word lines WL1, WL2, WL3 (X direction in FIG. 1). The polysilicon film under the BL and the source / drain region (impurity diffusion layer 18) are connected to the surface portion of the silicon substrate exposed in the bit contact.

  Next, as shown in FIG. 2, after a silicon nitride film covering the side surface of the BL 23a is formed, a liner insulating film 24 covering the upper surface is formed of a silicon nitride film or the like by using, for example, a CVD method.

After depositing a SOD (Spin On Dielectric) film (embedded insulating film) 25 as a coating film so as to fill the space between the BLs, annealing is performed in a high-temperature steam (H ₂ O) atmosphere to obtain a solid The film is modified. After performing planarization by CMP until the upper surface of the liner insulating film 24 is exposed, a silicon oxide film formed by, for example, a CVD method is formed as the second interlayer insulating film 26 to cover the surface of the SOD film 25.

  Thereafter, the capacitor contact 27 is formed by using a photolithography technique and a dry etching technique. The surface of the silicon substrate is exposed at a portion where the capacitor contact 27 and the active region 13 (FIG. 1) intersect. Then, an N-type impurity (phosphorus or the like) is ion-implanted to form an N-type impurity diffusion layer near the surface of the active region 13. The formed N-type impurity diffusion layer functions as source / drain regions 19a, 19b, 19c of the transistor.

  Next, a conductive material such as tungsten is embedded using, for example, a CVD method so as to bury the inside of the capacitor contact 27. Subsequently, excess conductive material on the second interlayer insulating film 26 is removed by, for example, CMP, and capacitive contact plugs 27b, 27d, and 27f are formed with the conductive material left inside the capacitive contact. Next, after a wiring material layer such as tungsten is formed on the second interlayer insulating film 26, the wiring material layer is processed by a known lithography technique and etching technique, and a capacitor contact pad 28 connected to the capacitor contact plug is formed. Form.

  After a stopper film is formed using a silicon nitride film so as to cover the capacitor contact pad 28, a third interlayer insulating film 29 is formed using a silicon oxide film or the like.

  Thereafter, an opening (cylinder hole) 30 penetrating the third interlayer insulating film 29 and the silicon nitride film is formed so as to expose the upper surface of the capacitor contact pad 28, and then the capacitor is made of titanium nitride or the like so as to cover the inner wall of the opening. A lower electrode 31 of the element is formed. Subsequently, after forming the capacitive insulating film 32 so as to cover the surface of the lower electrode 31, the upper electrode 33 of the capacitor element is formed of titanium nitride or the like.

  Thereafter, although not shown, the wiring formation process is repeated to form a multilayer wiring, and the semiconductor device 10 is formed.

  In the embodiment of the semiconductor device manufacturing method, the first dummy word line DWL1 and the second dummy word line DWL2 are formed at the bottom of the groove 14a through the gate insulating film 15a covering the inner surface of the dummy word line groove 14a. Is provided. On the other hand, the first daward line WL1, the second word line WL2, and the third word line WL3 are provided at the bottom of the groove 14b via the gate insulating film 15b covering the inner surface of the word line groove 14b. In particular, the gate insulating film 15a is thicker than the gate insulating film 15b. For this reason, the threshold voltage at which the dummy word line parasitic transistors DTr1 and DTr2 are turned on is increased, and the parasitic transistors DTr1 and DTr2 are not turned on even if the supplied voltage is set higher than the cell transistors Tr1 and Tr2. Thereby, the data retention characteristics of the cell transistors Tr1 and Tr2 can be improved and the current can be increased.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the spirit and scope of the present invention described in the claims.

  The present invention is suitable for a DRAM using electrical element isolation using a buried word line structure.

DESCRIPTION OF SYMBOLS 10 Semiconductor device WL1, WL2, WL3 Embedded word line DWL1, DWL2 Embedded dummy word line BL23a Bit line 11 Semiconductor substrate 14a Embedded dummy word line groove 14b Embedded word line groove 15a, 15b Gate insulating films 18, 19a, 19b 19c Impurity diffusion layer

Claims (3)

Forming an element isolation region on the semiconductor substrate, and forming an active region made of the semiconductor substrate surrounded by the element isolation region;
Etching the semiconductor substrate to form a trench for a buried dummy word line and a trench for a buried word line;
Forming a first gate insulating film for a parasitic transistor in the trench for the buried dummy word line;
Forming a second gate insulating film for a memory cell transistor in the trench for the buried word line,
A method of manufacturing a semiconductor device, wherein the thickness of the first gate insulating film is made larger than the thickness of the second gate insulating film. In order to make the film thickness of the first gate insulating film thicker than the film thickness of the second gate insulating film,
Forming the first gate insulating film for the parasitic transistor on an active region of the semiconductor substrate including the trench for the buried dummy word line and the trench for the buried word line;
Leaving the first gate insulating film for the parasitic transistor and removing the first gate insulating film covering the trench for the buried word line;
The step of forming the second gate insulating film for the memory cell transistor in the trench for the buried word line after removing the first gate insulating film is performed. The manufacturing method of the semiconductor device as described in any one of. A semiconductor substrate;
Two adjacent embedded word lines formed on the semiconductor substrate so as to extend in parallel with each other;
Embedded dummy word lines formed on the semiconductor substrate so as to extend in parallel with the embedded word lines on both sides of the two embedded word lines, respectively,
The buried dummy word line is for forming a parasitic transistor, and is formed at the bottom of a trench for the buried dummy word line formed in the semiconductor substrate via a first gate insulating film,
The buried word line is for forming a memory cell transistor, and is formed at the bottom of a trench for a buried word line formed in the semiconductor substrate via a second gate insulating film,
The semiconductor device is characterized in that the film thickness of the first gate insulating film is larger than the film thickness of the second gate insulating film.

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