CN116648062A - Semiconductor device structure and preparation method - Google Patents
Semiconductor device structure and preparation method Download PDFInfo
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- CN116648062A CN116648062A CN202310815373.3A CN202310815373A CN116648062A CN 116648062 A CN116648062 A CN 116648062A CN 202310815373 A CN202310815373 A CN 202310815373A CN 116648062 A CN116648062 A CN 116648062A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 230000002093 peripheral effect Effects 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 35
- 238000011049 filling Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000006870 function Effects 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
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- 230000004888 barrier function Effects 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Abstract
The application discloses a semiconductor device structure and a preparation method thereof.A transistor is positioned in a peripheral circuit area and comprises a source electrode and a drain electrode; the word line groove is positioned in the substrate and penetrates through the adjacent first area and the second area of the substrate; the embedded grid word line is positioned in the word line groove; the embedded grid word line comprises a first conductive layer and a second conductive layer which are sequentially stacked, wherein the thickness of the first conductive layer positioned in the second area is larger than that of the first conductive layer positioned in the first area; the covering dielectric layer is positioned on the substrate of the second area and the peripheral circuit area; the first interconnection hole and the second interconnection hole are both positioned in the covering dielectric layer, the first interconnection hole exposes the second conductive layer positioned in the second area, and the second interconnection hole exposes the source electrode and the drain electrode of the transistor; the interconnection structure is positioned in the first interconnection hole and is contacted with the first conductive layer of the second area, so that the embedded grid word line can be smoothly and electrically led out, and the advantage of reducing grid leakage is maintained.
Description
The application date of the parent application of the division application is 2021, 07 and 08, the application number is 202110774378.7, and the name of the application is a semiconductor device structure and a preparation method.
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device structure and a preparation method thereof.
Background
With the rapid development of semiconductor memory technology, the market has placed higher demands on the memory capacity and functional size of semiconductor memory products. For the dynamic random access memory (Dynamic Random Access Memory, DRAM for short), as the power size of the DRAM is continuously scaled, the conductive layer of the novel hybrid embedded gate word line structure is prepared by utilizing two work function materials, so that the problem of gate induced drain leakage (Gate induced drain leakage, GIDL) caused by the embedded gate word line is reduced, and the performance of the transistor is improved.
However, when the conductive layer etched by the novel hybrid buried gate word line is etched, the etching rate of forming the interconnection hole is changed due to the conductive layer containing two work function materials, and the interconnection hole on the buried gate word line is not completely opened when the interconnection hole electrically led out by the buried gate word line is formed, so that the buried gate word line cannot be electrically connected with the peripheral circuit structure, and the performance of the DRAM is disabled.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor device structure and a manufacturing method for solving the problem that the interconnect hole on the novel hybrid buried gate word line including the conductive layers of two work function materials is not completely opened, so that the DRAM recovers performance while maintaining the advantage of reducing gate leakage.
In order to solve the above technical problems, a first aspect of the present application provides a semiconductor device structure, which includes a substrate, a transistor, a word line trench, a buried gate word line, a capping dielectric layer, a first interconnect hole, a second interconnect hole, and an interconnect structure: the substrate comprises a first area, a second area adjacent to the first area and a peripheral circuit area, wherein the substrate of the first area comprises a plurality of active areas which are arranged in an array manner and extend along a first direction; a transistor located in the peripheral circuit region, the transistor including a source and a drain; the word line groove is positioned in the substrate, penetrates through the first area and the second area, extends along the second direction and is oblique to the first direction; the embedded grid word line is positioned in the word line groove; the embedded grid word line comprises a first conductive layer and a second conductive layer, wherein the second conductive layer is positioned on the upper surface of the first conductive layer, and the thickness of the first conductive layer positioned in the second area is larger than that of the first conductive layer positioned in the first area; the covering dielectric layer is positioned on the substrate of the second area and the peripheral circuit area; the first interconnection hole and the second interconnection hole are respectively positioned in the second area and the covering dielectric layer of the peripheral circuit area, the first interconnection hole exposes the second conductive layer positioned in the second area, and the second interconnection hole exposes the source electrode and the drain electrode of the transistor; the interconnect structure is located within the first interconnect hole and is in contact with the first conductive layer of the second region.
In some embodiments, the work functions of the first conductive layer and the second conductive layer are different.
In some embodiments, the material of the first conductive layer includes arsenic or boron doped silicon, phosphorus or arsenic doped germanium, tungsten, titanium nitride or gold; the second conductive layer is made of polysilicon.
In some embodiments, the upper surface of the first conductive layer in the second region is higher than the upper surface of the first conductive layer in the first region.
In some embodiments, the first conductive layer is stepped.
In some embodiments, the second conductive layer has a thickness less than a difference in height between the first conductive layer in the first region and the upper surface of the first conductive layer in the second region.
In some embodiments, the buried gate word line further includes a fill dielectric layer on the second conductive layer and filling the word line trench, a top surface of the fill dielectric layer being flush with a top surface of the substrate.
In some embodiments, the semiconductor device structure further includes a plurality of bit lines arranged in parallel and spaced apart, the bit lines being located in the first region, and the bit lines extending along a third direction, the third direction intersecting both the first direction and the second direction.
In some embodiments, an upper surface of the second conductive layer is lower than a top surface of the word line trench.
In some embodiments, the second conductive layer does not cover an upper surface of the first conductive layer of the first region.
In some embodiments, the first conductive layer located in the second region is electrically connected to the transistors of the peripheral circuit region via the interconnect structure.
The second aspect of the present application provides a method for manufacturing a semiconductor device structure, including:
providing a substrate, wherein the substrate comprises a first area, a second area adjacent to the first area and a peripheral circuit area, and the substrate of the first area comprises a plurality of active areas which are arranged in an array manner and extend along a first direction;
forming a transistor in the peripheral circuit region, the transistor including a source and a drain;
forming word line grooves in the substrate, wherein the word line grooves penetrate through the first area and the second area;
forming a buried gate word line in the word line trench, wherein the buried gate word line comprises a first conductive layer and a second conductive layer, the second conductive layer is positioned on the upper surface of the first conductive layer, and the thickness of the first conductive layer positioned in the second region is larger than that of the first conductive layer positioned in the first region;
forming a covering dielectric layer on the substrate, wherein the covering dielectric layer covers the second area and the peripheral circuit area;
forming a first interconnection hole in the covering dielectric layer of the second region and forming a second interconnection hole in the covering dielectric layer of the peripheral circuit region at the same time, wherein the first interconnection hole exposes the first conductive layer positioned in the second region, and the second interconnection hole exposes the source electrode and the drain electrode of the transistor;
and forming an interconnection structure in the first interconnection hole, wherein the interconnection structure is contacted with the first conductive layer.
In some embodiments, forming a buried gate word line within a word line trench includes:
forming a first conductive layer in the word line groove, wherein the first conductive layer is in a step shape;
a second conductive layer is formed on the upper surface of the first conductive layer in the first region.
In some embodiments, forming the first conductive layer in the word line trench includes:
forming a first conductive material layer in the word line groove, wherein the first conductive material layer fills the word line groove and extends to the substrate;
and removing the first conductive material layer positioned on the substrate, and carrying out back etching on the first conductive material layer positioned in the first area to obtain a first conductive layer, wherein the upper surface of the first conductive layer positioned in the second area is higher than the upper surface of the first conductive layer positioned in the first area.
In some embodiments, etching back the first conductive material layer located in the first region includes:
forming a photoresist layer on the first conductive material layer positioned in the second area;
etching the first conductive material layer in the first area back based on the photoresist layer to obtain a first conductive layer;
and removing the photoresist layer.
In some embodiments, forming the second conductive layer on the upper surface of the first conductive layer in the first region includes:
forming a second conductive material layer on the upper surface of the first conductive layer, wherein the second conductive material covers the first region and the second region;
etching the second conductive material layer back so that the upper surface of the second conductive material layer is lower than the top surface of the word line groove, and the upper surface of the second conductive material layer in the second area is higher than the upper surface of the second conductive material layer in the first area;
forming a dielectric filling material layer on the upper surface of the reserved second conductive material layer;
and removing part of the filling medium material layer and removing the second conductive material layer positioned in the second area to obtain the filling medium layer and the second conductive layer, wherein the upper surface of the filling medium layer is flush with the upper surface of the first conductive layer positioned in the second area, and the thickness of the second conductive layer is smaller than the height difference between the first conductive layer positioned in the first area and the upper surface of the first conductive layer positioned in the second area.
In some embodiments, removing portions of the layer of fill dielectric material and removing the layer of second conductive material in the second region includes:
and flattening the dielectric material filling layer and the second conductive material layer along the thickness direction of the substrate by adopting a chemical mechanical polishing process or a horizontal pushing etching process until the first conductive layer positioned in the second area is exposed.
In the semiconductor device structure and the method for manufacturing the same provided in the above embodiments, the substrate includes a first region and a second region adjacent to the first region; forming word line grooves extending along the word line direction in the provided substrate, wherein the word line grooves penetrate through the first area and the second area; the embedded gate word line is formed in the word line groove and comprises a word line conducting layer, the word line conducting layer penetrates through the first area and the second area, the thickness of the word line conducting layer located in the second area is larger than that of the word line conducting layer located in the first area, the top surface of the word line conducting layer located in the second area is higher than that of the word line conducting layer located in the first area, a step-shaped word line conducting layer is formed, the first interconnection hole formed in the second area and used for electrically leading out the embedded gate word line can be ensured to expose the word line conducting layer after the embedded gate word line is manufactured, and therefore the embedded gate word line can be smoothly electrically led out, and the advantage of reducing gate leakage is reserved when a conducting path is provided for the DRAM.
The foregoing description is only an overview of the present application, and is intended to provide a better understanding of the present application, as it is embodied in the following description, with reference to the preferred embodiments of the present application and the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other embodiments of the drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device structure according to an embodiment of the present application;
FIGS. 2-3 are schematic diagrams illustrating structures obtained after forming word line trenches according to an embodiment of the present application; fig. 2 is a top view of a structure obtained after forming a word line trench, fig. 3 is a schematic cross-sectional structure of fig. 2, fig. 3 (a) is a schematic partial cross-sectional structure taken along the direction AA 'in fig. 2, and fig. 3 (b) is a schematic partial cross-sectional structure taken along the direction BB' in fig. 2;
fig. 4 is a schematic structural diagram of a structure obtained after forming a gate oxide layer according to an embodiment of the present application, in which fig. 4 is a schematic structural diagram of a cross-section of fig. 2, fig. 4 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 4 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
fig. 5 is a schematic structural diagram of a structure obtained after forming a metal barrier material layer according to an embodiment of the present application, wherein fig. 5 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 5 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
fig. 6 is a schematic structural diagram of a structure obtained after forming a first conductive material layer according to an embodiment of the present application, in which fig. 6 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 6 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
fig. 7 is a schematic structural diagram of a structure obtained after forming a photoresist layer on a second conductive material layer located in a second area according to an embodiment of the present application, wherein fig. 7 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 7 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
fig. 8 is a schematic structural diagram of a photoresist layer removal portion-based first conductive material layer and a metal barrier material layer according to an embodiment of the present application, where fig. 8 (a) is a schematic structural diagram of a partial cross-section taken along the AA 'direction in fig. 2, and fig. 8 (b) is a schematic structural diagram of a partial cross-section taken along the BB' direction in fig. 2;
FIG. 9 is a schematic structural diagram of a structure obtained by removing a photoresist layer according to an embodiment of the present application, wherein FIG. 9 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in FIG. 2, and FIG. 9 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in FIG. 2;
fig. 10 is a schematic structural diagram of a structure obtained after forming a second conductive material layer according to an embodiment of the present application, in which fig. 10 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 10 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
fig. 11 is a schematic structural diagram of a structure obtained after etching back the second conductive material layer according to an embodiment of the present application, in which fig. 11 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 11 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
fig. 12 is a schematic structural diagram of a structure obtained after forming a dielectric filling material layer according to an embodiment of the present application, in which fig. 12 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 12 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
fig. 13 is a schematic structural diagram of a structure obtained by removing a portion of the dielectric material layer and a portion of the second conductive material layer according to an embodiment of the present application, in which fig. 13 (a) is a schematic structural diagram of a partial cross-section taken along the direction AA 'in fig. 2, and fig. 13 (b) is a schematic structural diagram of a partial cross-section taken along the direction BB' in fig. 2;
FIG. 14 is a schematic view of a partial cross-sectional structure taken along the BB' direction in FIG. 2 of a structure obtained after forming bit lines and a capping dielectric layer according to an embodiment of the present application;
fig. 15 is a schematic structural diagram of a structure obtained after forming the first interconnect hole according to an embodiment of the present application, in which fig. 15 (a) is a schematic structural diagram of a partial cross-section taken along the BB' direction in fig. 2, and fig. 15 (b) is a schematic structural diagram of a cross-section of the peripheral circuit region.
Reference numerals illustrate: 10-substrate, 11-shallow trench isolation structure, 12-active region, 13-word line trench;
20-buried gate word lines, 21-gate oxide, 22-metal barrier, 221-metal barrier material layers;
23-word line conductive layer, 231-first conductive layer, 2311-first conductive material layer, 232-second conductive layer, 2321-second conductive material layer;
24-a layer of fill dielectric, 241-a layer of fill dielectric material;
30-bit line, 31-first bit line conductive layer, 32-second bit line conductive layer, 33-bit line insulating layer;
40-capping dielectric layer, 41-first capping dielectric layer, 42-second capping dielectric layer, 50-first interconnect hole, 51-photoresist layer, 60-second interconnect hole.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
In the process of preparing the novel hybrid embedded grid word line with the interconnection holes in the prior art, in order to prevent the problem that the interconnection holes are not opened, the etching rate for preparing the interconnection holes can be improved; however, when the etching rate is increased, the etching depth of the interconnection holes on the peripheral circuit is increased, so that the problem of MOS transistor junction leakage occurs in the performance of the device. Therefore, the application provides a semiconductor device structure and a preparation method thereof, solves the problem that an interconnection hole is not completely opened due to two work function materials, and avoids the factor that junction leakage of an MOS tube is likely to occur.
In one embodiment of the present application, as shown in fig. 1, a method for manufacturing a semiconductor device structure is provided, including the following steps:
step S10: providing a substrate, wherein the substrate comprises a first area and a second area adjacent to the first area;
step S20: forming word line grooves in the substrate, wherein the word line grooves penetrate through the first area and the second area;
step S30: and forming a buried gate word line in the word line groove, wherein the gate word line comprises a word line conducting layer, the word line conducting layer penetrates through the first area and the second area, and the thickness of the word line conducting layer positioned in the second area is larger than that of the word line conducting layer positioned in the first area.
In the method for manufacturing a semiconductor device structure provided in the above embodiment, the substrate includes a first region and a second region adjacent to the first region; forming word line trenches in the provided substrate, wherein the word line trenches penetrate through the first region and the second region; the embedded gate word line is formed in the word line groove and comprises a word line conducting layer, the word line conducting layer penetrates through the first area and the second area, the thickness of the word line conducting layer located in the second area is larger than that of the word line conducting layer located in the first area, the top surface of the word line conducting layer located in the second area is higher than that of the word line conducting layer located in the first area, a step-shaped word line conducting layer is formed, the first interconnection hole formed in the second area and used for electrically leading out the embedded gate word line can be ensured to expose the word line conducting layer after the embedded gate word line is manufactured, and therefore the embedded gate word line can be smoothly electrically led out, and the advantage of reducing gate leakage is reserved when a conducting path is provided for the DRAM.
In one embodiment, as shown in fig. 2 and 3, a plurality of shallow trench isolation structures 11 are formed in the substrate 10 provided in step S10, and the shallow trench isolation structures 11 isolate a plurality of active regions 12 arranged in an array in the substrate 10; the active region 12 extends in a first direction, and the word line trench 13 formed in the substrate 10 in step S20 extends in a second direction, which is oblique to the first direction.
As an example, the material of the shallow trench isolation structure 11 may include, but is not limited to, silicon oxide, silicon nitride, and the like; the substrate 11 may include, but is not limited to, a silicon substrate. The first direction and the second direction have an included angle of greater than 0 ° and less than or equal to 90 °, for example, the included angle of the first direction and the second direction may be 10 °, 20 °, 30 °, 45 °,50 °,60 °, 70 ° or 80 °, etc.
For the sake of clarity of the description of the embodiments of the application, the subsequent schematic cross-sectional views are taken along the AA 'and BB' directions in fig. 2, and the corresponding top views are not based on the top views of fig. 2.
In one embodiment, step S30: forming the buried gate word line 20 in the word line trench 13 includes the steps of:
step S31: forming a gate oxide layer 21 on the bottom and side walls of the word line trench 13 as shown in fig. 4;
step S32: forming a metal barrier material layer 221 on the surface of the gate oxide layer 13 and the substrate 10, as shown in fig. 5;
step S33: forming a first conductive material layer 2311 on the surface of the metal barrier material layer 221, wherein the first conductive material layer 2311 fills the word line trench 13 and extends onto the substrate 10, as shown in fig. 6;
step S34: removing the first conductive material layer 2311 located on the substrate 10 and the metal barrier material layer 221 located on the substrate, and performing back etching on the first conductive material layer 2311 located in the first area a and the metal barrier material layer 221 located in the first area a to obtain a metal barrier layer 22 and a first conductive layer 231, as shown in fig. 9; the upper surface of the metal barrier layer 22 located in the first area a and the upper surface of the first conductive layer 231 located in the first area a are lower than the upper surface of the substrate 10, and the upper surface of the first conductive layer 231 located in the second area B is higher than the upper surface of the first conductive layer 231 located in the first area a, i.e. the thickness of the first conductive layer 231 located in the second area B is greater than the thickness of the first conductive layer 231 located in the second area B, and the first conductive layer 231 is in a step shape, so that the first conductive layer 231 located in the second area B can be penetrated without changing the etching rate when preparing the first interconnection hole, and is communicated with the MOS transistor structure of the peripheral circuit through the interconnection structure (not shown in the figure).
Specifically, as shown in fig. 7 to 9, a photoresist layer 51 is formed on the first conductive material layer 2311 located in the second region B, and the photoresist layer 51 is removed after the first conductive material layer 2311 and the metal barrier material layer 221 are etched back based on the photoresist layer 51 to obtain the metal barrier layer 22 and the first conductive layer 231.
Step S35: a filling dielectric layer 24 is formed on the first conductive layer 231, and the filling dielectric layer 24 fills the word line trench 13.
As an example, the material of the gate oxide layer 21 may include, but is not limited to, silicon oxide or silicon nitride, and the gate oxide layer 21 may be formed using an atomic layer deposition process, a plasma vapor deposition process (Chemical Vapor Deposition, CVD), or a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO). The material of the metal barrier layer 22 may include, but is not limited to, silicon oxide, silicon nitride or silicon oxynitride; the material of the first conductive layer 231 may include, but is not limited to, as (arsenic) or B (boron) doped silicon, P (phosphorus) or As doped germanium, W (tungsten), ti (titanium), tiN (titanium nitride) or Au (gold).
In one embodiment, step S34: after forming the first conductive layer 231, and in step S35: the step of forming the filling dielectric layer 24 further includes:
step S341: forming a second conductive material layer 2321 on the upper surface of the first conductive layer 231, where the second conductive material covers the first region a and the second region B, as shown in fig. 10;
step S342: the second conductive material layer 2321 is etched back such that the upper surface of the second conductive material layer 2321 is lower than the upper surface of the word line trench 13, as shown in fig. 11. The second conductive material layer 2321 remaining after the etching again has a step shape, and an upper surface of the second conductive material layer 2321 located in the second area B is higher than an upper surface of the second conductive material layer 2321 located in the first area a.
In one embodiment, step S35: forming the fill dielectric layer 24 includes the steps of:
step S351: forming a filling dielectric material layer 241 on the upper surface of the remaining second conductive material layer 2321, as shown in fig. 12;
step S352: a portion of the filling dielectric material layer 241 is removed such that an upper surface of the remaining filling dielectric material layer 241 is flush with an upper surface of the first conductive layer 231 located at the second region B, as shown in fig. 13.
Specifically, removing the portion of the filling dielectric material layer 241 includes: the second conductive material layer 2321 located in the second region B is removed, so as to obtain the second conductive layer 232. The filling dielectric material layer 241 and the second conductive material layer 2321 may be planarized in the thickness direction by a chemical mechanical polishing process or a horizontal pushing etching process until the first conductive layer 231 located in the second region B is exposed. The upper surface of the filling dielectric layer 24 is flush with the upper surface of the substrate 10, the upper surface of the first conductive layer 231 in the second region B, and the upper surface of the word line trench 13. The first conductive layer 231 and the second conductive layer 232 have different work functions.
In one embodiment, please continue to refer to fig. 13, the thickness of the second conductive layer 232 is smaller than the difference between the height of the upper surface of the first conductive layer 231 located in the first region a and the height of the upper surface of the first conductive layer 231 located in the second region B; the second conductive layer 232 and the first conductive layer 231 together constitute the word line conductive layer 23.
By way of example, the material of the fill dielectric layer 24 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like. The material of the second conductive layer 232 may include, but is not limited to, polysilicon; the material of the first conductive layer 231 is different from the material of the second conductive layer 232, and the work functions of the first conductive layer and the second conductive layer are different, so that leakage of the embedded gate word line is reduced, and the performance of the DRAM is improved.
In one embodiment, as shown in fig. 14 to 15, step S30: after forming the buried gate word line 20 in the word line trench 13, the method further comprises the steps of:
step S40: forming a cover dielectric layer 40 on the substrate 10, wherein the cover dielectric layer 40 covers at least the second region B;
step S50: forming a first interconnection hole 50 in the cover medium 40 of the second region B, wherein the first interconnection hole 50 exposes the word line conductive layer 23 in the second region B;
step S60: an interconnect structure (not shown) is formed in the first interconnect hole 50, the interconnect structure being in contact with the word line conductive layer 23.
It should be noted that, the cover dielectric layer 40 also covers the first area a and the peripheral circuit area, the bit line 30 is also formed in the cover dielectric layer 40 located in the first area a, and the transistor (not shown) is also formed in the cover dielectric layer 40 located in the peripheral circuit area; forming a first interconnection hole 50 in the cover dielectric 40 of the second region B and forming a second interconnection hole 60 in the cover dielectric layer 40 located in the peripheral circuit region; the second interconnect hole 60 in the peripheral circuit region shown in fig. 15 (b) is prepared simultaneously with the first interconnect hole 50 in fig. 15 (a), and the first interconnect hole 50 and the second interconnect hole 60 have the same depth. The second interconnection hole 60 in the peripheral circuit region exposes the source S and drain D in the substrate 10.
Specifically, the bit line 30 extends along a third direction that intersects both the first direction and the second direction.
As an example, step S40: forming the blanket dielectric layer 40 over the substrate 10 includes the steps of:
step S41: forming a first dielectric layer 41 on the substrate 10, wherein the first dielectric layer 41 covers the first area a and the second area B;
step S42: forming an opening in the first capping dielectric layer 41, the opening exposing a portion of the first region a;
step S43: forming a plurality of bit lines 30 in the opening, wherein the bit lines are arranged in parallel at intervals;
step S44: forming a second covering dielectric layer 42, wherein the second covering dielectric layer 42 is positioned on the upper surface of the first covering dielectric layer 41 and fills up the gaps between the adjacent bit lines 30; the second capping dielectric layer 42 and the first capping dielectric layer 41 together constitute a capping dielectric layer 40. Thus, the preparation of the semiconductor device structure is completed.
Specifically, the bit line 30 includes a first bit line conductive layer 31, a second bit line conductive layer 32, and a bit line insulating layer 33 stacked in this order from bottom to top. The material of the first bit line conductive layer 31 may include, but is not limited to, polysilicon, metal tungsten, metal copper, or the like; the material of the second bit line conductive layer 32 may include, but is not limited to, W, ti, al (aluminum), or Pt (platinum), and the material of the first bit line conductive layer 31 is different from the material of the second bit line conductive layer 32; the material of the bit line insulating layer 33 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like. The material of the first capping dielectric layer 41 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like; the material of the second capping dielectric layer 42 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like.
Since the thickness of the word line conductive layer 23 in the second region B is greater than that of the word line conductive layer 23 in the first region a in the semiconductor device structure prepared in this embodiment, so as to form the step-shaped word line conductive layer 23, in the process of simultaneously forming the first interconnection hole 50 and the second interconnection hole 60, it is ensured that the first interconnection hole 50 can expose the word line conductive layer 23, thereby ensuring that the buried gate word line 20 can be electrically led out smoothly, providing a conductive path for the DRAM, and also retaining the advantage of reducing gate leakage.
In another embodiment of the present application, as shown in fig. 15, there is further provided a semiconductor device structure, which is prepared based on the preparation method of the semiconductor device structure as above, and the semiconductor device structure includes: a substrate 10, a word line trench 13 and a buried gate word line 20. The substrate 10 includes a first region a and a second region B adjacent to the first region a; the word line groove 13 is positioned in the substrate 10, and the word line groove 13 penetrates through the first area A and the second area B; the buried gate word line 20 includes a word line conductive layer 23, the word line conductive layer 23 penetrates through the first area a and the second area B, and the thickness of the word line conductive layer 23 located in the second area a is greater than that of the word line conductive layer 23 located in the first area a, so as to form a step-shaped word line conductive layer, after the preparation of the buried gate word line 20 is completed, it is ensured that the first interconnection hole 20 for electrical extraction of the buried gate word line formed in the second area B can expose the word line conductive layer 23, thereby ensuring that the buried gate word line 20 can be electrically extracted smoothly, and maintaining the advantage of reducing gate leakage while providing a conductive path for the DRAM.
In one embodiment, the buried gate word line 20 further includes a gate oxide layer 21, a metal barrier layer 22, a first conductive layer 231, and a filling dielectric layer 24, where the gate oxide layer 21 is located at the bottom and sidewalls of the word line trench 13; the metal barrier layer 22 is positioned on the surface of part of the gate oxide layer 21; the first conductive layer 231 is located on the surface of the metal barrier layer 22 and fills part of the word line trench 13; the upper surface of the metal barrier layer 22 located in the first region a and the upper surface of the first conductive layer 231 located in the first region a are lower than the upper surface of the substrate 10, and the upper surface of the first conductive layer 231 located in the second region B is higher than the upper surface of the first conductive layer 231 located in the first region a; a fill dielectric layer 24 is on the first conductive layer 231 and fills the wordline trenches 13. The upper surface of the filling dielectric layer 24 is flush with the upper surface of the substrate 10 and the upper surface of the first conductive layer 231 in the second region B.
In one embodiment, the buried gate word line 20 further includes a second conductive layer 232, the second conductive layer 232 being located on a surface of the a first conductive layer 231 of the first region; the filling medium layer 24 is located on the surface of the second conductive layer 232.
In one embodiment, the thickness of the second conductive layer 232 is smaller than the difference in height between the upper surface of the first conductive layer 231 located in the first region a and the first conductive layer 231 located in the second region B; the second conductive layer 232 and the first conductive layer 231 together constitute the word line conductive layer 23.
In one embodiment, the semiconductor device structure further comprises: covering the dielectric layer 40, the first interconnect hole 50, and the interconnect structure (not shown in fig. 15 (a)). A capping dielectric layer 40 is located on the substrate 10, the capping dielectric layer 40 covering at least the second region B; the first interconnection hole 50 is located in the covering dielectric layer 40 of the second region B, and the first interconnection hole 50 exposes the word line conductive layer 23 located in the second region B; the interconnect structure fills the first interconnect hole 50 and contacts the word line conductive layer 50.
In one embodiment, the capping dielectric layer 40 includes a first capping dielectric layer 41 and a second capping dielectric layer 42; an opening (not shown in fig. 14) is formed in the first covering dielectric layer 41, the opening exposes the first region, a plurality of bit lines 30 arranged in parallel at intervals are formed in the opening, the bit lines 30 extend along a third direction, and the third direction intersects with the first direction and the second direction; the second dielectric layer 42 is located on the upper surface of the first dielectric layer 41 and fills the gaps between adjacent bit lines 30.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present application.
It should be understood that the steps described are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps described may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
Claims (17)
1. A semiconductor device structure, comprising:
the substrate comprises a first area, a second area adjacent to the first area and a peripheral circuit area, wherein the substrate of the first area comprises a plurality of active areas which are arranged in an array, and the active areas extend along a first direction;
a transistor located in the peripheral circuit region, the transistor including a source and a drain;
a word line trench within the substrate, the word line trench extending through the first region and the second region, the word line trench extending along a second direction, the second direction being oblique to the first direction;
a buried gate word line in the word line trench;
the embedded grid word line comprises a first conductive layer and a second conductive layer, wherein the second conductive layer is positioned on the upper surface of the first conductive layer, and the thickness of the first conductive layer positioned in the second area is larger than that of the first conductive layer positioned in the first area;
a cover dielectric layer on the substrate in the second region and the peripheral circuit region;
a first interconnect hole and a second interconnect hole respectively located in the second region and the cover dielectric layer of the peripheral circuit region, the first interconnect hole exposing the second conductive layer located in the second region, the second interconnect hole exposing the source and drain of the transistor;
an interconnect structure is located within the first interconnect hole and is in contact with the first conductive layer of the second region.
2. The semiconductor device structure of claim 1, wherein,
the first conductive layer and the second conductive layer have different work functions.
3. The semiconductor device structure of claim 2, wherein,
the material of the first conductive layer comprises arsenic or boron doped silicon, phosphorus or arsenic doped germanium, tungsten, titanium nitride or gold; the second conductive layer is made of polysilicon.
4. The semiconductor device structure of claim 1, wherein,
an upper surface of the first conductive layer located in the second region is higher than an upper surface of the first conductive layer located in the first region.
5. The semiconductor device structure of claim 4, wherein,
the first conductive layer is in a step shape.
6. The semiconductor device structure of claim 4, wherein,
the thickness of the second conductive layer is smaller than the height difference between the first conductive layer located in the first area and the upper surface of the first conductive layer located in the second area.
7. The semiconductor device structure of claim 1, wherein,
the buried gate word line further includes a fill dielectric layer on the second conductive layer and filling the word line trench, a top surface of the fill dielectric layer being flush with a top surface of the substrate.
8. The semiconductor device structure of claim 1, further comprising:
the bit lines are arranged in parallel at intervals and located in the first area, extend along a third direction, and intersect with the first direction and the second direction.
9. The structure of claim 1, wherein,
an upper surface of the second conductive layer is lower than a top surface of the word line trench.
10. The structure of a semiconductor device according to any of claims 1-9, wherein,
the second conductive layer does not cover an upper surface of the first conductive layer of the first region.
11. The structure of a semiconductor device according to any of claims 1-9, wherein,
the first conductive layer located in the second region is electrically connected with the transistor of the peripheral circuit region via the interconnection structure.
12. A method of fabricating a semiconductor device structure, comprising:
providing a substrate, wherein the substrate comprises a first area, a second area adjacent to the first area and a peripheral circuit area, the substrate of the first area comprises a plurality of active areas which are arranged in an array, and the active areas extend along a first direction;
forming a transistor in the peripheral circuit region, the transistor including a source and a drain;
forming a word line trench in the substrate, the word line trench penetrating through the first region and the second region;
forming a buried gate word line in the word line trench, wherein the buried gate word line comprises a first conductive layer and a second conductive layer, the second conductive layer is positioned on the upper surface of the first conductive layer, and the thickness of the first conductive layer positioned in the second region is larger than that of the first conductive layer positioned in the first region;
forming a covering dielectric layer on the substrate, wherein the covering dielectric layer covers the second area and the peripheral circuit area;
forming a first interconnection hole in the covering dielectric layer of the second region and forming a second interconnection hole in the covering dielectric layer of the peripheral circuit region at the same time, wherein the first interconnection hole exposes the first conductive layer in the second region, and the second interconnection hole exposes the source electrode and the drain electrode of the transistor;
and forming an interconnection structure in the first interconnection hole, wherein the interconnection structure is contacted with the first conductive layer.
13. The method of manufacturing a semiconductor device structure of claim 12, wherein forming a buried gate wordline in the wordline trench comprises:
forming a first conductive layer in the word line groove, wherein the first conductive layer is in a step shape;
and forming a second conductive layer on the upper surface of the first conductive layer in the first region.
14. The method of claim 13, wherein forming a first conductive layer in the word line trench comprises:
forming a first conductive material layer in the word line trench, wherein the first conductive material layer fills the word line trench and extends onto the substrate;
and removing the first conductive material layer on the substrate, and carrying out back etching on the first conductive material layer in the first area to obtain the first conductive layer, wherein the upper surface of the first conductive layer in the second area is higher than the upper surface of the first conductive layer in the first area.
15. The method of manufacturing a semiconductor device structure of claim 14, wherein back etching the first conductive material layer in the first region comprises:
forming a photoresist layer on the first conductive material layer located in the second area;
etching back the first conductive material layer in the first area based on the photoresist layer to obtain the first conductive layer;
and removing the photoresist layer.
16. The method of claim 13, wherein forming a second conductive layer on the upper surface of the first conductive layer in the first region comprises:
forming a second conductive material layer on the upper surface of the first conductive layer, wherein the second conductive material covers the first area and the second area;
etching back the second conductive material layer so that the upper surface of the second conductive material layer is lower than the top surface of the word line trench and the upper surface of the second conductive material layer in the second region is higher than the upper surface of the second conductive material layer in the first region;
forming a dielectric filling material layer on the upper surface of the reserved second conductive material layer;
and removing part of the filling medium material layer and removing the second conductive material layer positioned in the second area to obtain a filling medium layer and a second conductive layer, wherein the upper surface of the filling medium layer is flush with the upper surface of the first conductive layer positioned in the second area, and the thickness of the second conductive layer is smaller than the height difference between the first conductive layer positioned in the first area and the upper surface of the first conductive layer positioned in the second area.
17. The method of manufacturing a semiconductor device structure of claim 16, wherein removing portions of the fill dielectric material layer and removing the second conductive material layer in the second region comprises:
and flattening the dielectric filling material layer and the second conductive material layer along the thickness direction of the substrate by adopting a chemical mechanical polishing process or a horizontal pushing etching process until the first conductive layer positioned in the second area is exposed.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492221B1 (en) * | 1998-09-30 | 2002-12-10 | Infineon, Ag | DRAM cell arrangement |
| US20070161179A1 (en) * | 2005-12-28 | 2007-07-12 | Nanya Technology Corporation | Semiconductor device and method for making the same |
| US20120091518A1 (en) * | 2010-10-13 | 2012-04-19 | Elpida Memory, Inc. | Semiconductor device, method for forming the same, and data processing system |
| US20120286358A1 (en) * | 2011-05-10 | 2012-11-15 | Elpida Memory, Inc. | Semiconductor device and method of forming the same |
| JP2013219179A (en) * | 2012-04-09 | 2013-10-24 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
| CN107134486A (en) * | 2017-04-28 | 2017-09-05 | 睿力集成电路有限公司 | Memory |
| CN108063140A (en) * | 2017-11-27 | 2018-05-22 | 睿力集成电路有限公司 | Transistor arrangement, memory cell array and preparation method thereof |
| CN207852674U (en) * | 2017-12-07 | 2018-09-11 | 睿力集成电路有限公司 | transistor and memory cell array |
| CN113035870A (en) * | 2021-03-01 | 2021-06-25 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1003219B1 (en) * | 1998-11-19 | 2011-12-28 | Qimonda AG | DRAM with stacked capacitor and buried word line |
| CN1264221C (en) * | 2003-04-28 | 2006-07-12 | 南亚科技股份有限公司 | Semiconductor structure reducing external diffusion of buried layer contact tape, method for making the same and forming method for semiconductor storage device |
| US20050014332A1 (en) * | 2003-07-15 | 2005-01-20 | Infineon Technologies North America Corp. | Method to improve bitline contact formation using a line mask |
| CN107910328B (en) * | 2017-12-12 | 2023-09-22 | 长鑫存储技术有限公司 | Method for manufacturing storage node contact in semiconductor device and semiconductor device |
| CN109065625A (en) * | 2018-07-25 | 2018-12-21 | 七色堇电子科技（上海）有限公司 | A kind of groove type MOS transistor, preparation method and the electronic device comprising it |
| KR102505229B1 (en) * | 2018-10-02 | 2023-03-06 | 삼성전자주식회사 | Semiconductor device and method of fabricating semiconductor device |
| CN209119102U (en) * | 2018-11-21 | 2019-07-16 | 长鑫存储技术有限公司 | Semiconductor devices |
-
2021
- 2021-07-08 CN CN202110774378.7A patent/CN113517232B/en active Active
- 2021-07-08 CN CN202310815388.XA patent/CN116867268A/en active Pending
- 2021-07-08 CN CN202310815373.3A patent/CN116648062A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492221B1 (en) * | 1998-09-30 | 2002-12-10 | Infineon, Ag | DRAM cell arrangement |
| US20070161179A1 (en) * | 2005-12-28 | 2007-07-12 | Nanya Technology Corporation | Semiconductor device and method for making the same |
| US20120091518A1 (en) * | 2010-10-13 | 2012-04-19 | Elpida Memory, Inc. | Semiconductor device, method for forming the same, and data processing system |
| US20120286358A1 (en) * | 2011-05-10 | 2012-11-15 | Elpida Memory, Inc. | Semiconductor device and method of forming the same |
| JP2013219179A (en) * | 2012-04-09 | 2013-10-24 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
| CN107134486A (en) * | 2017-04-28 | 2017-09-05 | 睿力集成电路有限公司 | Memory |
| CN108063140A (en) * | 2017-11-27 | 2018-05-22 | 睿力集成电路有限公司 | Transistor arrangement, memory cell array and preparation method thereof |
| CN207852674U (en) * | 2017-12-07 | 2018-09-11 | 睿力集成电路有限公司 | transistor and memory cell array |
| CN113035870A (en) * | 2021-03-01 | 2021-06-25 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
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