CN108063140A - Transistor arrangement, memory cell array and preparation method thereof - Google Patents
Transistor arrangement, memory cell array and preparation method thereof Download PDFInfo
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- CN108063140A CN108063140A CN201711206798.5A CN201711206798A CN108063140A CN 108063140 A CN108063140 A CN 108063140A CN 201711206798 A CN201711206798 A CN 201711206798A CN 108063140 A CN108063140 A CN 108063140A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of transistor arrangement, memory cell array and preparation method, and transistor preparation includes：The Semiconductor substrate with active area is provided, in forming groove structure in active area；Dielectric layer is formed in groove structure bottom and side wall；Wordline superficial layer is formed in dielectric layer bottom and partial sidewalls, and the wordline physical layer including being incorporated into the lug boss on the filling part of wordline surface layer surface and filling part top, wordline superficial layer top is less than Semiconductor substrate upper surface, lug boss top forms lateral sulcus higher than wordline superficial layer top and less than Semiconductor substrate upper surface between the lateral wall and dielectric layer of lug boss；Filling perforation insulating layer covers the top of wordline physical layer and the top of lateral sulcus, lateral sulcus is closed to form air chamber.Through the above scheme, the present invention prepares transistor arrangement by deposition and wet-etching technology, forms the transistor with insulation lateral sulcus, changes the middle dielectric layer of capacitance, so as to reduce parasitic capacitance, can also reduce the resistance of transistor.
Description
Technical field
The invention belongs to ic manufacturing technology field, more particularly to a kind of transistor arrangement and preparation method thereof.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer
Semiconductor storage unit, be made of the storage unit of many repetitions.Each storage unit is mainly by a transistor and one
A capacitor manipulated by transistor is formed, and storage unit can be arranged in array format, each storage unit passes through
Wordline is electrically connected to each other with bit line.As electronic product is increasingly towards light, thin, short, small development, dynamic random access memory
The design of component also have to comply with high integration, it is highdensity requirement towards miniaturization trend development, for improve dynamic with
Machine accesses the integration of memory to accelerate the service speed of component and meet need of the consumer for miniaturized electronic device
It asks, develops buried gate wordline dynamic random access memory in recent years, to meet above-mentioned a variety of demands.
However, in said structure, the parasitic capacitance in the presence of the transistor arrangement of memory still constructs device junction
Into very big influence, in addition, constantly reduce with the array of dynamic RAM, the resistance of the buried gate wordline by
It is cumulative to add, affect the final performance of device.
Therefore, how the memory cell array of a kind of transistor arrangement, storage unit and its composition and above-mentioned knot are provided
The preparation method of structure is necessary with solving the above problems.
The content of the invention
In view of the foregoing deficiencies of prior art, it is an object of the invention to provide a kind of transistor arrangement, storage are single
Element array and preparation method thereof, for solving asking for parasitic capacitance in the prior art in transistor and transistor circuit resistance
Topic.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of transistor arrangement, including
Step：
1) providing one has the Semiconductor substrate of active area, and in forming groove structure in the active area；
2) dielectric layer is formed in the bottom of the groove structure and side wall；
3) wordline superficial layer is formed in the bottom of the dielectric layer and partial sidewalls, and in the wordline surface layer surface shape
Into wordline physical layer, the wordline physical layer includes being incorporated into the filling part of wordline surface layer surface and positioned at the filling
Lug boss on portion top, wherein, the top of the wordline superficial layer is less than the upper surface of the Semiconductor substrate, the lug boss
Top of the top higher than the wordline superficial layer and the upper surface less than the Semiconductor substrate, and the outside of the lug boss
Lateral sulcus is formed between wall and the dielectric layer；And
4) in forming filling perforation insulating layer in the groove structure, the bottom of the filling perforation insulating layer covers the wordline entity
The top of layer and the top of the lateral sulcus, the lateral sulcus is closed to form air chamber.
As a preferred embodiment of the present invention, the thickness of the wordline superficial layer is between 0.8~5 nanometer, to limit
The width of the air chamber.
As a preferred embodiment of the present invention, in step 1), the size of the opening of the groove structure is between 10~50
Nanometer；In step 2), the thickness of the dielectric layer is between 1~9 nanometer；In step 4), the height of the air chamber is between 1~40
Nanometer.
As a preferred embodiment of the present invention, in step 1), the step of forming the groove structure, includes：
1-1) in the semiconductor substrate surface formed one layer have window mask layer, wherein, the window with it is described
Groove structure is corresponding up and down；And
1-2) Semiconductor substrate is performed etching based on the window, to form the groove structure.
As a preferred embodiment of the present invention, in step 2), the medium is formed using steam in situ (ISSG) technique
Layer.
As a preferred embodiment of the present invention, in step 3), step is further included：In the wordline superficial layer and the word
One layer of adhesion layer is formed between line physical layer.
As a preferred embodiment of the present invention, in step 3), the wordline superficial layer and the wordline physical layer are formed
The step of include：
3-1) the semiconductor substrate surface around the bottom of the groove structure, side wall and the groove structure
Form one layer of first conductive material layer；
3-2) one layer of second conductive material layer, second conductive material layer are formed in the first conductive material layer surface
The full groove structure of filling simultaneously extends over first conductive material layer on the semiconductor substrate surface；
3-3) first conductive material layer and second conductive material layer are performed etching, led with being respectively formed first
Electric material portion and the second conductive material part, top to the upper surface of the Semiconductor substrate of first conductive material part and institute
Top to the upper surface of the Semiconductor substrate for stating the second conductive material part all has the first spacing；And
3-4) first conductive material layer and second conductive material layer are continued by wet-etching technology
Etching, Yi Fen Do form the wordline superficial layer and the wordline physical layer, the wordline superficial layer and the Semiconductor substrate
Surface has the second spacing, and the wordline physical layer has the 3rd spacing, second spacing with the semiconductor substrate surface
More than the 3rd spacing, to define the height of the protrusion.
As a preferred embodiment of the present invention, first spacing is between 30~70 nanometers；Second spacing and institute
The difference of the 3rd spacing is stated between 1~40 nanometer.
As a preferred embodiment of the present invention, step 3-4) in, carrying out the reagent of the wet etching includes ammonium hydroxide
(NH4OH), hydrogen peroxide (H2O2) and water composition mixed liquor, wherein, the ratio of ammonium hydroxide, hydrogen peroxide and water in the mixed liquor
Example is sequentially 1 to 0.01~2 to 5~150.
As a preferred embodiment of the present invention, step 3-3) in, it is conductive to described first by the technique of alternately etching
Material layer and second conductive material layer perform etching, wherein, the etching gas of the alternately etching include sulfur hexafluoride, chlorine
Gas and argon gas form arbitrary two or three of combination in group.
As a preferred embodiment of the present invention, before step 4), step is further included：Using dilute hydrogen fluoride acid (DHF) reagent
The surface of the wordline physical layer is cleaned to remove surface by-product, the dilute hydrogen fluoride acid reagent includes hydrofluoric acid (HF)
With the mixed liquor of water, wherein, the ratio of hydrofluoric acid and water includes 1 to 50~1000.
As a preferred embodiment of the present invention, in step 2), the material of the dielectric layer includes silica, step 3)
In, the material of the wordline superficial layer includes titanium nitride, and in step 3), the material of the wordline physical layer includes tungsten, step 4)
In, the material of the filling perforation insulating layer includes silicon nitride.
As a preferred embodiment of the present invention, in step 4), the filling perforation is formed by atom layer deposition process and is insulated
Layer, so as to not destroy the air chamber.
As a preferred embodiment of the present invention, the deposition of the atom layer deposition process between 200~1000 nanometers/
Minute.
The present invention also provides a kind of preparation methods of memory cell array, comprise the following steps：
A) multiple storage units with transistor arrangement are formed, and each storage unit is configured as cell row and list
Member row, wherein, the transistor arrangement is prepared using the preparation method as described in above-mentioned any one scheme, the crystalline substance
Body pipe structure connects two capacitances without active area；And
B) the wordline physical layer of each storage unit in addressed line to the cell row or the cell columns is connected, with
Memory cell array is prepared, wherein, the addressed line is used to control the storage unit.
The present invention also provides a kind of transistor arrangement, including：
Semiconductor substrate has active area；
Groove structure, in the active area of the Semiconductor substrate；
Dielectric layer, positioned at the bottom of the groove structure and side wall；
Wordline superficial layer is less than positioned at the top of the bottom of the dielectric layer and partial sidewalls, and the wordline superficial layer
The upper surface of the Semiconductor substrate；
Wordline physical layer, positioned at wordline surface layer surface, including the filling part being incorporated into the wordline superficial layer
And the lug boss on the filling part top, the top of the lug boss are higher than the top of the wordline superficial layer and less than institute
The upper surface of Semiconductor substrate is stated, lateral sulcus is formed between the lateral wall of the lug boss and the dielectric layer；And
Filling perforation insulating layer is filled in the top of the groove structure, and the bottom of the filling perforation insulating layer covers the word
The top of line physical layer and the top of the lateral sulcus are located at the air chamber of the lug boss both sides to be formed.
As a preferred embodiment of the present invention, the thickness of the wordline superficial layer is between 0.8~5 nanometer, to limit
The width of the air chamber.
As a preferred embodiment of the present invention, the size of the opening of the groove structure is between 10~50 nanometers；It is described
The thickness of dielectric layer is between 1~9 nanometer；The height of the air chamber is between 1~40 nanometer.
As a preferred embodiment of the present invention, the material of the dielectric layer includes silica, the wordline superficial layer
Material includes titanium nitride, and the material of the wordline physical layer includes tungsten, and the material of the filling perforation insulating layer includes silicon nitride.
The present invention also provides a kind of memory cell array, including：
Several storage units, the storage unit include the transistor arrangement as described in above-mentioned any one scheme, and
Each memory cell arrangements respectively connect two electricity into cell row and cell columns, each active area of the transistor arrangement
Hold；And
Addressed line is connected to the wordline physical layer of each storage unit in the cell row or the cell columns, institute
Addressed line is stated for controlling the storage unit.
The present invention also provides a kind of memory construction, including the memory cell array as described in above-mentioned any one scheme.
As described above, the transistor arrangement of the present invention, memory cell array and preparation method thereof, have below beneficial to effect
Fruit：
The present invention prepares transistor arrangement by deposition and wet-etching technology, is formed a kind of with insulation lateral sulcus (void)
Transistor, in the case where the other parts of device architecture are identical, to insulate lateral sulcus part be compared, due to insulation sides
The presence of ditch makes original Conductive layer portions be changed into the air of insulation lateral sulcus, the middle dielectric layer of capacitance is changed, so as to drop
Low parasitic capacitance；In addition, technical solution using the present invention, it can also be ensured that increase while small leakage current as grid
The height of the metal layer of wordline, so as to reduce the resistance of transistor.
Description of the drawings
Fig. 1 is shown as the flow chart of the transistor arrangement preparation process of the present invention.
Fig. 2 is shown as providing the structure diagram of Semiconductor substrate in the transistor arrangement preparation of the present invention.
Fig. 3 is shown as the structure diagram of mask layer in the transistor arrangement preparation of the present invention.
Fig. 4 is shown as being formed the structure diagram of groove structure in the transistor arrangement preparation of the present invention.
Fig. 5 is shown as being formed the structure diagram of dielectric layer in the transistor arrangement preparation of the present invention.
Fig. 6 is shown as being formed the structure diagram of the first conductive material layer in the transistor arrangement preparation of the present invention.
Fig. 7 is shown as being formed the structure diagram of the second conductive material layer in the transistor arrangement preparation of the present invention.
Fig. 8 be shown as the present invention transistor arrangement prepare in the one the second conductive material layer showing to the first spacing of etching
It is intended to.
Fig. 9 is shown as being formed the structural representation of wordline superficial layer and wordline physical layer in the transistor arrangement preparation of the present invention
Figure.
Figure 10 is shown as being formed the structure diagram of filling perforation insulating layer in the transistor arrangement preparation of the present invention.
Figure 11 is shown with the schematic diagram of the storage unit connection of the transistor arrangement of the present invention.
Figure 12 is shown with the schematic diagram of the memory construction of the transistor arrangement of the present invention.
Figure 13 is shown as ringing present in existing device architecture.
Figure 14 (a) and Figure 14 (b) is shown as the prior art and the capacitance variations schematic diagram in the transistor arrangement of the present invention.
Figure 15 is shown as a kind of product schematic diagram of the transistor arrangement including the present invention.
Component label instructions
100 Semiconductor substrates
101 active areas
102 isolation structures
103 isolation structure filled layers
104 mask layers
105 windows
106 groove structures
107 dielectric layers
108 first conductive material layers
109 second conductive material layers
110 first conductive material parts
111 second conductive material parts
112 wordline superficial layers
113 wordline physical layers
1131 filling parts
1132 lug bosses
114 lateral sulcus
1141 air chambers
115 filling perforation insulating layers
116 capacitances
117 wordline
118 amplifiers
119 channel regions
120 shallow junction regions
121 doped drains
S1~S4 steps 1)~step 4)
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It please refers to Fig.1 to Figure 15.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though package count when only display is with related component in the present invention rather than according to actual implementation in diagram
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during actual implementation, and its
Assembly layout form may also be increasingly complex.
As shown in Figure 1, the present invention provides a kind of preparation method of transistor arrangement, include the following steps：
1) providing one has the Semiconductor substrate of active area, and in forming groove structure in the active area；
2) dielectric layer is formed in the bottom of the groove structure and side wall；
3) wordline superficial layer is formed in the bottom of the dielectric layer and partial sidewalls, and in the wordline surface layer surface shape
Into wordline physical layer, the wordline physical layer includes being incorporated into the filling part of wordline surface layer surface and positioned at the filling
The lug boss that portion is pushed up, wherein, the top of the wordline superficial layer is less than the upper surface of the Semiconductor substrate, the protrusion
Top of the top in portion higher than the wordline superficial layer and the upper surface less than the Semiconductor substrate, and the lug boss is outer
Lateral sulcus is formed between side wall and the dielectric layer；And
4) in forming filling perforation insulating layer in the groove structure, the bottom of the filling perforation insulating layer covers the wordline entity
The top of layer and the top of the lateral sulcus, the lateral sulcus is closed to form air chamber.
Below in conjunction with the preparation method of the attached drawing transistor arrangement that the present invention will be described in detail.
As shown in the S1 in Fig. 1 and Fig. 2~4, step 1) is carried out first, and a semiconductor with active area 101 is provided and is served as a contrast
Bottom 100, and in formation groove structure 106 in the active area 101；
Specifically, the present embodiment provides one first has the Semiconductor substrate 100 of active area 101, the Semiconductor substrate
100 material includes but not limited to monocrystalline or polycrystalline semiconductor material, furthermore it is also possible to be that intrinsic monocrystalline substrate is either light
The silicon substrate of micro- doping, further, it is possible to be N-type polycrystalline silicon substrate or p-type polysilicon substrate, in the present embodiment, described half
Conductor substrate 100 is the substrate of P+ type polycrystalline silicon material.
Wherein, in this example, the active area 101 is isolated structure 102 and separates, and the isolation structure 102 is preferably shallow
Groove isolation construction, internal to have isolation structure filled layer 103, material includes but not limited to silica.Then, have described
The groove structure 106 is etched in source region, there are two groove knots as shown in figure 4, being shown as the formation in the active area 101
The schematic diagram of structure 106, in addition, the cross sectional shape of the groove structure 106 is preferably U-shaped, it is, of course, also possible to be applicable in for rectangle etc.
The arbitrary shape of device performance.
As an example, in step 1), the step of forming groove structure 106, includes：
1-1) as shown in figure 3, forming one layer of mask layer 104 with window 105 in 100 surface of Semiconductor substrate,
Wherein, the window 105 and the groove structure are corresponding about 106；And
1-2) as shown in figure 4, being performed etching based on the window 105 to the Semiconductor substrate 100, to form the ditch
Slot structure 106.
Specifically, this example provides a kind of formation process of the groove structure 106, it is necessary to illustrate, in this example
Preparation process in, preferably retain the isolation structure filled layer 103 for filling the isolation structure 102, i.e., served as a contrast in the semiconductor
The surface at bottom 100 is there are one layer of isolation structure filled layer, such as silicon oxide layer, as shown in Figure 2, certainly, and in other examples,
This one silica layer on surface can also be removed, and is not particularly limited, then, the preparation of groove structure 106 is carried out, using light
Carve and etching technique is formed in the Semiconductor substrate 100 have window 105 the mask layer 104, wherein, first in
Mask layer is formed in the Semiconductor substrate 100, and uses the photoresist with opening as mask to the mask material
The bed of material performs etching, and forms the mask layer 104 with the window 105, and continues to etch the Semiconductor substrate, with
Form the groove structure 106.
As shown in S2 and Fig. 5 in Fig. 1, step 2) is then carried out, is formed in the bottom of the groove structure 106 and side wall
Dielectric layer 107；
As an example, in step 2), using steam in situ (ISSG) technique in the bottom of the groove structure 106 and side wall
Form the dielectric layer 107.
Specifically, the material of the dielectric layer 107 can be but not limited to silica, silicon nitride, the silica can be with
Resistivity for silicon monoxide or silica, and material is preferably 2 × 1011~1 × 1025Ω m, naturally it is also possible to be other
Material medium layer, the material selection of the dielectric layer 107 in this example is silica.The dielectric layer 107 can be by atom
Deposition manufacture process (Atomic Layer Deposition) or plasma vapor deposition (Chemical Vapor Deposition)
Film or quick heated oxide (Rapid Thermal Oxidation) and formed, it is preferable that the dielectric layer 107 is using former
Position steam (in-situ stream generation, ISSG) technique is prepared, and substantial amounts of gas-phase activity is generated in preparation certainly
By base, the oxidation of silicon chip is taken part in, so as to obtain the less film of defect, by insulation lateral sulcus 114 in this present embodiment
The surface of dielectric layer described in expose portion, so as to obtain good device performance.
As shown in the S3 in Fig. 1 and Fig. 6~9, step 3) is carried out, in the bottom of the dielectric layer 107 and partial sidewalls shape
Wordline physical layer 113, the wordline physical layer 113 are formed into wordline superficial layer 112, and in 112 surface of wordline superficial layer
Filling part 1131 including being incorporated into 112 surface of wordline superficial layer and the lug boss on the filling part 1131 top
1132, wherein, the top of the wordline superficial layer 112 is less than the upper surface of the Semiconductor substrate 100, the lug boss 1132
Top of the top higher than the wordline superficial layer 112 and the upper surface less than the Semiconductor substrate 100, and the lug boss
Lateral sulcus 114 is formed between 1132 lateral wall and the dielectric layer 107；
Specifically, by the technique of this step, two conductive layers, the wordline table are formed in the groove structure 106
The material of surface layer 112 includes but not limited to titanium nitride, and the material of the wordline physical layer 113 includes but not limited to tungsten metal, and
And lateral sulcus 114 is formed between wordline physical layer 113 and dielectric layer 107, further, the thickness of the wordline superficial layer 112 is used
In the width for limiting the air chamber, the thickness range of the wordline superficial layer 112 includes 0.8~5 nanometer.
As an example, in step 3), step is further included：In the wordline superficial layer 112 and the wordline physical layer 113 it
Between formed one layer of adhesion layer.
Specifically, the material of the adhesion layer can be with selected as silane (SiH4) and tetrachloro silicane (SiCl4) at least one
Kind, it is of course also possible to be the laminated structural layers of the two, so as to so that wordline superficial layer (such as TiN) and wordline physical layer (such as W)
Between form good interface, the wordline physical layer is filled up in the gap allowed in the wordline superficial layer.
As an example, in step 3), the step of forming the wordline superficial layer 112 and wordline physical layer 113, includes：
3-1) the semiconductor lining around the bottom of the groove structure 106, side wall and the groove structure 106
100 surface of bottom forms one layer of first conductive material layer 108；
One layer of second conductive material layer 109 3-2) is formed in 108 surface of the first conductive material layer, described second is conductive
The full groove structure 106 of the filling of material layer 109 simultaneously extends over first conduction material on the semiconductor substrate surface
The bed of material；
3-3) first conductive material layer 108 and second conductive material layer 109 are performed etching, to be respectively formed
First conductive material part 110 and the second conductive material part 111, the top of first conductive material part 110 to the semiconductor
The upper surface of substrate 100 and the upper surface of the top of second conductive material part 111 to the Semiconductor substrate 100 all have
First spacing Z1；And
3-4) by wet-etching technology to first conductive material layer 108 and second conductive material layer 109 after
It is continuous to perform etching, to be respectively formed the wordline superficial layer 112 and the wordline physical layer 113, the wordline superficial layer 112
Top to the upper surface of the Semiconductor substrate 100 has the second spacing Z2, the top of the wordline physical layer 113 to described half
There is the 3rd spacing Z3, the second spacing Z2 to be more than the 3rd spacing Z3 for the upper surface of conductor substrate 100, described to define
The height of protrusion 1132.
As an example, the first spacing Z1 is between 30~70 nanometers；The second spacing Z2 and the 3rd spacing Z3
Difference between 1~40 nanometer.
As an example, step 3-3) in, by the technique of alternately etching to first conductive material layer 108 and described the
Two conductive material layers 109 perform etching, wherein, the etching gas of the alternately etching include sulfur hexafluoride, chlorine and argon gas
(SF6), chlorine (Cl2) and argon gas (Ar) form arbitrary two or three of combination in group.
Specifically, this example the preparation process of a kind of wordline superficial layer 112 and the wordline physical layer 113 is provided, it is necessary to
Illustrate, shown in the drawings of the isolation structure filled layer 103 and the feelings of mask layer 104 mentioned in the example for retaining the present invention
The situation of technique is carried out under condition, first, one layer of first conductive material layer 108 is formed, as shown in fig. 6, covering one in the above again
The second conductive material layer 109 of layer, as shown in fig. 7, first conductive material layer 108 and second conductive material layer 109
It prepares and includes but not limited to the depositing operations such as plating, chemical vapor deposition, physical vapour deposition (PVD) or atomic layer deposition, this example
In, selected as chemical vapor deposition (CVD) technique.
Then, further include through chemical-mechanical planarization (Chemical-Mechanical Planarization, CMP)
The technique planarized to the two layers of material on 100 surface of Semiconductor substrate.Then using the technique pair of alternately etching
Two layers of material is once etched, as shown in figure 8, etching the result is that first conductive material layer 108 becomes first leads
Electric material portion 110, second conductive material layer 109 become the second conductive material part 111, certainly, the first conductive material part 110
Can there can be different spacing from 100 surface of Semiconductor substrate with the second conductive material part 111, pass through subsequent technique
The structure needed is formed, both is preferably that there is identical spacing Z1 away from 100 surface of Semiconductor substrate in this example, from
And being conducive to the control of subsequent technique, the etching of the step is preferably dry etching, and alternating is passed through to first, second conductive material
Layer has the gas of different etching rate, and using the first conductive material layer as titanium nitride, the second conductive material layer is quarter exemplified by tungsten metal
It loses gas and uses SF6/Cl2, by adjusting flow proportional or a other etching period to perform etching.
Finally, as shown in figure 9, again by an etching technics, the etch rate to two kinds of materials is controlled, finally obtains word
Line superficial layer 112 and wordline physical layer 113 and the formation insulation lateral sulcus between wordline physical layer 113 and dielectric layer 107
114, wherein, wordline superficial layer 112 has the second spacing Z2, wordline physical layer 113 and institute with 100 surface of Semiconductor substrate
The height that difference of 100 surface of Semiconductor substrate with the 3rd spacing Z3, Z3 and Z2 is also the protrusion 1132 is stated, is also
The length of the insulation lateral sulcus 114, and the thickness of the wordline superficial layer 112 is the width of the insulation lateral sulcus 114.
As an example, step 3-4) in, carrying out the reagent of the wet etching includes ammonium hydroxide, hydrogen peroxide and water composition
Mixed liquor, wherein, ammonium hydroxide (NH in the mixed liquor4OH), hydrogen peroxide (H2O2) and water (H2O ratio) is sequentially 1 to 0.01
~2 to 5~150；Carrying out the temperature range of the wet etching includes 4~25 DEG C.
Specifically, giving the technique that a kind of wet etching forms wordline superficial layer and wordline physical layer in this example, adopt
Wet etching is carried out with APM reagents, reagent includes ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O), the dense of APM is adjusted
Scope and temperature range are spent, the etch rate to the first conductive material layer (such as TiN) is improved, reduces to the second conductive material layer
The etch rate of (such as W), so as to the structure needed, it is preferable that ammonium hydroxide (NH in the mixed liquor4OH), hydrogen peroxide (H2O2)
And water (H2O ratio) includes 1:(0.1~1.5):(20~100), selected as 1 in this example:1:50；In addition, it carries out wet
The temperature of method etching is preferably 10~20 DEG C, 15 DEG C of selected as in this example.
As an example, before step 4), step is further included：Using dilute hydrogen fluoride acid (DHF) reagent to the wordline physical layer
113 surface is cleaned to remove surface by-product, and the DHF reagents include the mixed liquor of hydrofluoric acid and water, the mixing
The ratio of hydrofluoric acid (HF) and water includes 1 than (50~1000) in liquid.
Specifically, using DHF reagents so as to remove the oxide layer formed in operation process by oxidation, as formed
WO, so as to reduce the impedance of word line structure.Preferably, the ratio of hydrofluoric acid (HF) and water includes 1 in the mixed liquor:(100~
500) it is 1 that thief, is selected in this example:300.
As shown in S4 and Figure 10 in Fig. 1, step 4) is carried out, in formation filling perforation insulating layer in the groove structure 106
115, the bottom of the filling perforation insulating layer 115 covers the top of the wordline physical layer 113 and the top of the lateral sulcus 114,
The lateral sulcus 114 closing is formed air chamber 1141；
As an example, in step 4), the filling perforation insulating layer 115 is formed by atom layer deposition process, so as to not destroy
The insulation lateral sulcus 114.
As an example, the deposition of the atom layer deposition process is between 200~1000 nm/minutes.
Specifically, finally carrying out step 4), filling perforation insulating layer 115 is formed, as shown in Figure 10, and the filling perforation is controlled to insulate
Layer 115 is not deposited in the insulation lateral sulcus 114, so as to ensure the integrality of insulation lateral sulcus 114, may be employed CVD's or ALD
Method forms filling perforation insulating layer 115 and fills up GAP (in the top of groove structure), wherein, deposition is controlled in 200~1000nm/
Min is preferably 220~500nm/min, and selected as 250nm/min in this example, the material of the filling perforation insulating layer 115 includes
But it is not limited to silicon nitride.
It should be noted that by the step, lateral sulcus 114 is enclosed so as to form air chamber in the device structure
(void) 1141, in the case where the other parts of device architecture are identical, the part of air chamber (void) is compared, due to
The presence of air chamber 1141 makes original conductive layer (being such as equivalent to the wordline surface layer part in this example) portions turn for sky
The air of air cavity changes the middle dielectric layer of capacitance, so as to reduce parasitic capacitance, gives one kind as shown in figure 14 and shows
Example, it is shown that the capacitance variations situation in device, wherein, Figure 14 (a) is shown as capacitance situation of the prior art, Figure 14 (b)
The capacitance situation being shown as in the device architecture of the present invention.
In addition, it should also be noted that, technical solution using the present invention, due to the 112 direct shape of wordline superficial layer
The surface of dielectric layer 107 described in Cheng Yu, therefore, the wordline superficial layer 112 are used as functional structure layer (work function),
Determine the threshold voltage vt of device architecture, meanwhile, it is formed at the wordline physical layer 113 inside the wordline superficial layer 112 and has
There is current lead-through, since it can include protruding from the lug boss 1132 of the wordline superficial layer 112, then it is high
Degree can have more flexible selection, so as to reduce the resistance in transistor, it is ensured that reduce while small leakage current
The resistance of transistor, in addition, the wordline superficial layer 112 is also used as the diffusion impervious layer of the wordline physical layer 113.Institute
Dual electric layer structure 111 to be stated both as grid, also serves as wordline, the grid wordline of this flush type can save device space,
Device size is reduced, improves device speed.
As an example, in step 1), the size of the opening of the groove structure 106 is between 10~50 nanometers；In step 2),
The thickness of the dielectric layer 107 is between 1~9 nanometer；In step 3), the width of the air chamber 1141 between 0.8~5 nanometer,
The height of the air chamber 1141 is between 1~40 nanometer.
Specifically, in this example, the opening of the groove structure 106 is preferably dimensioned to be 20~40 nanometers, wherein, opening
Size refers to the opening width in its sectional view, as shown in the D in Fig. 4,30 nanometers of selected as in this example；The dielectric layer
107 thickness is preferably 2~8 nanometers, 6 nanometers of selected as in this example；Width (the wordline superficial layer of the air chamber 1141
112 thickness) it is preferably 1~4 nanometer, 2 nanometers of selected as in this example, the height (lug boss of the air chamber 1141
Height) be preferably 10~30 nanometers, 20 nanometers of selected as in this example.
It should also be noted that, due to the presence of parasitic capacitance in device, wherein, in systems, these undesirable electricity
Hold from every aspect, such as the material of PCB, thickness, layer structure, the cabling depth of parallelism, these are all the parasitisms for influencing pcb board
Capacitance also has the parasitic capacitance of component in itself, and most hateful is that these things are also influenced by environment temperature.In high speed circuit
On, since frequency is higher and higher, the influence of parasitic capacitance cannot ignore, and as shown in figure 12, can cause device exists " to shake
Bell " phenomenon, and the structure that preparation process using the present invention obtains can be effectively improved this phenomenon.
The present invention also provides a kind of preparation methods of memory cell array, comprise the following steps：
A) multiple storage units with transistor arrangement are formed, and each storage unit is configured as cell row and list
Member row, wherein, the transistor arrangement uses any one transistor arrangement preparation scheme in the present embodiment to be prepared, institute
The each active area for stating transistor arrangement respectively connects two capacitances；And
B) the wordline physical layer of each storage unit in addressed line to the cell row or the cell columns is connected, with
Memory cell array is prepared, wherein, the addressed line is used to control the storage unit.
In addition, as shown in figure 11, transistor arrangement preparation process disclosed in this invention is used the present invention also provides a kind of
The method that the transistor being prepared prepares storage unit, wordline superficial layer 112 and wordline physical layer 113 are collectively as grid
Word line structure is connected with the driving of wordline 117, and source region is connected with capacitance 116, drain region connection amplifier 118, and in Figure 12
In a kind of connection mode of storage array is shown, specifically, data read during, data is exported via capacitance to weld pad
(pad) export, during data are write, data are via weld pad and are stored among capacitance.
In addition, as shown in figure 15, the present invention also provides a kind of products comprising transistor arrangement provided in this embodiment
Preparation method and the product being prepared, wherein, the preparation method of the product includes preparing crystalline substance provided in this embodiment
The step of body pipe, further includes the step of preparing channel region 119, shallow junction region 120 and doped drain 121, wherein, described active
B (boron) is carried out in area 101 to adulterate to prepare the channel region 119, and As (arsenic) is carried out in the active area 101 and adulterates to prepare
The shallow junction region 120 carries out P (phosphorus) in the active area 101 and adulterates to prepare the doped drain 121.
The present invention also provides a kind of transistor arrangement, wherein, the transistor arrangement be preferably using the present embodiment provides
The preparation method of transistor arrangement be prepared, but be not limited in this approach, as shown in Figure 10, the transistor arrangement bag
It includes：
Semiconductor substrate 100 has active area 101；
Groove structure 106, in the active area 101 of the Semiconductor substrate 100；
Dielectric layer 107, positioned at the bottom of the groove structure 106 and side wall；
Wordline superficial layer 112, positioned at the bottom of the dielectric layer 107 and partial sidewalls, and the wordline superficial layer 112
Top is less than the upper surface of the Semiconductor substrate 100；
Wordline physical layer 113, positioned at 112 surface of wordline superficial layer, and including being incorporated into the wordline superficial layer 112
The filling part 1131 on surface and the lug boss 1132 on the filling part 1131 top, the top of the lug boss 1132 is higher than
The top of the wordline superficial layer 112 and the upper surface for being less than the Semiconductor substrate 100, the lateral wall of the lug boss 1132
Lateral sulcus 114 is formed between the dielectric layer 107；And
Filling perforation insulating layer 115 is filled in the top of the groove structure 106, and the bottom of the filling perforation insulating layer 115
It covers the top of the wordline physical layer 113 and the top of the lateral sulcus 114 and is located at 1132 both sides of lug boss to be formed
Air chamber 1141.
As an example, the thickness of the wordline superficial layer is between 0.8~5 nanometer, to limit the air chamber 1141
Width.
As an example, the material of the dielectric layer 107 includes silica, the material of the wordline superficial layer 112 includes nitrogen
Change titanium, the material of the wordline physical layer 113 includes tungsten, and the material of the filling perforation insulating layer 115 includes silicon nitride.
Specifically, in this example, the active area 101 is isolated structure 102 and separates, and the isolation structure 102 is preferably
Fleet plough groove isolation structure, internal to have isolation structure filled layer 103, material includes but not limited to silica.The dielectric layer
107 material can be but not limited to silica, silicon nitride, and the silica can be silicon monoxide or silica.
It should be noted that the material of the wordline superficial layer 112 includes but not limited to titanium nitride, the wordline physical layer
113 material includes but not limited to tungsten metal, and forms air chamber between wordline physical layer 113 and dielectric layer 107
(void) 1141, so as to, in the case where the other parts of device architecture are identical, the part of air chamber is compared, due to
The presence of air chamber 1141 makes original conductive layer (being such as equivalent to the wordline surface layer part in this example) portions turn for sky
The air of air cavity changes the middle dielectric layer of capacitance, so as to reduce parasitic capacitance.
Further, since the wordline superficial layer 112 is formed directly into the surface of the dielectric layer 107, therefore, the wordline
Superficial layer 112 is used as functional structure layer (work function), determines the threshold voltage vt of device architecture, meanwhile, it is formed at
Wordline physical layer 113 inside the wordline superficial layer 112 plays an important role of current lead-through, since it can include protruding from institute
The lug boss 1132 of wordline superficial layer 112 is stated, then its height there can be more flexible selection, so as to reduce transistor
In resistance, it is ensured that reduce the resistance of transistor while small leakage current, in addition, the wordline superficial layer 112 may be used also
Using the diffusion impervious layer as the wordline physical layer 113.The dual electric layer structure 111 both as grid, also served as wordline,
The grid wordline of this flush type can save device space, reduce device size, improve device speed.
As an example, one layer of adhesion layer is also formed between the wordline superficial layer 112 and the wordline physical layer 113.
The material of the adhesion layer can be with selected as silane (SiH4) and tetrachloro silicane (SiCl4At least one of), it is of course also possible to
For the laminated structural layers of the two, so as to so as to be formed between wordline superficial layer (such as TiN) and wordline physical layer (such as W) good
The wordline physical layer is filled up in interface, the gap allowed in the wordline superficial layer.
As an example, the size of the opening of the groove structure is between 10~50 nanometers；The thickness of the dielectric layer is between 1
~9 nanometers；The width of the air chamber is between 0.8~5 nanometer, and the height of the air chamber is between 1~40 nanometer.
Specifically, in this example, the opening of the groove structure 106 is preferably dimensioned to be 20~40 nanometers, wherein, opening
Size refers to the opening width in its sectional view, as shown in the D in Fig. 4,30 nanometers of selected as in this example；The dielectric layer
107 thickness is preferably 2~8 nanometers, 6 nanometers of selected as in this example；Width (the wordline superficial layer 112 of the air chamber 114
Thickness) be preferably 1~4 nanometer, 2 nanometers of selected as in this example, the height (height of the lug boss of the air chamber 114
Degree) it is preferably 10~30 nanometers, 20 nanometers of selected as in this example.
The present invention also provides a kind of memory cell array, including：
Several storage units, the storage unit include the transistor junction described in any one scheme in the present embodiment
Structure, and each memory cell arrangements, into cell row and cell columns, each active area of the transistor arrangement respectively connects two
A capacitance；And
Addressed line is connected to the wordline physical layer of each storage unit in the cell row or the cell columns, institute
Addressed line is stated for controlling the storage unit.
The present invention also provides a kind of memory construction, including the storage unit battle array described in any one scheme in the present embodiment
Row.
Further, several fleet plough groove isolation structures are further included in the memory construction, wherein, the adjacent shallow trench
It is active area between isolation structure, there are two the transistor arrangements being spaced apart for setting.
In conclusion the present invention provides a kind of transistor arrangement, memory cell array and preparation method, transistor prepares bag
It includes：There is provided one has the Semiconductor substrate of active area, and in forming groove structure in the active area；In the groove structure
Bottom and side wall form dielectric layer；Wordline superficial layer is formed in the bottom of the dielectric layer and partial sidewalls, and in the wordline
Surface layer surface forms wordline physical layer, the wordline physical layer include the filling part for being incorporated into wordline surface layer surface and
Lug boss on the filling part top, wherein, the top of the wordline superficial layer is less than the upper table of the Semiconductor substrate
Face, top of the top higher than the wordline superficial layer of the lug boss and the upper surface less than the Semiconductor substrate, and institute
It states and forms lateral sulcus between the lateral wall of lug boss and the dielectric layer；It is described in formation filling perforation insulating layer in the groove structure
The bottom of filling perforation insulating layer covers the top of the wordline physical layer and the top of the lateral sulcus, by the lateral sulcus enclosed shape
Into air chamber.Through the above scheme, the present invention prepares transistor arrangement by deposition and wet-etching technology, and forming one kind has
The transistor of air chamber (void), so as in the case where the other parts of device architecture are identical, be carried out to the part of air chamber
Compare, due to the presence of air chamber, original Conductive layer portions is made to be changed into the air of air chamber, change intermediate Jie of capacitance
Matter layer, so as to reduce parasitic capacitance；In addition, technical solution using the present invention, it can also be ensured that while small leakage current
Increase the height of the metal layer as grid wordline, so as to reduce the resistance of transistor.So the present invention effectively overcome it is existing
Various shortcoming in technology and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (21)
1. a kind of preparation method of transistor arrangement, which is characterized in that include the following steps：
1) providing one has the Semiconductor substrate of active area, and in forming groove structure in the active area；
2) dielectric layer is formed in the bottom of the groove structure and side wall；
3) wordline superficial layer is formed in the bottom of the dielectric layer and partial sidewalls, and word is formed in wordline surface layer surface
Line physical layer, the wordline physical layer include being incorporated into the filling part of wordline surface layer surface and positioned at the filling part top
On lug boss, wherein, the top of the wordline superficial layer is less than the upper surface of the Semiconductor substrate, the top of the lug boss
End higher than the wordline superficial layer top and less than the Semiconductor substrate upper surface, and the lateral wall of the lug boss with
Lateral sulcus is formed between the dielectric layer；And
4) in forming filling perforation insulating layer in the groove structure, the bottom of the filling perforation insulating layer covers the wordline physical layer
Top and the top of the lateral sulcus, the lateral sulcus is closed to form air chamber.
2. the preparation method of transistor arrangement according to claim 1, which is characterized in that the thickness of the wordline superficial layer
Between 0.8~5 nanometer, to limit the width of the air chamber.
3. the preparation method of transistor arrangement according to claim 2, which is characterized in that in step 1), the groove knot
The size of the opening of structure is between 10~50 nanometers；In step 2), the thickness of the dielectric layer is between 1~9 nanometer；In step 4),
The height of the air chamber is between 1~40 nanometer.
4. the preparation method of transistor arrangement according to claim 1, which is characterized in that in step 1), form the ditch
The step of slot structure, includes：
One layer of mask layer with window 1-1) is formed in the semiconductor substrate surface, wherein, the window and the groove
Structure is corresponding up and down；And
1-2) Semiconductor substrate is performed etching based on the window, to form the groove structure.
5. the preparation method of transistor arrangement according to claim 1, which is characterized in that in step 2), using water in situ
Vapour (ISSG) technique forms the dielectric layer.
6. the preparation method of transistor arrangement according to claim 1, which is characterized in that in step 3), further include step：
One layer of adhesion layer is formed between the wordline superficial layer and the wordline physical layer.
7. the preparation method of transistor arrangement according to claim 1, which is characterized in that in step 3), form the word
The step of line superficial layer and the wordline physical layer, includes：
3-1) semiconductor substrate surface around the bottom of the groove structure, side wall and the groove structure is formed
One layer of first conductive material layer；
3-2) one layer of second conductive material layer, the second conductive material layer filling are formed in the first conductive material layer surface
The full groove structure simultaneously extends over first conductive material layer on the semiconductor substrate surface；
3-3) first conductive material layer and second conductive material layer are performed etching, to be respectively formed the first conduction material
Material portion and the second conductive material part, top to the upper surface of the Semiconductor substrate of first conductive material part and described
The top of two conductive material parts to the upper surface of the Semiconductor substrate all has the first spacing；And
3-4) first conductive material layer and second conductive material layer are continued to etch by wet-etching technology,
Yi Fen Do form the wordline superficial layer and the wordline physical layer, the top of the wordline superficial layer to the Semiconductor substrate
Upper surface there is the second spacing, top to the upper surface of the Semiconductor substrate of the wordline physical layer has between the 3rd
Away from second spacing is more than the 3rd spacing, to define the height of the protrusion.
8. the preparation method of transistor arrangement according to claim 7, which is characterized in that first spacing between 30~
70 nanometers；The difference of second spacing and the 3rd spacing is between 1~40 nanometer.
9. the preparation method of transistor arrangement according to claim 7, which is characterized in that step 3-4) in, described in progress
The reagent of wet etching includes ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water composition mixed liquor, wherein, in the mixed liquor
The ratio of ammonium hydroxide, hydrogen peroxide and water is sequentially 1 to 0.01~2 to 5~150.
10. the preparation method of transistor arrangement according to claim 7, which is characterized in that step 3-3) in, pass through alternating
The technique of etching performs etching first conductive material layer and second conductive material layer, wherein, it is described alternately to etch
Etching gas include sulfur hexafluoride (SF6), chlorine (Cl2) and argon gas (Ar) and form arbitrary two or three in group
Combination.
11. the preparation method of transistor arrangement according to claim 1, which is characterized in that before step 4), further include step
Suddenly：Dilute hydrogen fluoride acid (DHF) reagent is used to be cleaned to remove surface by-product to the surface of the wordline physical layer, wherein,
The dilute hydrogen fluoride acid reagent includes the mixed liquor of hydrofluoric acid (HF) and water, wherein, the ratio of hydrofluoric acid and water including 1 to 50~
1000。
12. the preparation method of transistor arrangement according to claim 1, which is characterized in that in step 2), the dielectric layer
Material include silica；In step 3), the material of the wordline superficial layer includes titanium nitride, the material of the wordline physical layer
Including tungsten；In step 4), the material of the filling perforation insulating layer includes silicon nitride.
13. the preparation method of the transistor arrangement according to any one in claim 1~12, which is characterized in that step
4) in, the filling perforation insulating layer is formed by atom layer deposition process, so as to not destroy the air chamber.
14. the preparation method of transistor arrangement according to claim 13, which is characterized in that the atom layer deposition process
Deposition between 200~1000 nm/minutes.
15. a kind of preparation method of memory cell array, which is characterized in that comprise the following steps：
A) multiple storage units with transistor arrangement are formed, and each storage unit is configured as cell row and unit
Row, wherein, the transistor arrangement is prepared using preparation method as described in claim 1, the transistor arrangement
Each active area respectively connection two capacitances；And
B) the wordline physical layer of each storage unit in addressed line to the cell row or the cell columns is connected, to prepare
Memory cell array, wherein, the addressed line is used to control the storage unit.
16. a kind of transistor arrangement, which is characterized in that including：
Semiconductor substrate has active area；
Groove structure, in the active area of the Semiconductor substrate；
Dielectric layer, positioned at the bottom of the groove structure and side wall；
Wordline superficial layer, positioned at the bottom of the dielectric layer and partial sidewalls, and the top of the wordline superficial layer is less than described
The upper surface of Semiconductor substrate；
Wordline physical layer, positioned at the surface of the wordline superficial layer, the wordline physical layer includes being incorporated into the wordline surface
Filling part in layer and the lug boss on the filling part top, the top of the lug boss is higher than the wordline superficial layer
Top and the upper surface for being less than the Semiconductor substrate, side is formed between the lateral wall of the lug boss and the dielectric layer
Ditch；And
Filling perforation insulating layer is filled in the top of the groove structure, and the bottom of the filling perforation insulating layer covers the wordline reality
The top of body layer and the top of the lateral sulcus are located at the air chamber of the lug boss both sides to be formed.
17. transistor arrangement according to claim 16, which is characterized in that the thickness of the wordline superficial layer is between 0.8
~5 nanometers, to limit the width of the air chamber.
18. transistor arrangement according to claim 17, which is characterized in that the size of the opening of the groove structure between
10~50 nanometers；The thickness of the dielectric layer is between 1~9 nanometer；The height of the air chamber is between 1~40 nanometer.
19. transistor arrangement according to claim 16, which is characterized in that the material of the dielectric layer includes silica,
The material of the wordline superficial layer includes titanium nitride, and the material of the wordline physical layer includes tungsten, the material of the filling perforation insulating layer
Material includes silicon nitride.
20. a kind of memory cell array, which is characterized in that including：
Several storage units, the storage unit include transistor arrangement as claimed in claim 16, and each storage
Unit is configured to cell row and cell columns, and each active area of the transistor arrangement respectively connects two capacitances；And
Addressed line is connected to the wordline physical layer of each storage unit in the cell row or the cell columns, described to seek
Location line is used to control the storage unit.
21. a kind of memory construction, which is characterized in that including memory cell array as claimed in claim 20.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610940A (en) * | 2018-06-15 | 2019-12-24 | 长鑫存储技术有限公司 | Memory transistor, word line structure of memory transistor and word line preparation method |
| CN111430348A (en) * | 2020-04-14 | 2020-07-17 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN111508841A (en) * | 2019-01-30 | 2020-08-07 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113644032A (en) * | 2021-08-11 | 2021-11-12 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN113707612A (en) * | 2021-07-19 | 2021-11-26 | 长鑫存储技术有限公司 | Memory device and method of forming the same |
| CN114093942A (en) * | 2020-07-30 | 2022-02-25 | 中国科学院微电子研究所 | Semiconductor structure, manufacturing method thereof and DRAM |
| WO2022041896A1 (en) * | 2020-08-24 | 2022-03-03 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN114267641A (en) * | 2020-09-16 | 2022-04-01 | 长鑫存储技术有限公司 | Manufacturing method of embedded word line transistor, transistor and memory |
| CN116546815A (en) * | 2023-06-21 | 2023-08-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN116648062A (en) * | 2021-07-08 | 2023-08-25 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
| WO2024021180A1 (en) * | 2022-07-28 | 2024-02-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US12041764B2 (en) | 2020-09-16 | 2024-07-16 | Changxin Memory Technologies, Inc. | Method for manufacturing buried word line transistor, transistor and memory |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1003219A2 (en) * | 1998-11-19 | 2000-05-24 | Siemens Aktiengesellschaft | DRAM with stacked capacitor and buried word line |
| JP2012248604A (en) * | 2011-05-26 | 2012-12-13 | Denso Corp | Semiconductor device and method of manufacturing the same |
| CN104103577A (en) * | 2013-04-12 | 2014-10-15 | 爱思开海力士有限公司 | Semiconductor device with air gap and method for fabricating the same |
| CN104103638A (en) * | 2013-04-01 | 2014-10-15 | 三星电子株式会社 | Semiconductor device and semiconductor module |
| US8896059B1 (en) * | 2013-07-24 | 2014-11-25 | SK Hynix Inc. | Semiconductor device including multi-layered gate, electronic device including the same, and method for forming the same |
| US20150221742A1 (en) * | 2014-02-04 | 2015-08-06 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
| CN107104103A (en) * | 2017-05-19 | 2017-08-29 | 睿力集成电路有限公司 | A kind of transistor arrangement and preparation method thereof |
| CN107134486A (en) * | 2017-04-28 | 2017-09-05 | 睿力集成电路有限公司 | Memory |
| US9786760B1 (en) * | 2016-09-29 | 2017-10-10 | International Business Machines Corporation | Air gap and air spacer pinch off |
| CN207852681U (en) * | 2017-11-27 | 2018-09-11 | 睿力集成电路有限公司 | Transistor arrangement and memory cell array |
-
2017
- 2017-11-27 CN CN201711206798.5A patent/CN108063140B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1003219A2 (en) * | 1998-11-19 | 2000-05-24 | Siemens Aktiengesellschaft | DRAM with stacked capacitor and buried word line |
| JP2012248604A (en) * | 2011-05-26 | 2012-12-13 | Denso Corp | Semiconductor device and method of manufacturing the same |
| CN104103638A (en) * | 2013-04-01 | 2014-10-15 | 三星电子株式会社 | Semiconductor device and semiconductor module |
| CN104103577A (en) * | 2013-04-12 | 2014-10-15 | 爱思开海力士有限公司 | Semiconductor device with air gap and method for fabricating the same |
| US8896059B1 (en) * | 2013-07-24 | 2014-11-25 | SK Hynix Inc. | Semiconductor device including multi-layered gate, electronic device including the same, and method for forming the same |
| US20150221742A1 (en) * | 2014-02-04 | 2015-08-06 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
| US9786760B1 (en) * | 2016-09-29 | 2017-10-10 | International Business Machines Corporation | Air gap and air spacer pinch off |
| CN107134486A (en) * | 2017-04-28 | 2017-09-05 | 睿力集成电路有限公司 | Memory |
| CN107104103A (en) * | 2017-05-19 | 2017-08-29 | 睿力集成电路有限公司 | A kind of transistor arrangement and preparation method thereof |
| CN207852681U (en) * | 2017-11-27 | 2018-09-11 | 睿力集成电路有限公司 | Transistor arrangement and memory cell array |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610940A (en) * | 2018-06-15 | 2019-12-24 | 长鑫存储技术有限公司 | Memory transistor, word line structure of memory transistor and word line preparation method |
| CN111508841A (en) * | 2019-01-30 | 2020-08-07 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN111430348A (en) * | 2020-04-14 | 2020-07-17 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN111430348B (en) * | 2020-04-14 | 2022-05-03 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN114093942B (en) * | 2020-07-30 | 2024-05-28 | 中国科学院微电子研究所 | Semiconductor structure, manufacturing method thereof and DRAM |
| CN114093942A (en) * | 2020-07-30 | 2022-02-25 | 中国科学院微电子研究所 | Semiconductor structure, manufacturing method thereof and DRAM |
| WO2022041896A1 (en) * | 2020-08-24 | 2022-03-03 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US12041764B2 (en) | 2020-09-16 | 2024-07-16 | Changxin Memory Technologies, Inc. | Method for manufacturing buried word line transistor, transistor and memory |
| CN114267641A (en) * | 2020-09-16 | 2022-04-01 | 长鑫存储技术有限公司 | Manufacturing method of embedded word line transistor, transistor and memory |
| CN116648062B (en) * | 2021-07-08 | 2024-06-28 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
| CN116648062A (en) * | 2021-07-08 | 2023-08-25 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
| CN113707612A (en) * | 2021-07-19 | 2021-11-26 | 长鑫存储技术有限公司 | Memory device and method of forming the same |
| CN113707612B (en) * | 2021-07-19 | 2023-10-20 | 长鑫存储技术有限公司 | Memory device and method of forming the same |
| CN113644032B (en) * | 2021-08-11 | 2023-10-10 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
| CN113644032A (en) * | 2021-08-11 | 2021-11-12 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| WO2024021180A1 (en) * | 2022-07-28 | 2024-02-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN116546815B (en) * | 2023-06-21 | 2023-11-24 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN116546815A (en) * | 2023-06-21 | 2023-08-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
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