CN207852674U - transistor and memory cell array - Google Patents
transistor and memory cell array Download PDFInfo
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- CN207852674U CN207852674U CN201721686101.4U CN201721686101U CN207852674U CN 207852674 U CN207852674 U CN 207852674U CN 201721686101 U CN201721686101 U CN 201721686101U CN 207852674 U CN207852674 U CN 207852674U
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Abstract
A kind of transistor of the utility model offer and memory cell array, including：Semiconductor substrate has active area, is formed in semiconductor substrate in groove structure；Buried gate word line structure is located in groove structure, and buried gate word line structure includes：Gate oxide is located at the bottom and side wall of groove structure；First conductive layer is located at bottom and the partial sidewalls of gate oxide；Second conductive layer, second conductive layer include be filled in the lower part of groove structure and surface cover the first conductive layer filling part and the lug boss on filling part, wherein, top of the top of lug boss higher than the first conductive layer and the upper surface less than semiconductor substrate, the spacing between the outside side wall of any length and gate oxide of lug boss account for 1% ~ 50% of groove structure in same widths to the opening size under section.The utility model improves the height of grid wordline, reduces the resistance of grid wordline, to reduce the access time of device.
Description
Technical field
The utility model belongs to ic manufacturing technology field, more particularly to a kind of transistor and storage unit battle array
Row.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer
Semiconductor storage unit, be made of the storage unit of many repetitions.Each storage unit is mainly by a transistor and one
It is a to be made of the capacitor that transistor is manipulated, and storage unit can be arranged in array format, each storage unit passes through
Wordline is electrically connected to each other with bit line.As electronic product is increasingly towards light, thin, short, small development, dynamic random access memory
The design of component also have to comply with high integration, it is highdensity require towards miniaturization trend development, for improve dynamic with
Machine accesses the integration of memory to accelerate the service speed of component, and meets need of the consumer for miniaturized electronic device
It asks, develops buried gate wordline dynamic random access memory in recent years, to meet above-mentioned various demands.
However, in above-mentioned this structure, constantly reduces with the array of dynamic RAM, there is reduction wordline
Balanced problem between resistance and reduction gate induced drain leakage electric current, wherein with the reduction of device size, wordline electricity
Resistance can gradually increase, and which increase the access times of device, generally can be by increasing the height of wordline to realize the low electricity of itself
Resistance, but at the same time, field distribution of the grid (wordline) between source and drain will change, and be generated below buried gate wordline
Higher electric field, to which the overlapping region between source/drain and grid causes higher grid to be led to drain leakage (GIDL
Current), and the storage time (retention time) of embedded type word line dynamic random access memory is reduced.
Therefore it provides a kind of energy solves, above-mentioned grid word line resistance reduces and grid is led to that drain leakage flow phenomenon generates it
Between conflicting scheme be necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of transistor and storage are single
Element array is especially used to solve grid word line resistance reduction in the prior art and is led to that drain leakage flow phenomenon generates it with grid
Between conflicting problem.
In order to achieve the above objects and other related objects, the utility model provides a kind of preparation method of transistor arrangement,
Include the following steps：
1) semiconductor substrate with active area is provided, in forming groove structure, the ditch in the semiconductor substrate
Slot structure passes through the active area；
2) gate oxide is formed in the bottom of the groove structure and side wall, the gate oxide covers the groove structure
Bottom and side wall；
3) the first conductive material layer is formed in the gate oxide surface；
4) the second conductive material layer is formed in the first conductive material layer surface, second conductive material layer fills up institute
State groove structure；
5) part of etching removal for the first time first conductive material layer and part second conductive material layer so that institute
The upper surface of the upper surface and second conductive material layer of stating the first conductive material layer is below the upper of the semiconductor substrate
Surface；And
6) first conductive material layer and second conductive material layer are etched for the second time, to respectively obtain the first conduction
Layer and the second conductive layer, the used etching liquid of second of etching are more than to institute the etch rate of first conductive material layer
State the etch rate of the second conductive material layer, first conductive layer, second conductive layer and the common structure of the gate oxide
At buried gate word line structure；Wherein, second conductive layer includes the filling part for being incorporated into first conductive layer surface
And the lug boss on the filling part top, the top of the lug boss are higher than the top of first conductive layer, and it is described
Between the outside side wall of any length of lug boss and the gate oxide have spacing, account for the groove structure same widths to
1%~50% of opening size under section.
As a kind of preferred embodiment of the utility model, the groove structure that is formed in step 1) is in width under section
Opening size between 10 nanometers~50 nanometers；The thickness of the gate oxide formed in step 2) is received between 1 nanometer~9
Rice；In step 6), the height of the lug boss between 1 nanometer~40 nanometers, the outside side wall of length of the lug boss with it is described
Spacing between gate oxide is between 0.8 nanometer~5 nanometers.
As a kind of preferred embodiment of the utility model, first conductive material layer includes titanium nitride (TiN) layer, described
Second conductive material layer includes tungsten (W) metal wire.
As a kind of preferred embodiment of the utility model, in step 1), in forming the groove in the semiconductor substrate
The step of structure includes：
1-1) one layer of mask layer with window is formed in the semiconductor substrate surface, wherein the window definition goes out
The shape of the groove structure and position；And
1-2) semiconductor substrate is performed etching based on the window, to form the groove structure.
As a kind of preferred embodiment of the utility model, in step 5), by alternately dry etch process to described first
Conductive material layer and second conductive material layer perform etching, wherein the etching gas of the alternately etching includes lithium
Sulphur (SF6), chlorine (Cl2) and argon gas (Ar) constituted group in arbitrary two or three of combination.
Further include step after step 6) as a kind of preferred embodiment of the utility model：In shape in the groove structure
At filling perforation insulating layer, the filling perforation insulating layer covers the top of first conductive layer and coats the lug boss.
As a kind of preferred embodiment of the utility model, after step 6), in forming the filling perforation in the groove structure
Further include step before insulating layer：The surface of second conductive layer is cleaned using hydrofluoric acid weak solution (DHF) reagent
To remove surface by-product, wherein the DHF
Reagent includes the mixed liquor of hydrofluoric acid (HF) and water, and the molar ratio of hydrofluoric acid and water is in 1 ratio in the mixed liquor
50~1000.
As a kind of preferred embodiment of the utility model, in step 6), the etching liquid is to first conductive material layer
And the etch rate ratio of second conductive material layer is between 3 to 1 to 10 to 1.
As a kind of preferred embodiment of the utility model, the etching liquid includes ammonium hydroxide (NH4OH), hydrogen peroxide
(H2O2) and water：Wherein, the molar ratio of the ammonium hydroxide, the hydrogen peroxide and the water is 1 to 0.01~2 to 5~150；
The etching temperature of the etching liquid is between 4 DEG C~25 DEG C.
The utility model also provides a kind of transistor arrangement, including：
Semiconductor substrate has active area, is formed in the semiconductor substrate in groove structure, the groove structure is worn
Cross the active area；And
Buried gate word line structure is located in the groove structure, and the buried gate word line structure includes：
Gate oxide is located at the bottom and side wall of the groove structure；
First conductive layer is located at bottom and the partial sidewalls of the gate oxide, and the top of first conductive layer is low
In the upper surface of the semiconductor substrate；
Second conductive layer, second conductive layer include be filled in the lower part of the groove structure and surface covering described in
The filling part of first conductive layer and the lug boss on the filling part, wherein the top of the lug boss is higher than described
The top of first conductive layer and the upper surface for being less than the semiconductor substrate, the outside side wall of any length of the lug boss and institute
Stating has spacing between gate oxide, accounts for 1%~50% of the groove structure in same widths to the opening size under section.
As a kind of preferred embodiment of the utility model, the groove structure is situated between in width to the size of the opening under section
In 10 nanometers~50 nanometers；The thickness of the gate oxide is between 1 nanometer~9 nanometers；The height of the lug boss is between 1 nanometer
~40 nanometers, the spacing between the outside side wall of length of the lug boss and the gate oxide is between 0.8 nanometer~5 nanometers.
As a kind of preferred embodiment of the utility model, first conductive material layer includes titanium nitride (TiN) layer, described
Second conductive material layer includes tungsten (W) metal wire.
As a kind of preferred embodiment of the utility model, the width of the lug boss to cross sectional shape include polygon, circle
Shape, semicircle or elliposoidal.
As a kind of preferred embodiment of the utility model, the transistor arrangement further includes filling perforation insulating layer, is formed in institute
It states in groove structure, the filling perforation insulating layer covers the top of first conductive layer and coats the described of second conductive layer
Lug boss.
As a kind of preferred embodiment of the utility model, the transistor arrangement further includes：
Source electrode is passed through in the active area of the semiconductor substrate by two buried gate word line structures
Middle section, and positioned at the buried gate word line structure side；And
Drain electrode, is passed through in the active area of the semiconductor substrate by two buried gate word line structures
Side area, and be located at the other side of the buried gate word line structure far from the source electrode.
The utility model also provides a kind of memory cell array, has multiple storages for being configured to cell row and cell columns
Unit, the storage unit include the transistor arrangement as described in above-mentioned any one scheme, wherein the buried gate word
Cable architecture is connected to an addressed line, and the addressed line is for controlling the storage unit.
As a kind of preferred embodiment of the utility model, the storage unit further includes：
Embolism conductive layer, including dielectric layer and the first conductive plug and second in the dielectric layer and up and down
Conductive plug；Wherein, the dielectric layer is located at the upper surface of the semiconductor substrate；
Capacitance contact is located on the embolism conductive layer, and the bottom of the capacitance contact and first conductive plug
Top be in contact；
Bit line is located on the embolism conductive layer, and the top phase of the bottom of the bit line and second conductive plug
Contact.
The utility model also provides a kind of memory construction, includes the storage unit as described in above-mentioned any one scheme
Array.
As described above, the transistor and memory cell array of the utility model, in specific operation process, have has as follows
Beneficial effect：
1) transistor arrangement of the utility model is carried by the top by the top of the first conductive layer less than the second conductive layer
The high height of grid wordline, reduces the resistance of grid wordline, to reduce the access time of device；Meanwhile it changing
The distribution of grid wordline surrounding electric field, reduces the contact area of grid and source-drain electrode, increase P/N knot drain electrode between away from
From the electric field near grid being reduced, the phenomenon that reduce gate induced drain leakage current.
2) preparation method of the transistor arrangement of the utility model makes first by additional wet etching after dry etching
The top of conductive layer is less than the top of the second conductive layer, can effectively solve as semiconductor devices is decreased to certain size
Afterwards, it cannot achieve by dry etch process so that the problem of top of the first conductive layer is less than the top of the second conductive layer.
Description of the drawings
Fig. 1 is shown as the flow chart of the transistor arrangement preparation method provided in the utility model embodiment one.
Fig. 2 to Fig. 4 is shown as step 1) institute in the transistor arrangement preparation method provided in the utility model embodiment one
Partial cross section's structural schematic diagram of presentation.
Fig. 5 is shown as what step 2) in the transistor arrangement preparation method provided in the utility model embodiment one was presented
Partial cross section's structural schematic diagram.
Fig. 6 is shown as what step 3) in the transistor arrangement preparation method provided in the utility model embodiment one was presented
Partial cross section's structural schematic diagram.
Fig. 7 is shown as what step 4) in the transistor arrangement preparation method provided in the utility model embodiment one was presented
Partial cross section's structural schematic diagram.
Fig. 8 is shown as what step 5) in the transistor arrangement preparation method provided in the utility model embodiment one was presented
Partial cross section's structural schematic diagram.
Fig. 9 is shown as what step 6) in the transistor arrangement preparation method provided in the utility model embodiment one was presented
Partial cross section's structural schematic diagram.
Figure 10 is shown as forming filling perforation insulation in the transistor arrangement preparation method provided in the utility model embodiment one
The partial cross section's structural schematic diagram presented after layer.
Figure 11 is shown as forming source electrode and leakage in the transistor arrangement preparation method provided in the utility model embodiment one
The partial cross section's structural schematic diagram presented after extremely.
Figure 12 is shown as the dimensional structure diagram of the memory cell structure provided in the utility model embodiment three.
Reference numerals explanation
10 semiconductor substrates
11 active areas
12 isolation structures
13 mask layers
131 windows
14 groove structures
15 buried gate word line structures
151 gate oxides
152 first conductive material layers
1521 first conductive layers
153 second conductive material layers
1531 second conductive layers
1532 filling parts
1533 lug bosses
16 filling insulating layers
17 source electrodes
18 drain electrodes
191 dielectric layers
192 first conductive plugs
193 second conductive plugs
20 capacitance contacts
21 bit lines
211 bit line metals
212 isolated insulation layers
The size of the opening of d1 groove structures
D2 gate oxide thickness
The height of d3 lug bosses
Spacing between the lateral wall and gate oxide of d4 lug bosses
Specific implementation mode
Illustrate that the embodiment of the utility model, those skilled in the art can be by this theorys below by way of specific specific example
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific implementation modes are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
It please refers to Fig.1 to Figure 12.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can be a kind of random change
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the utility model provides a kind of preparation method of transistor arrangement, the preparation of the transistor arrangement
Method includes the following steps：
1) semiconductor substrate with active area is provided, in forming groove structure, the ditch in the semiconductor substrate
Slot structure passes through the active area；
2) gate oxide is formed in the bottom of the groove structure and side wall, the gate oxide covers the groove structure
Bottom and side wall；
3) the first conductive material layer is formed in the gate oxide surface；
4) the second conductive material layer is formed in the first conductive material layer surface, second conductive material layer fills up institute
State groove structure；
5) part of etching removal for the first time first conductive material layer and part second conductive material layer so that institute
The upper surface of the upper surface and second conductive material layer of stating the first conductive material layer is below the upper of the semiconductor substrate
Surface；And
6) first conductive material layer and second conductive material layer are etched for the second time, to respectively obtain the first conduction
Layer and the second conductive layer etch the etching liquid used and are more than the etch rate of first conductive material layer to described for the second time
The etch rate of second conductive material layer, first conductive layer, second conductive layer and the gate oxide collectively form
Buried gate word line structure；Wherein, second conductive layer include be incorporated into first conductive layer surface filling part and
Lug boss on the filling part top, the top of the lug boss are higher than the top of first conductive layer, and described convex
Rise portion the outside side wall of any length and the gate oxide between have spacing d4, account for the groove structure same widths to
1%~50% of opening size under section.
In step 1), the S1 steps in please referring to Fig.1 and Fig. 2 to Fig. 4 provide a semiconductor with active area 11 and serve as a contrast
Bottom 10, in forming groove structure 14 in the semiconductor substrate 10, the groove structure 14 passes through the active area 11.
Specifically, the material of the substrate 10 includes but not limited to monocrystalline or polycrystalline semiconductor material, in addition, the substrate
10 can also include the silicon substrate of intrinsic monocrystalline substrate either light dope, further, it is possible to be N-type polycrystalline silicon substrate
Or P type multicrystalline silicon substrates, in the present embodiment, the substrate 10 includes the substrate of P+ type polycrystalline silicon material.In addition, the lining
The resistivity of the material at bottom 10 is preferably between 2 × 10-8~1 × 102Between Ω m.
As an example, being formed with several isolation structures 12 being spaced apart, the interval in the semiconductor substrate 10
Structure 12 isolates several mutually isolated active areas 11 in the semiconductor substrate 10.The isolation structure 12
And the quantity of the active area 11 can be set according to actual needs, and the semiconductor substrate 10 is only provided in Fig. 2 to Fig. 4
Two interior isolation structures 12, the quantity of the isolation structure 12 is not in actual example, in the semiconductor substrate 10
As limit.
As an example, in step 1), include the following steps in forming groove structure 14 in the semiconductor substrate 10：
1-1) one layer of mask layer 13 with window 131 is formed in 10 surface of the semiconductor substrate, wherein the window
131 define the shape of the groove structure 14 to be formed and position, as shown in Figure 3；And
1-2) semiconductor substrate 10 is performed etching based on the window 131, to form the groove structure 14, such as
Shown in Fig. 4.The semiconductor is served as a contrast specifically, at least one of dry etch process and wet-etching technology may be used
Bottom 10 is performed etching to form the groove structure 14.
As an example, the cross sectional shape of the groove structure 14 can be U-shaped as shown in Figure 4.Certainly, in other implementations
In example, the cross sectional shape of the groove structure 14 can also be the arbitrary shape that rectangle, inverted trapezoidal etc. are applicable in device performance.
It should be noted that the quantity of the groove structure 14 formed in the active area 11 can be according to actual needs
It is set, Fig. 4 only provides the groove structure 14 to form two intervals in the active area 11 as an example, in reality
In example, the quantity of the groove structure 14 in the active area 11 is not limited.
As an example, the size (i.e. the width of the groove structure 14) of the opening of the groove structure 14 can be according to reality
Border is set, it is preferable that in the present embodiment, the groove structure 14 can to the size d1 of the opening under section in width
With between but be not limited only to 10 nanometers~50 nanometers.
Further include that removal is located at 10 table of the semiconductor substrate it should be noted that being formed after the groove structure 14
The step of mask layer 13 in face.Specifically, dry etch process or the wet-etching technology removal mask may be used
Layer 13.
In step 2), the S2 steps in please referring to Fig.1 and Fig. 5 are formed in the bottom of the groove structure 14 and side wall
Gate oxide 151, the gate oxide 151 cover bottom and the side wall of the groove structure 14.
Include the following steps as an example, forming gate oxide 151 in the bottom of the groove structure 14 and side wall：
2-1) in the bottom and side wall deposition gate oxidation material of the surface of the semiconductor substrate 10 and the groove structure 14
Bed of material (not shown), the gate oxide material layer cover the surface of the semiconductor substrate 10 and the bottom of the groove structure 14
And side wall；
The gate oxide material layer for 2-2) removing 10 surface of semiconductor substrate, is retained in the groove structure 14
The gate oxide material layer of bottom and side wall is the gate oxide 151.
Specifically, the material of the gate oxide 151 can be but not limited to silica, the silica can be to include
Silicon monoxide or silica, and the resistivity of material is preferably between 2 × 1011~1 × 1025Between Ω m, the gate oxide
151 can be by atomic deposition processing procedure (Atomic Layer Deposition), plasma vapor deposition (Chemical Vapor
Deposition) film, quick heated oxide (Rapid Thermal Oxidation) or steam (in-situ in situ
Stream generation, ISSG) technique prepare and formed.Preferably, in the present embodiment, the gate oxide 151 uses
Prepared by steam technique in situ, a large amount of gas-phase activity free radical is generated in preparation, takes part in the oxidation of silicon chip, so as to obtain
The few film of defect.
As an example, the thickness d 2 of the gate oxide 151 can between but be not limited only between 1nm~9nm.
In step 3), it is conductive to form first in 151 surface of the gate oxide by the S3 steps in please referring to Fig.1 and Fig. 6
Material layer 152.
As an example, the techniques such as plating, chemical vapor deposition, physical vapour deposition (PVD) or atomic layer deposition may be used in institute
It states 151 surface of gate oxide and forms first conductive material layer 152.The material of first conductive material layer 152 can wrap
It includes but is not limited only to titanium nitride.
As an example, first conductive material layer 152 can be covered in the table of the semiconductor substrate 10 as shown in Figure 6
Face and the surface of the gate oxide 151 can also be gone after forming first conductive material layer 152 as shown in FIG. 6
Except first conductive material layer 152 positioned at 10 surface of the semiconductor substrate, only retains and be located in the groove structure 14
First conductive material layer 152 on 151 surface of the gate oxide.
In step 4), the S4 steps in please referring to Fig.1 and Fig. 7 form the in 152 surface of the first conductive material layer
Two conductive material layers 153, second conductive material layer 153 fill up the groove structure 14.
As an example, the techniques such as plating, chemical vapor deposition, physical vapour deposition (PVD) or atomic layer deposition may be used in institute
It states 152 surface of the first conductive material layer and forms second conductive material layer 153.Second is conductive described in same etching processing procedure
The etch rate of material layer 153 is less than the etch rate of first conductive material layer 152, it is preferable that described in the present embodiment
The material of second conductive material layer 153 may include but be not limited only to tungsten, be more highly preferred to, second conductive material layer 153
Including tungsten metal wire.
As an example, second conductive material layer 153 can be covered in as shown in Figure 7 positioned at the semiconductor substrate 10
On first conductive material layer 152 surface and first conductive material layer 152 in the groove structure 14
Surface, can also formed first conductive material layer 152 as shown in Figure 7 and second conductive material layer 153 it
First conductive material layer 152 and second conductive material layer 153 of the removal positioned at 10 surface of the semiconductor substrate afterwards,
Only retain and is located at first conductive material layer 152 on 151 surface of the gate oxide in the groove structure 14 and is located at institute
State second conductive material layer 153 on 152 surface of the first conductive material layer in groove structure 14.
It should be noted that when second conductive material layer 153 and first conductive material layer 152 are from the ditch
Further include that removal is located at the semiconductor substrate when extending to 10 surface of semiconductor substrate in slot structure 14, after step 4)
First conductive material layer 152 on 10 surfaces and second conductive material layer 153.Specifically, chemical machine may be used
Tool planarizes (Chemical-Mechanical Planarization, CMP) to described the of 10 surface of the semiconductor substrate
One conductive material layer 152 and second conductive material layer 153.
In step 5), the S5 steps in please referring to Fig.1 and Fig. 8, part first conduction material of etching removal for the first time
The bed of material 152 and part second conductive material layer 153 so that the upper surface of first conductive material layer 152 and described
The upper surface of two conductive material layers 153 is below the upper surface of the semiconductor substrate 10.
As an example, by alternately dry etch process to first conductive material layer 152 and second conduction material
The bed of material 153 performs etching,.It can be as shown in figure 8, after by alternately dry etch process, to be retained in the groove structure 14
The top of interior first conductive material layer 152 and second conductive material layer 153 can be with flush, certainly, at other
In example, pass through first conductive material layer 152 after alternately dry etch process, being retained in the groove structure 14
And the top of second conductive material layer 153 can also have it is at regular intervals；Preferably, in the present embodiment, alternately dry method is crossed
After etching technics, first conductive material layer 152 and second conductive material that are retained in the groove structure 14
The top of layer 153 can be with flush, in order to the control of subsequent technique.
Specifically, can alternately be passed through has first conductive material layer 152 and second conductive material layer 153
Alternately etching is carried out to the two without the etching gas of etch rate, wherein the etching gas of the alternately etching includes hexafluoro
Change sulphur (SF6), chlorine (Cl2) and argon gas (Ar) constituted group in arbitrary two or three of combination.It is led with described first
Material layer 152 is titanium nitride, second conductive material layer 153 is tungsten as an example, etching gas uses SF6/Cl2, pass through
Flow proportional or a other etching period are adjusted to perform etching.
In step 6), the S6 steps in please referring to Fig.1 and Fig. 9, etch for the second time first conductive material layer 152 and
Second conductive material layer 153, to respectively obtain the first conductive layer 1521 and the second conductive layer 1531, second of etching is made
Etching liquid is more than the etch rate of first conductive material layer 152 etching to second conductive material layer 153
Rate, first conductive layer 1521, second conductive layer 1531 and the gate oxide 151 collectively form buried gate
Word line structure 15；Wherein, second conductive layer 1531 includes the filling part for being incorporated into 1521 surface of the first conductive layer
1532 and positioned at the filling part 1532 top on lug boss 1533, the top of the lug boss 1533 is led higher than described first
The top of electric layer 1521, and between having between the outside side wall of any length and the gate oxide 151 of the lug boss 1533
Away from d4, the spacing accounts for 1%~50% of the groove structure 14 in same widths to the opening size d1 under section.
As an example, the outside side wall of any length of the height of the lug boss 1533 and the lug boss 1533 with it is described
Spacing between gate oxide 151 can be set according to actual needs, it is preferable that in the present embodiment, the lug boss
1533 height d3 is between 1 nanometer~40 nanometers, the outside side wall of any length and the gate oxide of the lug boss 1533
Spacing d4 between 151 is between 0.8 nanometer~5 nanometers.
Due to the spacing between the outside side wall of any length of the lug boss 1533 after etching and the gate oxide 151
D4 is very small, only between 0.8 nanometer~5 nanometers, using existing dry etch process can not, therefore in the present embodiment use wet method
Etching technics is more than using the etch rate to first conductive material layer 152 to second conductive material layer 153
The etching liquid of etch rate etches first conductive material layer 152 and second conductive material layer 153, after ensuring etching
The size that second conductive material layer 153 is removed is much smaller than the size that first conductive material layer 152 is removed.Specifically
, the etching liquid can be to the etch rate ratio of first conductive material layer 152 and second conductive material layer 153
But it is not limited only to 3:1~10:1.
As an example, the etching liquid is APM reagents, the APM reagents include ammonium hydroxide (NH4OH), hydrogen peroxide
(H2O2) and water.By adjusting the temperature of the concentration range and the APM reagents of each ingredient in the APM reagents, can improve pair
The etch rate of first conductive material layer 152, and reduce the etch rate to second conductive material layer 153, to
Obtain required structure.Preferably, in the etching liquid, the molar ratio packet of the ammonium hydroxide, the hydrogen peroxide and the water
Include 1 to 0.01~2 to 5~150；The etching temperature of the etching liquid is between 4 DEG C~25 DEG C；It is further preferable that this implementation
In example, in the etching liquid, the molar ratio of the ammonium hydroxide, the hydrogen peroxide and the water includes 1:1:50；The etching
The etching temperature of liquid includes 15 DEG C.
In addition, it should also be noted that, using the technical solution of the utility model, since first conductive layer 1521 is straight
The surface for being formed in the gate oxide 151 is connect, therefore, first conductive layer 1521 is as functional structure layer (work
Function), the threshold voltage vt of device architecture is determined, meanwhile, second be formed in inside first conductive layer 1521
Conductive layer 1531 has the function of current lead-through, since it may include protrude from first conductive layer 1521 described convex
Portion 1533 is played, then its height there can be more flexible selection, so as to reduce the resistance in transistor, it is ensured that small leakage
The resistance for reducing transistor while electric current, in addition, first conductive layer 1521 is also used as second conductive layer
1531 diffusion impervious layer.First conductive layer 1521 and second conductive layer 1531 are both used as grid, are also used as wordline,
The grid word line structure of this flush type can save device space, reduce device size, improve device speed.
Further include following steps as an example, after step 6)：Using DHF (hydrofluoric acid weak solution) reagents to described
The surface of two conductive layers 1531 is cleaned to remove surface by-product, wherein the DHF reagents include hydrofluoric acid (HF) and
The mixed liquor of water, the molar ratio of hydrofluoric acid and water includes 1 in the mixed liquor:50~1000.
Specifically, using DHF reagents so as to remove the oxide layer formed by oxidation in operation process, as formed
WO, to reduce the impedance of word line structure.Preferably, the molar ratio of hydrofluoric acid (HF) and water includes 1 in the mixed liquor:
(100~500) preferably include 1 in this example:300.
As an example, as shown in Figure 10, after being cleaned to the surface of second conductive layer 1531 using DHF reagents
Further include following steps：Form filling perforation insulating layer 16 in the groove structure 14, the filling perforation insulating layer 16 covers described the
The top of one conductive layer 1521 simultaneously coats the lug boss 1533.
As an example, the material of the filling perforation insulating layer 16 can be to include oxide (for example, silica, Al2O3、HfO2
Deng), any suitable insulating materials including silicon nitride and silicon oxynitride etc., be not limited herein.
As an example, as shown in figure 11, after forming the filling perforation insulating layer 16 in the groove structure 14, further including
By ion implantation technology in being respectively formed source electrode 17 in the active area 11 of 15 both sides of buried gate word line structure
And the step of drain electrode 18.
The transistor arrangement of the preparation of the utility model by the top of first conductive layer 1521 by being less than institute
The top for stating the second conductive layer 1531 improves the height of the grid word line structure 15, reduces the grid word line structure
15 resistance, to reduce the access time of device；Meanwhile changing point of 15 surrounding electric field of grid word line structure
Cloth reduces the contact area of grid and the source-drain electrode, increases the distance between P/N knots and the drain electrode 18, reduces
Electric field near the grid, the phenomenon that reduce the gate induced drain leakage.
Embodiment two
Please continue to refer to Figure 11, the utility model also provides transistor arrangement in technique, and the transistor arrangement can be adopted
It is prepared with the preparation method described in embodiment one, the transistor arrangement includes：Semiconductor substrate 10, groove structure
14, buried gate word line structure 15, the semiconductor substrate 10 have active area 11, institute are formed in the groove structure 14
It states in semiconductor substrate 10, the groove structure 14 passes through the active area 11；The buried gate word line structure 15 is located at
In the groove structure 14, the buried gate word line structure 15 includes：Gate oxide 151, the gate oxide 151 are located at
The bottom and side wall of the groove structure 14；First conductive layer 1521, first conductive layer 1521 are located at the gate oxide
151 bottom and partial sidewalls, and the top of first conductive layer 1521 is less than the upper surface of the semiconductor substrate 10；The
Two conductive layers 1531, second conductive layer 1531 include be filled in the lower part of the groove structure 14 in and surface cover described in
The filling part 1532 of first conductive layer 1521 and the lug boss 1533 on the filling part 1532, wherein the protrusion
Top of the top in portion 1533 higher than first conductive layer 151 and the upper surface less than the semiconductor substrate 10, it is described convex
Rising between the outside side wall of any length and the gate oxide 151 in portion 1533 has spacing, and the spacing accounts for the groove knot
Structure 14 is in same widths to 1%~50% of the opening size under section.
As an example, the material of the substrate 10 includes but not limited to monocrystalline or polycrystalline semiconductor material, in addition, the lining
Bottom 10 can also be the silicon substrate of intrinsic monocrystalline substrate either light dope, further, it is possible to be N-type polycrystalline silicon substrate
Or P type multicrystalline silicon substrates, in the present embodiment, the substrate 10 is the substrate of P+ type polycrystalline silicon material.In addition, the substrate
The resistivity of 10 material is preferably 2 × 10-8~1 × 102Ωm。
As an example, being formed with several isolation structures 12 being spaced apart, the interval in the semiconductor substrate 10
Structure 12 isolates several mutually isolated active areas 11 in the semiconductor substrate 10.The isolation structure 12
And the quantity of the active area 11 can be set according to actual needs, only be provided in the semiconductor substrate 10 in Figure 11
Two isolation structures 12, in actual example, the quantity of the isolation structure 12 is not with this in the semiconductor substrate 10
It is limited.
As an example, the size (i.e. the width of the groove structure 14) of the opening of the groove structure 14 can be according to reality
Border is set, it is preferable that in the present embodiment, the size d1 of the opening of the groove structure 14 can between but not only limit
In 10 nanometers~50 nanometers.
The material of the gate oxide 151 can be but not limited to silica, the silica can be silicon monoxide or
Silica, and the resistivity of material is preferably between 2 × 1011~1 × 1025Between Ω m, the thickness d 2 of the gate oxide 151
Can between but be not limited only between 1nm to 9nm.
As an example, the material of first conductive layer 1521 may include but be not limited only to titanium nitride；Described second leads
The material of electric layer 1531 may include but be not limited only to tungsten.
As an example, the lateral wall of the height of the lug boss 1533 and the lug boss 1533 and the gate oxide
Spacing between 151 can be set according to actual needs, it is preferable that in the present embodiment, the height of the lug boss 1533
Between between 1 nanometer~40 nanometers, the outside side wall of random length and the gate oxide 151 of the lug boss 1533
Away between 0.8 nanometer~5 nanometers.
As an example, the width of the lug boss 1533 to cross sectional shape include polygon, circle, semicircle or ellipsoid
Shape.
As an example, the transistor arrangement further includes filling perforation insulating layer 16, the filling perforation insulating layer 16 covers described
The top of one conductive layer 1521 simultaneously coats the lug boss 1533.The material of the filling perforation insulating layer 16 can be include oxide
(for example, silica, Al2O3、HfO2Deng), any suitable insulating materials including silicon nitride and silicon oxynitride etc., do not do herein
Limitation.
As an example, the transistor arrangement further includes：Source electrode 17 and drain electrode 18；The source electrode 17 is located at the semiconductor
The middle section passed through by two buried gate word line structures 15 in the active area 11 of substrate 10, and positioned at described
The side of buried gate word line structure 15；The drain electrode 18 is located in the active area 11 of the semiconductor substrate 10 by two
The side area that buried gate word line structure 15 passes through described in item, and positioned at the buried gate word line structure 15 far from institute
State the other side of source electrode 17.
The transistor arrangement of the utility model by the top of first conductive layer 1521 by being less than described second
The top of conductive layer 1531 improves the height of the grid word line structure 15, reduces the electricity of the grid word line structure 15
Resistance, to reduce the access time of device；Meanwhile the distribution of 15 surrounding electric field of grid word line structure is changed, reduce
The contact area of grid and the source-drain electrode increases the distance between P/N knots and the drain electrode 18, reduces the grid
Neighbouring electric field, the phenomenon that reduce the gate induced drain leakage.
Embodiment three
The utility model also provides a kind of preparation method of memory cell array, the preparation method of the memory cell array
Include the following steps：
1) multiple storage units with the transistor arrangement are formed, and each storage unit is configured with list
The memory cell array of first row and cell columns；Wherein, the buried gate wordline is used such as institute in above-mentioned any one scheme
The preparation method for the transistor arrangement stated is prepared, transistor arrangement buried gate wordline the most；
2) flush type of each storage unit in an addressed line to the cell row or the cell columns is connected
Grid wordline, the addressed line is for controlling the storage unit.
Specifically, as shown in figure 12, the storage unit formed in step 1) is in addition to including described in embodiment two
Except transistor arrangement, further include：Embolism conductive layer, capacitance contact 20 and bit line 21, the embolism conductive layer includes dielectric layer
191 and in the dielectric layer 191 and the first conductive plug 192 up and down and the second conductive plug 193；Wherein, institute
State the upper surface that dielectric layer 191 is located at the semiconductor substrate 10；The lower surface of first conductive plug 192 and the drain electrode
18 top and the top of the buried gate word line structure 15 are in contact；The lower surface of second conductive plug 193 with
The top of the source electrode 17 is in contact；The capacitance contact 20 is located on the embolism conductive layer, and the capacitance contact 20
Bottom is in contact with the top of first conductive plug 192；The bit line 21 is located on the embolism conductive layer, and institute's rheme
The bottom of line 21 is in contact with the top of second conductive plug 193；Specifically, the bit line 21 includes bit line metal 211
And coat the isolated insulation layer 212 of the bit line metal 211, wherein the bit line metal 211 and second conductive plug
193 top is in contact.
Example IV
Please continue to refer to Figure 12, the utility model also provides a kind of memory cell array, and the memory cell array has
Multiple storage units for being configured to cell row and cell columns, the storage unit include the transistor as described in embodiment two
Structure, wherein the buried gate word line structure is connected to an addressed line, and the addressed line is single for controlling the storage
Member.
As an example, specifically, as shown in figure 12, the storage unit further includes：Embolism conductive layer, capacitance contact 20 and
Bit line 21, the embolism conductive layer include dielectric layer 191 and the first conductive plugs interior positioned at the dielectric layer 191 and up and down
Plug 192 and the second conductive plug 193；Wherein, the dielectric layer 191 is located at the upper surface of the semiconductor substrate 10；Described
The lower surface of one conductive plug 192 connects with the top on the top of the drain electrode 18 and the buried gate word line structure 15
It touches；The lower surface of second conductive plug 193 is in contact with the top of the source electrode 17；The capacitance contact 20 is located at described
On embolism conductive layer, and the bottom of the capacitance contact 20 is in contact with the top of first conductive plug 192；The bit line
21 are located on the embolism conductive layer, and the bottom of the bit line 21 is in contact with the top of second conductive plug 193；Tool
Body, the bit line 21 includes bit line metal 211 and coats the isolated insulation layer 212 of the bit line metal 211, wherein described
Bit line metal 211 is in contact with the top of second conductive plug 193.
Embodiment five
The utility model also provides a kind of preparation method of memory construction, and the preparation method of the memory construction includes
The preparation process of the preparation method of memory cell array described in embodiment three.
Embodiment six
The utility model also provides a kind of memory construction, and the memory construction includes the storage described in example IV
Cell array.
In conclusion a kind of transistor of the utility model offer and memory cell array, include the following steps：1) one is provided
Semiconductor substrate with active area, in forming groove structure in the semiconductor substrate, the groove structure has across described
Source region；2) gate oxide is formed in the bottom of the groove structure and side wall, the gate oxide covers the groove structure
Bottom and side wall；3) the first conductive material layer is formed in the gate oxide surface；4) in the first conductive material layer surface
The second conductive material layer is formed, second conductive material layer fills up the groove structure；5) the part institute of etching removal for the first time
State the first conductive material layer and part second conductive material layer so that the upper surface of first conductive material layer and described
The upper surface of second conductive material layer is below the upper surface of the semiconductor substrate；And 6) described first is etched for the second time
Conductive material layer and second conductive material layer, to respectively obtain the first conductive layer and the second conductive layer, second of etching institute
The etching liquid used is more than the etch rate to second conductive material layer to the etch rate of first conductive material layer,
First conductive layer, second conductive layer and the gate oxide collectively form buried gate word line structure；Wherein, institute
It includes the filling part for being incorporated into first conductive layer surface and the lug boss on the filling part top to state the second conductive layer,
The top of the lug boss be higher than first conductive layer top, and the outside side wall of any length of the lug boss with it is described
There is spacing between gate oxide, account for the 1%~50% of opening size of the groove structure under same widths section.This reality
With novel transistor arrangement by the top by the top of the first conductive layer less than the second conductive layer, grid wordline is improved
Highly, the resistance for reducing grid wordline, to reduce the access time of device；Meanwhile it changing electric around grid wordline
The distribution of field, reduces the contact area of grid and source-drain electrode, increases the distance between P/N knots and drain electrode, reduces grid
Neighbouring electric field, the phenomenon that reduce gate induced drain leakage current；The preparation side of the transistor arrangement of the utility model
Method makes the top of the first conductive layer be less than the top of the second conductive layer by additional wet etching after dry etching, can be effective
It solves after being decreased to certain size with semiconductor devices, is cannot achieve by dry etch process so that the first conductive layer
Top be less than the second conductive layer top the problem of.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.
Claims (9)
1. a kind of transistor arrangement, which is characterized in that including：
Semiconductor substrate has active area, is formed in the semiconductor substrate in groove structure, and the groove structure passes through institute
State active area；And
Buried gate word line structure is located in the groove structure, and the buried gate word line structure includes：
Gate oxide is located at the bottom and side wall of the groove structure；
First conductive layer is located at bottom and the partial sidewalls of the gate oxide, and the top of first conductive layer is less than institute
State the upper surface of semiconductor substrate；And
Second conductive layer, second conductive layer include be filled in the lower part of the groove structure and surface covering described first
The filling part of conductive layer and the lug boss on the filling part, wherein the top of the lug boss is higher than described first
The top of conductive layer and the upper surface for being less than the semiconductor substrate, the outside side wall of any length and the grid of the lug boss
There is spacing between oxide layer, account for 1%~50% of the groove structure in same widths to the opening size under section.
2. transistor arrangement according to claim 1, which is characterized in that the groove structure is in width to opening under section
Mouth size is between 10 nanometers~50 nanometers；The thickness of the gate oxide is between 1 nanometer~9 nanometers；The height of the lug boss
Spacing between 1 nanometer~40 nanometers, the outside side wall of length of the lug boss and the gate oxide is between 0.8 nanometer
~5 nanometers.
3. transistor arrangement according to claim 1, which is characterized in that first conductive layer includes titanium nitride (TiN)
Layer, second conductive layer includes tungsten (W) metal wire.
4. transistor arrangement according to claim 1, which is characterized in that the width of the lug boss includes to cross sectional shape
Polygon, circle, semicircle or elliposoidal.
5. transistor arrangement according to claim 1, which is characterized in that the transistor arrangement further includes filling perforation insulation
Layer, is formed in the groove structure, the filling perforation insulating layer covers the top of first conductive layer and coats described second
The lug boss of conductive layer.
6. transistor arrangement according to any one of claim 1 to 5, which is characterized in that the transistor arrangement also wraps
It includes：
Source electrode, in being passed through by two buried gate word line structures in the active area of the semiconductor substrate
Region is entreated, and positioned at the side of the buried gate word line structure；And
Drain electrode, the side passed through by two buried gate word line structures in the active area of the semiconductor substrate
Border region, and it is located at the other side of the buried gate word line structure far from the source electrode.
7. a kind of memory cell array, which is characterized in that have multiple storage units for being configured to cell row and cell columns, institute
It includes transistor arrangement as described in claim 1 to state storage unit, wherein the buried gate word line structure is connected to one
Addressed line, the addressed line is for controlling the storage unit.
8. memory cell array according to claim 7, which is characterized in that the storage unit further includes：
Embolism conductive layer, including dielectric layer and the first conductive plug in the dielectric layer and up and down and the second conduction
Embolism；Wherein, the dielectric layer is located at the upper surface of the semiconductor substrate；
Capacitance contact is located on the embolism conductive layer, and the top of the bottom of the capacitance contact and first conductive plug
End is in contact；And
Bit line is located on the embolism conductive layer, and the bottom of the bit line is in contact with the top of second conductive plug.
9. a kind of memory construction, which is characterized in that including memory cell array as claimed in claim 7.
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| CN201721686101.4U CN207852674U (en) | 2017-12-07 | 2017-12-07 | transistor and memory cell array |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109817621A (en) * | 2019-03-22 | 2019-05-28 | 贵州大学 | A kind of memory construction based on Mg2Si semiconductor material |
| CN110895954A (en) * | 2018-09-13 | 2020-03-20 | 长鑫存储技术有限公司 | Memory word line driver structure with symmetrical path and forming method thereof |
| CN111354676A (en) * | 2018-12-24 | 2020-06-30 | 夏泰鑫半导体(青岛)有限公司 | Method for forming oxide structure |
| CN113078113A (en) * | 2020-01-03 | 2021-07-06 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113270405A (en) * | 2020-02-14 | 2021-08-17 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN116648062A (en) * | 2021-07-08 | 2023-08-25 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
| US12069850B2 (en) | 2020-10-15 | 2024-08-20 | Changxin Memory Technologies, Inc. | Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110895954A (en) * | 2018-09-13 | 2020-03-20 | 长鑫存储技术有限公司 | Memory word line driver structure with symmetrical path and forming method thereof |
| CN110895954B (en) * | 2018-09-13 | 2024-05-17 | 长鑫存储技术有限公司 | Memory word line driver structure with symmetrical paths and method of forming the same |
| CN111354676A (en) * | 2018-12-24 | 2020-06-30 | 夏泰鑫半导体(青岛)有限公司 | Method for forming oxide structure |
| CN111354785A (en) * | 2018-12-24 | 2020-06-30 | 夏泰鑫半导体(青岛)有限公司 | Method for forming oxide structure |
| CN109817621A (en) * | 2019-03-22 | 2019-05-28 | 贵州大学 | A kind of memory construction based on Mg2Si semiconductor material |
| CN113078113A (en) * | 2020-01-03 | 2021-07-06 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113270405A (en) * | 2020-02-14 | 2021-08-17 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| US12069850B2 (en) | 2020-10-15 | 2024-08-20 | Changxin Memory Technologies, Inc. | Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer |
| CN116648062A (en) * | 2021-07-08 | 2023-08-25 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
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