CN110047840A - 3D nand flash memory and preparation method - Google Patents
3D nand flash memory and preparation method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of 3D nand flash memory and preparation method, includes the following steps: to provide semiconductor substrate, laminated construction is formed in semiconductor substrate, including the sacrificial layer and grid layer being alternately superimposed on；In formation channel through-hole in laminated construction；Channel through-hole includes several recess regions between neighboring gates layer and between grid layer and semiconductor substrate；Function side wall is formed in the sidewall surfaces of channel through-hole, and forms channel layer in the surface of function side wall and the bottom of channel through-hole；In forming gate pitch in laminated construction；Sacrificial layer is removed based on gate pitch；Dielectric layer between grid is formed between neighboring gates layer and between grid layer and semiconductor substrate, dielectric layer includes the first electric leakage inhibition layer being alternately superimposed on and the second electric leakage inhibition layer between grid.The present invention can effectively reduce the electric leakage between neighboring gates layer, improve the breakdown characteristics of dielectric layer between the grid between neighboring gates layer, reduce the coupling effect between neighboring gates layer.
Description
Technical field
The invention belongs to IC design and manufacturing technology fields, more particularly to a kind of 3D nand flash memory and preparation
Method.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid, and flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
The stacked structure of existing 3D nand flash memory is replaced by dielectric layer between stacked gate layer (i.e. grid word line layer) and grid
It is stacked to form.With the development of technique, in order to meet highdensity requirement, 3D nand flash memory (is put down in XY in addition to unit size
The size in face) it corresponds to except diminution therewith, the quantity (quantity i.e. on the Z-direction perpendicular to the X/Y plane) of grid layer
It need to dramatically increase therewith.Simultaneously as the limitation of etching technics, the overall thickness of the vertical structure in 3D nand flash memory is (i.e. vertical
Size of the structure in the Z-direction) it needs to reduce, this requires the thickness of dielectric layer between the thickness of grid layer and grid is corresponding
Reduce；However, due between the grid in existing 3D nand flash memory dielectric layer be generally homogenous material layer, for example silica
(SiO2) layer, the thinner thickness of dielectric layer easily causes the electric leakage between neighboring gates layer between grid, or even causes neighboring gates
Dielectric layer is breakdown between grid between layer.
In addition, existing 3D nand flash memory is when being programmed a certain grid layer, because of the grid programmed
The fringe field of the program voltage applied on layer can make between the grid layer programmed and grid layer adjacent thereto
The accumulation layer in region is programmed out a small amount of charge, this Partial charge will cause the grid mutually closed on the grid layer programmed
The threshold voltage shift of pole layer, that is, the grid layer programmed can cause layer coupling dry to the grid layer mutually closed on it
It disturbs.Further, concentration of electric charges highest in the region of accumulation layer face grid layer, accumulation layer correspond to grid layer and grid layer it
Between region in concentration of electric charges it is minimum, then charge in the region of accumulation layer face grid layer can because concentration gradient and to two
The accumulation layer regional diffusion (corresponding to the regional diffusion between grid layer and grid layer to accumulation layer) on side, to cause grid
The threshold voltage shift of layer has that charge is laterally lost in the accumulation layer in that is, existing 3D nand flash memory.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of 3D nand flash memory and preparations
Method, for solve in the prior art 3D nand flash memory as the reduction of thickness of dielectric layers between grid easily causes neighboring gates
Electric leakage between layer, or even the problem that dielectric layer is breakdown between the grid between neighboring gates layer is caused, it is adjacent in 3D nand flash memory
Interlayer coupled interference is stored between grid layer, thus the problem of causing the threshold voltage shift of grid layer and 3D nand flash memory
In accumulation layer in there are charge laterally be lost, thus the problem of causing the threshold voltage shift of grid layer.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of 3D nand flash memory, described
The preparation method of 3D nand flash memory includes the following steps:
Semiconductor substrate is provided, laminated construction is formed in the semiconductor substrate, the laminated construction includes alternately folded
The sacrificial layer and grid layer set；
In formation channel through-hole in the laminated construction；Include the following steps: vertical logical in being formed in the laminated construction
Hole；The part sacrificial layer is removed based on the vertical through-hole lateral etching, between the adjacent grid layer and the grid
Recess region is formed between pole layer and the semiconductor substrate；
Function side wall is formed in the sidewall surfaces of the channel through-hole, and in the surface of the function side wall and the channel
Channel layer is formed on the bottom of through-hole；The function side wall between the adjacent grid layer and be located at the grid layer with it is described
Being partially filled in the recess region between semiconductor substrate；
In forming gate pitch in the laminated construction；
The sacrificial layer is removed based on the gate pitch；And
Between the adjacent grid layer and between the grid layer and the semiconductor substrate formed grid between dielectric layer, institute
Dielectric layer includes the first electric leakage inhibition layer being alternately superimposed on and the second electric leakage inhibition layer between stating grid.
Optionally, the sidewall surfaces of Yu Suoshu channel through-hole form the function side wall and include the following steps:
Barrier layer is formed in the sidewall surfaces of the channel through-hole；
Accumulation layer is formed in the surface on the barrier layer, the accumulation layer is between the adjacent grid layer and positioned at institute
State being partially filled in the recess region between grid layer and the semiconductor substrate；And
Tunnel layer is formed in the surface of the accumulation layer.
Optionally, the barrier layer includes high-k dielectric layer and barrier laminate structure, and the high-k dielectric layer is located at the ditch
The surface of road through-hole, the barrier laminate structure are located at the surface of the high-k dielectric layer, and the barrier laminate structure includes along institute
State oxide skin(coating) and oxynitride layer that barrier laminate structural thickness direction is alternately superimposed on；The accumulation layer includes through-thickness
The nitride layer and oxynitride layer being alternately superimposed on；The tunnel layer includes the oxide skin(coating) and position that through-thickness is intervally arranged
Nitrogen oxides laminated construction between the oxide skin(coating).
Optionally, the channel through-hole runs through the laminated construction, and the gate pitch runs through the laminated construction.
It optionally, further include in shape in the channel through-hole after the surface of Yu Suoshu function side wall forms the channel layer
The step of at filling insulating layer.
Optionally, the grid are formed between the adjacent grid layer and between the grid layer and the semiconductor substrate
Between dielectric layer further include following steps:
In forming source region in the semiconductor substrate of the gate pitch bottom；And
In forming common source line in the gate pitch, the common source line is in contact with the source region.
Optionally, it is formed and is alternately superimposed in the upper surface of the semiconductor substrate while forming dielectric layer between the grid
The first electric leakage inhibition layer and the second electric leakage inhibition layer, shape in the semiconductor substrate of Yu Suoshu gate pitch bottom
It further include that removal is located at the grid at the source region later and before forming the common source line in the gate pitch
The step of first electric leakage inhibition layer and the second electric leakage inhibition layer of gap bottom.
Optionally, it is formed before the common source line in Yu Suoshu gate pitch, further includes in the gate pitch side wall shape
The step of at dielectric isolation layer.
Optionally, the first electric leakage inhibition layer includes oxide skin(coating), and the second electric leakage inhibition layer includes nitrogen oxides
Layer.
Optionally, the first electric leakage inhibition layer includes silicon oxide layer and the second electric leakage inhibition layer includes silicon oxynitride
Layer or the first electric leakage inhibition layer include hafnium oxide layer and the second electric leakage inhibition layer includes nitrogen oxidation hafnium layer.
Optionally, the grid are formed between the adjacent grid layer and between the grid layer and the semiconductor substrate
Between dielectric layer include the following steps:
The grid layer is carried out to the grid layer and carries out oxidation processes and nitrogen treatment, with the shape between the grid layer
At dielectric layer between the grid.
Optionally, dielectric layer further includes the air gap between the grid, and the air gap is located at first electric leakage and inhibits
In the structure that layer and the second electric leakage inhibition layer are alternately superimposed on.
The present invention also provides a kind of 3D nand flash memory, the 3D nand flash memory includes:
Semiconductor substrate；
Laminated construction is located in the semiconductor substrate, the laminated construction include between the grid being alternately superimposed on dielectric layer and
Grid layer；Between the grid dielectric layer include the air gap and be alternately superimposed on first electric leakage inhibition layer and second electric leakage inhibition layer,
The air gap is located in the structure that the first electric leakage inhibition layer and the second electric leakage inhibition layer are alternately superimposed on；
Channel through-hole is located in the laminated construction；The channel through-hole includes several recess regions, the groove area
Domain is between the adjacent grid layer and between the grid layer and the semiconductor substrate；
Function side wall, positioned at the sidewall surfaces of the channel through-hole, the function side wall be located at the adjacent grid layer it
Between and being partially filled in the recess region between the grid layer and the semiconductor substrate；And
Channel layer is located in the channel through-hole, and is located at the surface of the function side wall and the bottom of the channel through-hole
Portion.
Optionally, the function side wall includes:
Barrier layer, positioned at the sidewall surfaces of the channel through-hole；
Accumulation layer, positioned at the surface on the barrier layer, the accumulation layer is between the adjacent grid layer and positioned at institute
State being partially filled in the recess region between grid layer and the semiconductor substrate；And
Tunnel layer, positioned at the surface of the accumulation layer.
Optionally, the barrier layer includes high-k dielectric layer and barrier laminate structure, and the high-k dielectric layer is located at the ditch
The surface of road through-hole, the barrier laminate structure are located at the surface of the high-k dielectric layer, and the barrier laminate structure includes along institute
State oxide skin(coating) and oxynitride layer that barrier laminate structural thickness direction is alternately superimposed on；The accumulation layer includes through-thickness
The nitride layer and oxynitride layer being alternately superimposed on；The tunnel layer includes the oxide skin(coating) and position that through-thickness is intervally arranged
Nitrogen oxides laminated construction between the oxide skin(coating).
Optionally, the 3DNAND flash memory further include:
Gate pitch is located in the laminated construction, and the gate pitch is through the laminated construction and extends to described
In semiconductor substrate；
Source region is located in the semiconductor substrate, and is located at the bottom of the gate pitch；
Common source line is located in the gate pitch, and is connected with the source region；
Dielectric isolation layer is located in the gate pitch, and between the common source line and the laminated construction；
Insulating layer is filled, is filled in the channel through-hole, and is located at the surface of the channel layer.
Optionally, the first electric leakage inhibition layer includes oxide skin(coating), and the second electric leakage inhibition layer includes nitrogen oxides
Layer.
Optionally, the first electric leakage inhibition layer includes silicon oxide layer and the second electric leakage inhibition layer includes silicon oxynitride
Layer or the first electric leakage inhibition layer include hafnium oxide layer and the second electric leakage inhibition layer includes nitrogen oxidation hafnium layer.
As described above, 3D nand flash memory of the invention and preparation method, have the advantages that
Dielectric layer is including at least the first electric leakage inhibition layer being alternately superimposed on and the between grid in 3D nand flash memory of the present invention
Two electric leakage inhibition layers, can effectively reduce the electric leakage between neighboring gates layer, improve dielectric layer between the grid between neighboring gates layer
Breakdown characteristics, reduce neighboring gates layer between coupling effect；
Accumulation layer includes multiple protruding from neighboring gates along the thickness direction of laminated construction in 3D nand flash memory of the invention
Between the layer and protrusion part between grid layer and semiconductor substrate, protrusion part, which can mitigate, even prevents accumulation layer face grid
To the accumulation layer regional diffusion on both sides, i.e., protrusion part can mitigate even prevents in accumulation layer charge in the region of pole layer
Charge is lost along the transverse direction of laminated construction thickness direction, to mitigate the threshold voltage shift for even avoiding grid layer, it is ensured that 3D
The stability of nand flash memory performance；It, will not due to the presence of lobe portion meanwhile when being programmed to a certain layer grid layer
A small amount of charge is programed out between neighboring gates layer, to reduce the interlayer interference coupling between neighboring gates layer, and then is reduced
The threshold voltage shift of grid layer, it is ensured that the stability of the 3D nand flash memory performance.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one.
Fig. 2 is shown as step 1) resulting structures in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one
Cross section structure schematic diagram.
Fig. 3 and Fig. 4 is shown as in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one obtained by step 2)
The cross section structure schematic diagram of structure.
Fig. 5 to Fig. 9 is shown as in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one obtained by step 3)
The schematic diagram of structure；Wherein, Fig. 5 is that the cross section structure of the resulting structures after the sidewall surfaces formation function side wall of channel through-hole shows
It is intended to, Fig. 6 is shown as the partial enlargement structure chart on the barrier layer in function side wall, and Fig. 7 is shown as the accumulation layer in function side wall
Partial enlargement structure chart, Fig. 8 is shown as the partial enlargement structure chart of the tunnel layer in function side wall, and Fig. 9 is in function side wall
Surface and the channel through-hole bottom formed channel layer after resulting structures cross section structure schematic diagram.
Figure 10 is shown as in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one in shape in channel through-hole
At the cross section structure schematic diagram of resulting structures after filling insulating layer.
Figure 11 is shown as step 4) resulting structures in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one
Cross section structure schematic diagram.
Figure 12 is shown as step 5) resulting structures in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one
Cross section structure schematic diagram.
Figure 13 to Figure 16 is shown as step 6) institute in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one
Obtain the schematic diagram of structure；Wherein, Figure 13 and Figure 15 is the cross section structure schematic diagram of step 6) resulting structures in different examples, Figure 14
The structural schematic diagram of dielectric layer between the grid in Figure 13, Figure 16 are the structural schematic diagram of dielectric layer between the grid in Figure 15.
Figure 17 and Figure 18 is shown as step 7) institute in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one
Obtain the cross section structure schematic diagram of structure.
Figure 19 and Figure 20, which is shown as removing in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one, to be located at
The cross section structure schematic diagram of resulting structures after first electric leakage inhibition layer of gate pitch bottom and the second electric leakage inhibition layer.
Figure 21 and Figure 22 is shown as in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one between grid
The side wall of gap forms the cross section structure schematic diagram of resulting structures after dielectric isolation layer.
Figure 23 to Figure 25 is shown as step 8) institute in the preparation method of the 3D nand flash memory provided in the embodiment of the present invention one
Obtain the cross section structure schematic diagram of structure；Meanwhile Figure 23 and Figure 24 are also the section knot of the 3D nand flash memory provided in embodiment two
Structure schematic diagram；Figure 25 is the structural schematic diagram of dielectric layer between the grid in Figure 23.
Figure 26 is shown as the partial enlargement structure of function side wall barrier layer in the 3D flash memory provided in the embodiment of the present invention two
Figure.
Figure 27 is shown as the partial enlargement structure of function side wall accumulation layer in the 3D flash memory provided in the embodiment of the present invention two
Figure.
Figure 28 is shown as the partial enlargement structure of function side wall tunnel layer in the 3D flash memory provided in the embodiment of the present invention two
Figure.
Component label instructions
10 semiconductor substrates
11,31 laminated construction
111 sacrificial layers
12 channel through-holes
121 vertical through-holes
13 function side walls
131 barrier layers
131a high-k dielectric layer
131b barrier laminate structure
131c, 133a oxide skin(coating)
131d, 132b, 133c oxynitride layer
132 accumulation layers
132a nitride layer
133 tunnel layers
133b nitrogen oxides laminated construction
14 channel layers
15 gate pitch
Dielectric layer between 17 grid
17 ' electric leakages inhibit lamination
171 first electric leakage inhibition layers
172 second electric leakage inhibition layers
173 the air gaps
18 grid layers
19 filling insulating layers
20 source regions
21 common source lines
22 dielectric isolation layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
It should be noted that the basic conception that only the invention is illustrated in a schematic way is illustrated provided in the present embodiment,
Though only shown in diagram with it is of the invention in related component rather than component count, shape and size when according to actual implementation draw
System, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel can also
It can be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment also provides a kind of preparation method of 3D nand flash memory, the system of the 3D nand flash memory
Preparation Method includes the following steps:
1) semiconductor substrate is provided, laminated construction is formed in the semiconductor substrate, the laminated construction includes alternating
Stacked sacrificial layer and grid layer；
2) channel through-hole is formed in Yu Suoshu laminated construction；It is vertical in being formed in the laminated construction to include the following steps:
Through-hole；The part sacrificial layer is removed based on the vertical through-hole lateral etching, between the adjacent grid layer and described
Recess region is formed between grid layer and the semiconductor substrate；
3) sidewall surfaces of Yu Suoshu channel through-hole form function side wall, and in the surface of the function side wall and the ditch
Channel layer is formed on the bottom of road through-hole；The function side wall is between the adjacent grid layer and positioned at the grid layer and institute
State being partially filled in the recess region between semiconductor substrate；
4) gate pitch is formed in Yu Suoshu laminated construction；
5) sacrificial layer is removed based on the gate pitch；And
6) between the adjacent grid layer and between the grid layer and the semiconductor substrate formed grid between dielectric layer,
Dielectric layer includes the first electric leakage inhibition layer being alternately superimposed on and the second electric leakage inhibition layer between the grid.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, semiconductor substrate 10, the semiconductor substrate 10 are provided
On be formed with laminated construction 11, the laminated construction 11 includes the sacrificial layer 111 and grid layer 18 being alternately superimposed on.
As an example, the semiconductor substrate 10 can be selected according to the actual demand of device, the semiconductor lining
Bottom 10 may include silicon substrate, germanium (Ge) substrate, SiGe (SiGe) substrate, SOI (Silicon-on-insulator, insulation
Silicon on body) substrate or GOI (Germanium-on-Insulator, germanium on insulator) substrate etc.；Preferably, the present embodiment
In, the semiconductor substrate 10 includes monocrystalline silicon wafer crystal.
It should be noted that the semiconductor substrate 10 is the substrate carried out after ion doping, specifically, the semiconductor
Substrate 10 can be p-type doped substrate, or n-type doping substrate.
As an example, the material of the grid layer 18 may include metal (for example, tungsten or cobalt etc.) or silicon, it is preferable that
In the present embodiment, the material of the grid layer 18 may include DOPOS doped polycrystalline silicon (for example, the polysilicon of n-type doping or p-type doping
Polysilicon).
As an example, the sacrificial layer 111 can be selected compared to the grid layer 18 with higher etching for any one
The material of ratio is selected, for example, the material of the sacrificial layer 111 may include silicon nitride, silica or silicon oxynitride etc..
As an example, the laminated construction 11 may include the sacrificial layer 111 being successively alternately superimposed on from the bottom to top and
The grid layer 18, i.e., the bottom and top layer of the described laminated construction 11 are the sacrificial layer 111, positioned at the sacrifice of top layer
The upper surface of layer 111 is the upper surface of the laminated construction 11.
In step 2), the S2 step and Fig. 3 to Fig. 4 in Fig. 1 are please referred to, it is logical to form channel in Yu Suoshu laminated construction 11
Hole 12, the interior channel through-hole 12 that formed of Yu Suoshu laminated construction 11 include the following steps: in formation in the laminated construction 11 vertically
Through-hole 121；The part sacrificial layer 111 is removed based on vertical 121 lateral etching of through-hole, in the adjacent grid layer 18
Between and the grid layer 18 and the semiconductor substrate 10 between formed recess region 122.
As an example, step 2) may include steps of:
2-1) upper surface of Yu Suoshu laminated construction forms Patterned masking layer (not shown), in the Patterned masking layer
It is formed with the opening figure of the shape and position that define the vertical through-hole 121；
The laminated construction 11 2-2) is etched to form the vertical through-hole 121, such as Fig. 3 based on the Patterned masking layer
It is shown, specifically, the laminated construction 11 can be etched using dry etch process or wet-etching technology, it is preferable that this reality
It applies in example, the laminated construction 11 is etched using dry etch process；
The part sacrificial layer 111 2-3) is removed based on vertical 121 lateral etching of through-hole, in the adjacent grid
Recess region 122 is formed between layer 18 and between the grid layer 18 and the semiconductor substrate 10, as shown in Figure 4；Step 2-
3) the channel through-hole 12 obtained after is greater than in the width for corresponding to 111 part of sacrificial layer and corresponds to the grid layer 18
Partial width；Specifically, can using sacrificial layer 111 described in wet-etching technology lateral etching, specifically, can using pair
The sacrificial layer 111 has higher etching removal rate and the wet etching solution hardly etched to the grid layer 18 is horizontal
To the etching sacrificial layer 111；
2-4) remove the Patterned masking layer.
As an example, the channel through-hole 12 runs through the laminated construction 11 along the thickness direction of the laminated construction 11.
As an example, the quantity and distribution situation of the channel through-hole 12 can according to device architecture to be formed reality
Border is set, herein without limitation.
In step 3), the S3 step and Fig. 5 to Fig. 9 in Fig. 1, the sidewall surfaces shape of Yu Suoshu channel through-hole 12 are please referred to
Channel layer 14 is formed at function side wall 13, and in the surface of the function side wall 13 and the bottom of the channel through-hole 12；It is described
Function side wall 13 is between the adjacent grid layer 18 and between the grid layer 18 and the semiconductor substrate 10
It is partially filled in the recess region 122.
As an example, as shown in figure 5, the sidewall surfaces in the channel through-hole 12 form the function side wall 13 and can wrap
Include following steps:
3-1) sidewall surfaces of Yu Suoshu channel through-hole 12 form barrier layer 131；
3-2) surface on the barrier layer Yu Suoshu 131 forms accumulation layer 132, and the accumulation layer 132 is located at the adjacent grid
The recess region 122 is partially filled between layer 18 and between the grid layer 18 and the semiconductor substrate 10
It is interior；And
3-3) surface of Yu Suoshu accumulation layer 132 forms tunnel layer 133.
It should be noted that the function side wall 13 can be formed simultaneously sidewall surfaces and institute in the channel through-hole 12
State the bottom of channel through-hole 12；At this point, further including that removal is located at 12 bottom of channel through-hole after forming the function side wall 13
The step of function side wall 13 in portion, removal are located at institute after the function side wall 13 of 12 bottom of channel through-hole
The structure obtained is as shown in Figure 5.
It should be further noted that at least described accumulation layer 132 is filled in the function side wall 13 that step 3) obtains
In in the recess region 122, i.e., at least described accumulation layer 132 includes multiple protrusions along the thickness direction of the laminated construction 11
Protrusion part between the adjacent sacrificial layer 111 and between the sacrificial layer 111 and the semiconductor substrate 10；It is preferred that
Ground, in the present embodiment, the barrier layer 131, the accumulation layer 132 and the tunnel layer 133 are located at the adjacent sacrificial layer 111
Between and being partially filled in the recess region 122 between the sacrificial layer 111 and the semiconductor substrate 10, i.e.,
The barrier layer 131, the accumulation layer 132 and the tunnel layer 133 include multiple along the thickness direction of the laminated construction 11
The protrusion part between the adjacent sacrificial layer 111 and between the sacrificial layer 111 and the semiconductor substrate 10 is protruded from, such as
Shown in Fig. 5.
As an example, step 3-1) in, can using physical vapour deposition (PVD) (Physical Vapor Deposition,
PVD) technique, chemical vapor deposition (Chemical Vapor Deposition, CVD) technique or atomic layer deposition (Atomic
Layer Deposition, ALD) technique in the sidewall surfaces of the channel through-hole 12 forms the barrier layer 131；Preferably,
In the present embodiment, the barrier layer 131 is formed in the sidewall surfaces of the channel through-hole 12 using atom layer deposition process.
As an example, referring to Fig. 6, the barrier layer 131 may include high-k dielectric layer 131a and barrier laminate structure
131b；The high-k dielectric layer 131a is located at the surface of the channel through-hole 12, and the barrier laminate structure 131b is located at the height
The surface of k dielectric layer 131a；The barrier laminate structure 131b includes replacing along the barrier laminate structure 131b thickness direction
Stacked oxide skin(coating) 131c and oxynitride layer 131d.In the barrier laminate structure 131b, the oxide skin(coating) 131c and
The periodicity that the oxynitride layer 131d is alternately superimposed on can be set according to actual needs, herein without limitation；It is described
The sequence that oxide skin(coating) 131c and the oxynitride layer 131d are alternately superimposed on can be set according to actual needs, in Fig. 6
Only with the barrier layer 131 from the high-k dielectric layer 131a include outward the oxide skin(coating) 131c being successively alternately superimposed on and
The oxynitride layer 131d is as an example, only illustrate two layers of oxide skin(coating) 131c and one layer of nitrogen oxidation in Fig. 6
Nitride layer 131d, is not limited thereto in actual example.
As an example, the material of the high-k dielectric layer 131a may include aluminium oxide or hafnium oxide etc., the oxide layer
The material of 131c may include silica or hafnium oxide etc., and the material of the oxynitride layer 131d may include silicon oxynitride
Or nitrogen oxidation hafnium etc..
As an example, step 3-2) in, physical gas-phase deposition, chemical vapor deposition process or atomic layer can be used
Depositing operation forms the accumulation layer 132 in the surface on the barrier layer 131；Preferably, in the present embodiment, using atomic layer deposition
Product technique forms the accumulation layer 132 in the surface on the barrier layer 131.
As an example, referring to Fig. 7, the accumulation layer 132 includes the nitride layer 132a that through-thickness is alternately superimposed on
And oxynitride layer 132b；The sequence that the nitride layer 132a and the oxynitride layer 132b are alternately superimposed on can be according to reality
Border is set, and the periodicity that the nitride layer 132a and the oxynitride layer 132b are alternately superimposed on can be according to reality
Border is set, only outside including the successively alternate nitrogen from the barrier layer 131 with the accumulation layer 132 in Fig. 7
The compound layer 132a and oxynitride layer 132b as an example, and only illustrated in Fig. 7 three layers of nitride layer 132a and
Two layers of oxynitride layer 132b, is not limited thereto in actual example.
As an example, the material of the nitride layer 132a may include silicon nitride or hafnium nitride etc., the nitrogen oxidation
The material of nitride layer 132b may include silicon oxynitride or nitrogen oxidation hafnium etc..
In step 3-3), physical gas-phase deposition, chemical vapor deposition process or atomic layer deposition work can be used
Skill forms the tunnel layer 133 in the surface of the accumulation layer 132；Preferably, in the present embodiment, using atom layer deposition process
The tunnel layer 133 is formed in the surface of the accumulation layer 132.
As an example, referring to Fig. 8, the tunnel layer 133 may include the oxide skin(coating) that through-thickness is intervally arranged
133a and nitrogen oxides laminated construction 133b, the nitrogen oxides laminated construction 133b between the oxide skin(coating) 133a
The oxynitride layer 133c being stacked including multilayer along 133 thickness direction of tunnel layer.
As an example, the material of the nitride layer 133a may include silicon nitride or hafnium nitride etc., the nitrogen oxidation
The material of nitride layer 133c may include silicon oxynitride or nitrogen oxidation hafnium etc..
It should be noted that the number of plies of oxynitride layer 133c described in the nitrogen oxides laminated construction 133b can root
It is set according to actual needs, herein without limitation.
It should be further noted that each layer oxynitride layer 133c be not in the nitrogen oxides laminated construction 133b
Identical to the greatest extent, the atomic ratio of each element in each layer oxynitride layer 133c is not quite similar, for example, with the oxynitride layer
The material of 133c be silicon oxynitride as an example, nitrogen, oxygen and the atomic ratio of silicon three in each oxynitride layer 133c not
It is identical to the greatest extent.
As an example, can using physical gas-phase deposition, chemical vapor deposition process or atom layer deposition process in
The channel layer 14 is formed on the surface of the function side wall 13 and the bottom of the channel through-hole 12；Preferably, in the present embodiment,
The channel layer is formed in the surface of the function side wall 13 and the bottom of the channel through-hole 12 using atom layer deposition process
14, resulting structures are as shown in Figure 9 after forming the channel layer 14.
As an example, the material of the channel layer 14 may include polysilicon.Certainly, in other examples, the channel
The material of layer 14 can also be other semiconductor materials.
As an example, the sum of the thickness of the function side wall 13 and the channel layer 14 can be less than the channel through-hole 12
Width half, as shown in figure 5, at this point, forming after the channel layer 14 that also to remain with filling in the channel through-hole 12 exhausted
The reserved space of edge layer；In other examples, the channel layer 14 can also fill up the channel through-hole 12.
As an example, as shown in Figure 10, the surface of Yu Suoshu function side wall 13 forms the channel layer 14 and further includes later
In the step of forming filling insulating layer 19 in the channel through-hole 12.
As an example, can using physical gas-phase deposition, chemical vapor deposition process or atom layer deposition process in
The filling insulating layer 19 is formed in the channel through-hole 12；Preferably, in the present embodiment, using atom layer deposition process in institute
It states and forms the filling insulating layer 19 in channel through-hole 12.
As an example, the material of the filling insulating layer 19 may include oxide isolation layer, for example silica etc..It is described
Filling insulating layer 19 can fill up the channel through-hole 12.
In step 4), S4 step and Figure 11 in Fig. 1 are please referred to, forms gate pitch in Yu Suoshu laminated construction 11
15。
As an example, may include steps of in forming gate pitch 15 in the laminated construction 11:
4-1) upper surface of Yu Suoshu laminated construction 11 forms Patterned masking layer (not shown), the Patterned masking layer
Inside it is formed with the opening figure of the shape and position that define the gate pitch 15；
The laminated construction 11 4-2) is etched to form the gate pitch 15, specifically based on the Patterned masking layer
Ground can etch the laminated construction 11 using dry etch process or wet-etching technology, it is preferable that in the present embodiment, adopt
The laminated construction 11 is etched with dry etch process；
4-3) remove the Patterned masking layer.
As an example, the position of the gate pitch 15 and quantity can be set according to actual needs, do not do herein
It limits.
As an example, the gate pitch 15 can through the laminated construction 11 until the semiconductor substrate 10 it is upper
Surface, as shown in figure 11；Certainly, the gate pitch 15 may also extend through the laminated construction 11 and extend to the semiconductor
In substrate 10.
In step 5), S5 step and Figure 12 in Fig. 1 are please referred to, the sacrificial layer is removed based on the gate pitch 15
111。
As an example, the sacrificial layer 111 can be removed using wet-etching technology；It specifically, can be using to described
Sacrificial layer 111 has higher etching removal rate, and carries out to the wet etching solution that the grid layer 15 can hardly remove
Wet etching is to remove the sacrificial layer 111；Specifically, the wet etching solution is placed in the gate pitch 15, institute
Sacrificial layer 111 described in wet etching solution lateral encroaching is stated to completely remove the sacrificial layer 111.
In step 6), the S6 step and Figure 13 to Figure 16 in Fig. 1 are please referred to, between the adjacent grid layer 18 and institute
Dielectric layer 17 between forming grid between grid layer 18 and the semiconductor substrate 10 is stated, dielectric layer 17 includes being alternately superimposed between the grid
First electric leakage inhibition layer 171 and second electric leakage inhibition layer 172.
As an example, the first electric leakage inhibition layer 171 may include oxide skin(coating), the second electric leakage inhibition layer 172
It may include oxynitride layer.Specifically, the first electric leakage inhibition layer 171 may include silicon oxide layer or hafnium oxide layer, institute
Stating the second electric leakage inhibition layer 172 may include silicon oxynitride layer or nitrogen oxidation hafnium layer.
As an example, oxidation processes and nitrogen treatment can be carried out to the grid layer 18, to consume the part grid
Layer 18 simultaneously forms dielectric layer 17 between the grid between the grid layer 18.For example, when the grid layer 18 is polysilicon gate
When layer, silicon oxide layer can be formed as the first electric leakage inhibition layer 171, to institute by carrying out oxidation processes to the grid layer 18
Silicon oxynitride layer can be formed as the second electric leakage inhibition layer 172 by stating the progress oxidation processes of grid layer 18 and nitrogen treatment.
18 quilt of grid layer can be made by adjusting technological parameter (for example, reaction gas, reaction pressure and reaction temperature etc.)
Part consumes and forms the first electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172 that are alternately superimposed on.Certainly, exist
It, can also be using physical gas-phase deposition, chemical vapor deposition process or atom layer deposition process in adjacent in other examples
Deposition forms dielectric layer 17 between the grid between the grid layer 18 and between the grid layer 18 and the semiconductor substrate 10.
In one example, as shown in FIG. 13 and 14, dielectric layer 17 and the unfilled adjacent grid layer 18 between the grid
Between gap and the grid layer 18 and the semiconductor substrate 10 between gap, at this point, between the grid dielectric layer 17 also
Including the air gap 173, the air gap 173 is located at the first electric leakage inhibition layer 171 and the second electric leakage inhibition layer
In 172 structures being alternately superimposed on；I.e. at this point, between the adjacent grid layer 18 and the grid layer 18 and the semiconductor substrate
It include the first electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172 being alternately superimposed on there are two being respectively formed between 10
The electric leakage inhibit lamination 17 ', the air gap 173 positioned at the adjacent grid layer 18 between and the grid layer 18 and
Between the semiconductor substrate 10, and it is located at the electric leakage and inhibits between lamination 17 '.
In another example, dielectric layer 17 can fill up the gap between the adjacent grid layer 18 and described between the grid
Gap between grid layer 18 and the semiconductor substrate 10, as shown in Figure 15 and Figure 16.
It should be noted that no matter form dielectric layer 17 between the grid using the part grid layer 18 is carried out processing,
Or dielectric layer 17 between the grid is formed using depositing operation, the side wall of the gate pitch 15 can be formed simultaneously along the grid
The first electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172 that the width direction in gap 15 is alternately superimposed on, such as Figure 13
And shown in Figure 15.
As an example, forming alternating in the upper surface of the semiconductor substrate 10 while forming dielectric layer 17 between the grid
The stacked first electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172.
As an example, please refer to Figure 17 to Figure 25, between the adjacent grid layer 18 and the grid layer 18 with it is described
Dielectric layer 17 further includes later following steps between forming grid between semiconductor substrate 10:
7) source region 20 is formed in the semiconductor substrate 10 of 15 bottom of Yu Suoshu gate pitch, such as Figure 17 and Figure 18
It is shown；Wherein, cross section structure of the Figure 17 between the grid in dielectric layer 17 including 173 counter structure of the air gap is illustrated,
Figure 18 dielectric layer 17 between the grid can fill up the gap between the adjacent grid layer 18 and the grid layer 18 with it is described
The cross section structure schematic diagram of counter structure between semiconductor substrate 10；And
8) common source line 21 is formed in Yu Suoshu gate pitch 15, the common source line 21 is in contact with the source region 20,
As shown in Figure 23 and Figure 24；Wherein, section of the Figure 23 between the grid in dielectric layer 17 including 173 counter structure of the air gap
Face structural representation, Figure 24 dielectric layer 17 between the grid can fill up gap and the grid between the adjacent grid layer 18
The cross section structure schematic diagram of counter structure between layer 18 and the semiconductor substrate 10.
As an example, can partly be led using ion implantation technology to the described of 15 bottom of gate pitch in step 7)
Body substrate 10 carries out ion implanting, to form the source region 20.
It should be noted that when the semiconductor substrate 10 to 15 bottom of gate pitch carries out ion implanting, position
In the first electric leakage inhibition layer 171 of 15 bottom of gate pitch being alternately superimposed on and the second electric leakage inhibition layer 172
It is not removed, the first electric leakage inhibition layer 171 and described second being alternately superimposed on positioned at 15 bottom of gate pitch
The presence of electric leakage inhibition layer 172 can protect the semiconductor substrate 10 in ion implantation process, to avoid ion
Injection causes lattice damage to the semiconductor substrate 10.
As an example, Figure 19 and Figure 20 is please referred to, shape in the semiconductor substrate 10 of 15 bottom of Yu Suoshu gate pitch
It later further include first electric leakage being alternately superimposed on that removal is located at 15 bottom of gate pitch at the source region 20
The step of inhibition layer 171 and the second electric leakage inhibition layer 172.Specifically, dry etch process or wet etching can be used
Technique removal is located at the first electric leakage inhibition layer 171 being alternately superimposed on and second electric leakage of 15 bottom of gate pitch
Inhibition layer 172；Wherein, Figure 19 includes the cross section structure of 173 counter structure of the air gap in dielectric layer 17 between the grid
Signal, Figure 20 dielectric layer 17 for the grid between can fill up the gap between the adjacent grid layer 18 and the grid layer 18 and
The cross section structure schematic diagram of counter structure between the semiconductor substrate 10.
It should be noted that inhibiting in first electric leakage being alternately superimposed on that removal is located at 15 bottom of gate pitch
While layer 171 and the second electric leakage inhibition layer 172, positioned at described first be alternately superimposed on of 15 side wall of gate pitch
Electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172 are removed together, as shown in FIG. 19 and 20；Specifically, in described
The source region 20 is formed in the semiconductor substrate 10 of 15 bottom of gate pitch later can be upper prior to resulting structures
Surface forms the mask layer (not shown) with opening figure, can be removed using etching technics positioned at institute according to the mask layer
State the first electric leakage inhibition layer 171 being alternately superimposed on and the second electric leakage inhibition layer 172 of 15 side wall of gate pitch.When
So, in other examples, positioned at the first electric leakage inhibition layer 171 and described of 15 side wall of gate pitch being alternately superimposed on
Second electric leakage inhibition layer 172 can not also be removed and retain.
As an example, please referring to Figure 21 and Figure 22, is formed before the common source line 21 in Yu Suoshu gate pitch 15, also wrapped
Include in the gate pitch 15 side wall formed dielectric isolation layer 22 the step of.Specifically, physical vapour deposition (PVD) work can be used
Skill, chemical vapor deposition process or atom layer deposition process form the dielectric isolation layer in the side wall of the gate pitch 15
22.The dielectric isolation layer 22 is used to for the common source line 21 and the grid layer 18 being electrically isolated, the dielectric isolation layer 22
Material may include but be not limited only to silica, silicon nitride, silicon oxynitride or hafnium oxide etc.；Wherein, Figure 21 is between the grid
Cross section structure in dielectric layer 17 including 173 counter structure of the air gap is illustrated, and dielectric layer 17 can between the grid by Figure 22
With counter structure between the gap filled up between the adjacent grid layer 18 and the grid layer 18 and the semiconductor substrate 10
Cross section structure schematic diagram.
It should be noted that when forming dielectric isolation layer 22, the dielectric isolation layer 22 can shape simultaneously
The bottom of the side wall of gate pitch 15 and the gate pitch 15 described in Cheng Yu, at this point, in order to ensure in the gate pitch 15
The common source line 21 formed and the source region 20 are in electrical contact, and further include by position after the dielectric isolation layer 22 is formed
The step of dielectric isolation layer 22 in 15 bottom of gate pitch removes.
As an example, physical gas-phase deposition, chemical vapor deposition process or atomic layer deposition can be used in step 8)
Product technique is in forming the common source line 21 in the gate pitch 15, it is preferable that in the present embodiment, using atom layer deposition process
In forming the common source line 21 in the gate pitch 15.
As an example, the material of the common source line 21 may include metal (for example, copper, aluminium, gold, silver, nickel or cobalt etc.)
Or DOPOS doped polycrystalline silicon etc..The common source line 21 fills up the gate pitch 15, i.e., the upper surface of the described common source line 21 can be with
The upper surface of the gate pitch 15 is parallel.
In the 3D nand flash memory that the present embodiment obtains, it is formed in the semiconductor substrate 10 including being alternately superimposed on
The grid layer 18 and the grid between dielectric layer 17 laminated construction 31.
Dielectric layer 17 is including at least being alternately superimposed between the grid in the 3D nand flash memory manufactured in the present embodiment
The first electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172, can effectively reduce between the adjacent grid layer 18
Electric leakage, improve the breakdown characteristics of dielectric layer 17 between the grid between the adjacent grid layer 18, reduce the adjacent grid
Coupling effect between pole layer 18.
In the present embodiment, by being etched to the sacrificial layer 111 between the grid layer 18 is additional, so that the channel
Through-hole 12 is greater than the width corresponding to 18 part of grid layer in the width for corresponding to 111 part of sacrificial layer, described
After sacrificial layer 111 is removed, can make the channel through-hole 12 side wall formed the function side wall 13 in described in
Accumulation layer 132 is between the adjacent grid layer 18 and the portion between the grid layer 18 and the semiconductor substrate 10
It point is filled in the recess region 122, i.e., so that the accumulation layer 132 along the thickness direction of the laminated construction 31 includes more
A protrusion part protruded between the adjacent grid layer 13 and between the grid layer 13 and the semiconductor substrate 10.Institute
Stating protrusion part can mitigate or even prevent charge in the region of grid layer 18 described in 132 face of accumulation layer to both sides
132 regional diffusion of accumulation layer, i.e., the described protrusion part can mitigate or even prevent grid described in 132 face of accumulation layer
Charge in the region of layer 18 corresponds to the region between the grid layer 18 and the grid layer 18 to the accumulation layer 132 and expands
It dissipates, that is, protrusion part can mitigate or even prevent the charge in the accumulation layer 132 along 31 thickness of laminated construction
The lateral of direction is lost, to mitigate the threshold voltage shift for even avoiding the grid layer 18, it is ensured that the 3D nand flash memory
The stability of performance；Meanwhile when being programmed a certain layer grid layer 18, due to the presence of the lobe portion, no
A small amount of charge can be programed out between the adjacent grid layer 18, reduce the interlayer interference coupling between the adjacent grid layer 18
It closes, to avoid the threshold voltage of the grid layer 18 caused by coupling between the adjacent grid layer 18 there are interlayer interference
Drift, it is ensured that the stability of the 3D nand flash memory performance.
Embodiment two
A kind of 3D nand flash memory, the 3D nand flash memory are also provided please continue to refer to Figure 23 and Figure 25, in the present embodiment
It include: semiconductor substrate 10；Laminated construction 31, the laminated construction 31 are located in the semiconductor substrate 10, the lamination knot
Structure 31 includes dielectric layer 17 and grid layer 18 between the grid being alternately superimposed on；Dielectric layer 17 includes the air gap 173 and hands between the grid
For the first stacked electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172, the air gap 173 is located at first electric leakage
In the structure that inhibition layer 171 and the second electric leakage inhibition layer 172 are alternately superimposed on；Channel through-hole 12, the channel through-hole 12
In in the laminated construction 31；The channel through-hole 12 includes several recess regions 122, and the recess region 122 is located at phase
Between the adjacent grid layer 18 and between the grid layer 18 and the semiconductor substrate 10；Function side wall 13, the functioning side
Wall 13 is located at the sidewall surfaces of the channel through-hole 12, and the function side wall 13 is between the adjacent grid layer 18 and is located at
Being partially filled in the recess region 122 between the grid layer 18 and the semiconductor substrate 10；And channel layer 14, institute
It states channel layer 14 to be located in the channel through-hole 12, and is located at the surface of the function side wall 13 and the bottom of the channel through-hole 12
Portion.
As an example, the semiconductor substrate 10 can be selected according to the actual demand of device, the semiconductor lining
Bottom 10 may include silicon substrate, germanium (Ge) substrate, SiGe (SiGe) substrate, SOI (Silicon-on-insulator, insulation
Silicon on body) substrate or GOI (Germanium-on-Insulator, germanium on insulator) substrate etc.；Preferably, the present embodiment
In, the semiconductor substrate 10 includes monocrystalline silicon wafer crystal.
It should be noted that the semiconductor substrate 10 is the substrate carried out after ion doping, specifically, the semiconductor
Substrate 10 can be p-type doped substrate, or n-type doping substrate.
As an example, the laminated construction 31 may include dielectric layer 17 between the grid being successively alternately superimposed on from the bottom to top
And the grid layer 18, i.e., the bottom and top layer of the described laminated construction 31 are dielectric layer 17 between the grid, positioned at the institute of top layer
The upper surface for stating dielectric layer 17 between grid is the upper surface of the laminated construction 31.
As an example, the first electric leakage inhibition layer 171 may include oxide skin(coating), the second electric leakage inhibition layer 172
It may include oxynitride layer.Specifically, the first electric leakage inhibition layer 171 may include silicon oxide layer or hafnium oxide layer, institute
Stating the second electric leakage inhibition layer 172 may include silicon oxynitride layer or nitrogen oxidation hafnium layer.
As an example, can be carried out at oxidation using wet-oxygen oxidation technique or dry-oxygen oxidation technique to nitrogenous insulating medium layer
Reason obtains dielectric layer 17 between the grid.
As an example, the material of the grid layer 18 may include metal (for example, tungsten or cobalt etc.) or silicon, it is preferable that
In the present embodiment, the material of the grid layer 18 may include DOPOS doped polycrystalline silicon.
As an example, the channel through-hole 12 runs through the laminated construction 31 along the thickness direction of the laminated construction 31.
As an example, the quantity and distribution situation of the channel through-hole 12 can according to device architecture to be formed reality
Border is set, herein without limitation.
As an example, the function side wall 13 may include: barrier layer 131, it is logical that the barrier layer 131 is located at the channel
The sidewall surfaces in hole 12；Accumulation layer 132, the accumulation layer 132 are located at the surface on the barrier layer 131, at least described accumulation layer
132 between the adjacent grid layer 18 and being partially filled between the grid layer 18 and the semiconductor substrate 10
In in the recess region 122；And tunnel layer 133, the tunnel layer 133 are located at the surface of the accumulation layer 132.Preferably,
In the present embodiment, the barrier layer 131, the accumulation layer 132 and the tunnel layer 133 are between the adjacent grid layer 18
And being partially filled in the recess region 122 between the grid layer 18 and the semiconductor substrate 10, i.e., it is described
Barrier layer 131, the accumulation layer 132 and the tunnel layer 133 include multiple protrusions along the thickness direction of the laminated construction 31
Protrusion part between the adjacent grid layer 18 and between the grid layer 18 and the semiconductor substrate 10, such as Figure 23 institute
Show.
As an example, please referring to Figure 26, the barrier layer 131 may include high-k dielectric layer 131a and barrier laminate structure
131b；The high-k dielectric layer 131a is located at the surface of the channel through-hole 12, and the barrier laminate structure 131b is located at the height
The surface of k dielectric layer 131a；The barrier laminate structure 131b includes replacing along the barrier laminate structure 131b thickness direction
Stacked oxide skin(coating) 131c and oxynitride layer 131d.In the barrier laminate structure 131b, the oxide skin(coating) 131c and
The periodicity that the oxynitride layer 131d is alternately superimposed on can be set according to actual needs, herein without limitation；It is described
The sequence that oxide skin(coating) 131c and the oxynitride layer 131d are alternately superimposed on can be set according to actual needs, Tu26Zhong
Only with the barrier layer 131 from the high-k dielectric layer 131a include outward the oxide skin(coating) 131c being successively alternately superimposed on and
The oxynitride layer 131d is as an example, only illustrate two layers of oxide skin(coating) 131c and one layer of nitrogen oxidation in Figure 26
Nitride layer 131d, is not limited thereto in actual example.
As an example, the material of the high-k dielectric layer 131a may include aluminium oxide or hafnium oxide etc., the oxide layer
The material of 131c may include silica or hafnium oxide etc., and the material of the oxynitride layer 131d may include silicon oxynitride
Or nitrogen oxidation hafnium etc..
As an example, please referring to Figure 27, the accumulation layer 132 includes the nitride layer 132a that through-thickness is alternately superimposed on
And oxynitride layer 132b；The sequence that the nitride layer 132a and the oxynitride layer 132b are alternately superimposed on can be according to reality
Border is set, and the periodicity that the nitride layer 132a and the oxynitride layer 132b are alternately superimposed on can be according to reality
Border is set, only outside including the successively alternate nitrogen from the barrier layer 131 with the accumulation layer 132 in Figure 27
The compound layer 132a and oxynitride layer 132b as an example, and only illustrated in Figure 27 three layers of nitride layer 132a and
Two layers of oxynitride layer 132b, is not limited thereto in actual example.
As an example, the material of the nitride layer 132a may include silicon nitride or hafnium nitride etc., the nitrogen oxidation
The material of nitride layer 132b may include silicon oxynitride or nitrogen oxidation hafnium etc..
As an example, please referring to Figure 28, the tunnel layer 133 may include the oxide skin(coating) that through-thickness is intervally arranged
133a and nitrogen oxides laminated construction 133b, the nitrogen oxides laminated construction 133b between the oxide skin(coating) 133a
The oxynitride layer 133c being stacked including multilayer along 133 thickness direction of tunnel layer.
As an example, the material of the nitride layer 133a may include silicon nitride or hafnium nitride etc., the nitrogen oxidation
The material of nitride layer 133c may include silicon oxynitride or nitrogen oxidation hafnium etc..
It should be noted that the number of plies of oxynitride layer 133c described in the nitrogen oxides laminated construction 133b can root
It is set according to actual needs, herein without limitation.
It should be further noted that each layer oxynitride layer 133c be not in the nitrogen oxides laminated construction 133b
Identical to the greatest extent, the atomic ratio of each element in each layer oxynitride layer 133c is not quite similar, for example, with the oxynitride layer
The material of 133c be silicon oxynitride as an example, nitrogen, oxygen and the atomic ratio of silicon three in each oxynitride layer 133c not
It is identical to the greatest extent.
As an example, the material of the channel layer 14 may include polysilicon.Certainly, in other examples, the channel
The material of layer 14 can also be other semiconductor materials.
As an example, the sum of the thickness of the function side wall 13 and the channel layer 14 can be less than the channel through-hole 12
Width half, as shown in figure 23, at this point, being formed after the channel layer 14, that filling is also remained in the channel through-hole 12 is exhausted
The reserved space of edge layer；In other examples, the channel layer 14 can also fill up the channel through-hole 12.
As an example, the 3D nand flash memory can also include: gate pitch 15, the gate pitch 15 is located at described
In laminated construction 31, the gate pitch 15 is through the laminated construction 31 and extends in the semiconductor substrate 10；Source electrode
Region 20, the source region 20 are located in the semiconductor substrate 10, and are located at the bottom of the gate pitch 15；Common source line
21, the common source line 21 is located in the gate pitch 15, and is connected with 20 domain of source area；Dielectric isolation layer 22, institute
It states dielectric isolation layer 22 to be located in the gate pitch 15, and between the common source line 21 and the laminated construction 31；It fills out
Insulating layer 19 is filled, the filling insulating layer 19 is filled in the channel through-hole 12, and is located at the surface of the channel layer 14.
As an example, the position of the gate pitch 15 and quantity can be set according to actual needs, do not do herein
It limits.
As an example, the gate pitch 15 can through the laminated construction 11 until the semiconductor substrate 10 it is upper
Surface；Certainly, the gate pitch 15 may also extend through the laminated construction 11 and extend in the semiconductor substrate 10.
As an example, can using ion implantation technology to the semiconductor substrate 10 of 15 bottom of gate pitch into
Row ion implanting, to form the source region 20.
As an example, the material of the common source line 21 may include metal (for example, copper, aluminium, gold, silver, nickel or cobalt etc.)
Or DOPOS doped polycrystalline silicon etc..The common source line 21 fills up the gate pitch 15, i.e., the upper surface of the described common source line 21 can be with
The upper surface of the gate pitch 15 is parallel.
As an example, the dielectric isolation layer 22 is for the common source line 21 and the grid layer 18 to be electrically isolated, it is described
The material of dielectric isolation layer 22 may include but be not limited only to silica, silicon nitride or hafnium oxide etc..
As an example, the material of the filling insulating layer 19 may include oxide isolation layer, for example silica etc..It is described
Filling insulating layer 19 can fill up the channel through-hole 12.
Dielectric layer 17 is including at least described in being alternately superimposed between the grid in the embodiment of the present invention 3D nand flash memory
First electric leakage inhibition layer 171 and the second electric leakage inhibition layer 172, can effectively reduce the leakage between the adjacent grid layer 18
Electricity improves the breakdown characteristics of dielectric layer 17 between the grid between the adjacent grid layer 18, reduces the adjacent grid layer
Coupling effect between 18.
In 3D nand flash memory described in the present embodiment, as shown in figure 23, the channel through-hole 12 corresponds to adjacent described
Part between grid layer 18 and between the grid layer 18 and the semiconductor substrate 10 is formed with recess region 122, described
The width of 17 part of dielectric layer between corresponding to the grid of channel through-hole 12 is greater than the width corresponding to 18 part of grid layer,
The accumulation layer 132 in the function side wall 13 that the side wall of the channel through-hole 12 is formed is located at the adjacent grid layer
Being partially filled in the recess region 122 between 18 and between the grid layer 18 and the semiconductor substrate 10,
I.e. so that the accumulation layer 132 along the thickness direction of the laminated construction 31 include it is multiple protrude from the adjacent grid layer 13 it
Between and the protrusion part between the grid layer 13 and the semiconductor substrate 10, as shown in figure 23.Protrusion part can be with
Mitigate the accumulation layer 132 of the charge in the region for even preventing grid layer 18 described in 132 face of accumulation layer to both sides
Regional diffusion, i.e., the described protrusion part can mitigate or even prevent in the region of grid layer 18 described in 132 faces of the storage
Charge corresponds to the regional diffusion between the grid layer 18 and the grid layer 18 to the accumulation layer 132, that is, described convex
Part can mitigate or even prevent the charge in the accumulation layer 132 along the transverse flow of 31 thickness direction of laminated construction out
It loses, to mitigate the threshold voltage shift for even avoiding the grid layer 18, it is ensured that the stabilization of the 3D nand flash memory performance
Property；It, will not be in adjacent institute due to the presence of the lobe portion meanwhile when being programmed a certain layer grid layer 18
It states and programs out a small amount of charge between grid layer 18, the interlayer interference coupling between the adjacent grid layer 18 is reduced, to keep away
Exempt from the threshold voltage shift of the grid layer 18 caused by coupling between the adjacent grid layer 18 there are interlayer interference, it is ensured that
The stability of the 3D nand flash memory performance.
As described above, 3D nand flash memory of the invention and preparation method, the preparation method of the 3D nand flash memory include
Following steps: providing semiconductor substrate, and laminated construction is formed in the semiconductor substrate, and the laminated construction includes alternately folded
The sacrificial layer and grid layer set；In formation channel through-hole in the laminated construction；Include the following steps: in the laminated construction
Form vertical through-hole；Remove the part sacrificial layer based on the vertical through-hole lateral etching, in the adjacent grid layer it
Between and the grid layer and the semiconductor substrate between form recess region；Function is formed in the sidewall surfaces of the channel through-hole
Energy side wall, and channel layer is formed in the surface of the function side wall and the bottom of the channel through-hole；The function side wall is located at
The groove area is partially filled between the adjacent grid layer and between the grid layer and the semiconductor substrate
In domain；In forming gate pitch in the laminated construction；The sacrificial layer is removed based on the gate pitch；And in adjacent described
Dielectric layer between grid is formed between grid layer and between the grid layer and the semiconductor substrate, dielectric layer includes handing between the grid
For the first stacked electric leakage inhibition layer and the second electric leakage inhibition layer.Dielectric layer is at least between grid in 3D nand flash memory of the present invention
Including the first electric leakage inhibition layer and the second electric leakage inhibition layer being alternately superimposed on, the leakage between neighboring gates layer can be effectively reduced
Electricity improves the breakdown characteristics of dielectric layer between the grid between neighboring gates layer, reduces the coupling effect between neighboring gates layer；This
Accumulation layer includes multiple protrude between neighboring gates layer and grid along the thickness direction of laminated construction in the 3D nand flash memory of invention
Protrusion part between pole layer and semiconductor substrate, protrusion part can mitigate the region for even preventing accumulation layer face grid layer
For interior charge to the accumulation layer regional diffusion on both sides, i.e., protrusion part, which can mitigate, even prevents the charge in institute's accumulation layer along folded
The lateral of layer structural thickness direction is lost, to mitigate the threshold voltage shift for even avoiding grid layer, it is ensured that 3D nand flash memory
The stability of performance；It, will not be in adjacent gate due to the presence of lobe portion meanwhile when being programmed to a certain layer grid layer
A small amount of charge is programed out between the layer of pole, to reduce the interlayer interference coupling between neighboring gates layer, and then reduces grid layer
Threshold voltage shift, it is ensured that the stability of the 3D nand flash memory performance.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (18)
1. a kind of preparation method of 3D nand flash memory, which comprises the steps of:
Semiconductor substrate is provided, is formed with laminated construction in the semiconductor substrate, the laminated construction includes being alternately superimposed on
Sacrificial layer and grid layer；
In formation channel through-hole in the laminated construction；Include the following steps: in forming vertical through-hole in the laminated construction；Base
Remove the part sacrificial layer in the vertical through-hole lateral etching, between the adjacent grid layer and the grid layer with
Recess region is formed between the semiconductor substrate；
Function side wall is formed in the sidewall surfaces of the channel through-hole, and in the surface of the function side wall and the channel through-hole
Bottom formed channel layer；The function side wall is partly led between the adjacent grid layer and positioned at the grid layer with described
Being partially filled in the recess region between body substrate；
In forming gate pitch in the laminated construction；
The sacrificial layer is removed based on the gate pitch；And
Between the adjacent grid layer and between the grid layer and the semiconductor substrate formed grid between dielectric layer, the grid
Between dielectric layer include be alternately superimposed on first electric leakage inhibition layer and second electric leakage inhibition layer.
2. the preparation method of 3D nand flash memory according to claim 1, which is characterized in that the side of Yu Suoshu channel through-hole
Wall surface forms the function side wall and includes the following steps:
Barrier layer is formed in the sidewall surfaces of the channel through-hole；
Accumulation layer is formed in the surface on the barrier layer, the accumulation layer is between the adjacent grid layer and positioned at the grid
Being partially filled in the recess region between pole layer and the semiconductor substrate；And
Tunnel layer is formed in the surface of the accumulation layer.
3. the preparation method of 3D nand flash memory according to claim 2, which is characterized in that the barrier layer includes that high k is situated between
Matter layer and barrier laminate structure, the high-k dielectric layer are located at the surface of the channel through-hole, and the barrier laminate structure is located at institute
The surface of high-k dielectric layer is stated, the barrier laminate structure includes the oxygen being alternately superimposed on along barrier laminate structural thickness direction
Compound layer and oxynitride layer；The accumulation layer includes the nitride layer and oxynitride layer that through-thickness is alternately superimposed on；Institute
Stating tunnel layer includes the oxide skin(coating) that through-thickness is intervally arranged and the nitrogen oxides lamination between the oxide skin(coating)
Structure.
4. the preparation method of 3D nand flash memory according to claim 1, it is characterised in that: the channel through-hole runs through institute
Laminated construction is stated, the gate pitch runs through the laminated construction.
5. the preparation method of 3D nand flash memory according to claim 1, it is characterised in that: the table of Yu Suoshu function side wall
Face further includes the steps that after forming the channel layer in formation filling insulating layer in the channel through-hole.
6. the preparation method of 3D nand flash memory according to claim 1, it is characterised in that: in the adjacent grid layer it
Between and the grid layer and the semiconductor substrate between form the grid between dielectric layer further include following steps:
In forming source region in the semiconductor substrate of the gate pitch bottom；And
In forming common source line in the gate pitch, the common source line is in contact with the source region.
7. the preparation method of 3D nand flash memory according to claim 6, it is characterised in that: form dielectric layer between the grid
While in the semiconductor substrate upper surface formed be alternately superimposed on it is described first electric leakage inhibition layer and it is described second electric leakage
Inhibition layer, the semiconductor substrate of Yu Suoshu gate pitch bottom is interior to be formed after the source region and between the grid
It is formed before the common source line in gap, further includes the first electric leakage inhibition layer and the institute that removal is located at the gate pitch bottom
The step of stating the second electric leakage inhibition layer.
8. the preparation method of 3D nand flash memory according to claim 6, it is characterised in that: shape in Yu Suoshu gate pitch
Before the common source line, further include the steps that forming dielectric isolation layer in the gate pitch side wall.
9. the preparation method of 3D nand flash memory according to claim 1, it is characterised in that: the first electric leakage inhibition layer
Including oxide skin(coating), the second electric leakage inhibition layer includes oxynitride layer.
10. the preparation method of 3D nand flash memory according to claim 9, it is characterised in that: the first electric leakage inhibition layer
Including silicon oxide layer and the second electric leakage inhibition layer includes silicon oxynitride layer or the first electric leakage inhibition layer includes hafnium oxide
Layer and it is described second electric leakage inhibition layer include nitrogen oxidation hafnium layer.
11. the preparation method of 3D nand flash memory according to any one of claim 1 to 10, it is characterised in that: Yu Xianglin
Dielectric layer includes the following steps: between forming the grid between the grid layer and between the grid layer and the semiconductor substrate
The grid layer is carried out to the grid layer and carries out oxidation processes and nitrogen treatment, to form institute between the grid layer
State dielectric layer between grid.
12. the preparation method of 3D nand flash memory according to claim 11, it is characterised in that: dielectric layer is also between the grid
Including the air gap, the air gap is alternately superimposed on positioned at the first electric leakage inhibition layer and the second electric leakage inhibition layer
In structure.
13. a kind of 3D nand flash memory characterized by comprising
Semiconductor substrate；
Laminated construction is located in the semiconductor substrate, and the laminated construction includes dielectric layer and grid between the grid being alternately superimposed on
Layer；Between the grid dielectric layer include the air gap and be alternately superimposed on first electric leakage inhibition layer and second electric leakage inhibition layer, it is described
The air gap is located in the structure that the first electric leakage inhibition layer and the second electric leakage inhibition layer are alternately superimposed on；
Channel through-hole is located in the laminated construction；The channel through-hole includes several recess regions, the recess region position
Between the adjacent grid layer and between the grid layer and the semiconductor substrate；
Function side wall, positioned at the sidewall surfaces of the channel through-hole, the function side wall between the adjacent grid layer and
Being partially filled in the recess region between the grid layer and the semiconductor substrate；And
Channel layer is located in the channel through-hole, and is located at the surface of the function side wall and the bottom of the channel through-hole.
14. 3D nand flash memory according to claim 13, it is characterised in that: the function side wall includes:
Barrier layer, positioned at the sidewall surfaces of the channel through-hole；
Accumulation layer, positioned at the surface on the barrier layer, the accumulation layer is between the adjacent grid layer and positioned at the grid
Being partially filled in the recess region between pole layer and the semiconductor substrate；And
Tunnel layer, positioned at the surface of the accumulation layer.
15. 3D nand flash memory according to claim 14, which is characterized in that the barrier layer includes high-k dielectric layer and resistance
Laminated construction is kept off, the high-k dielectric layer is located at the surface of the channel through-hole, and the barrier laminate structure is located at the high k and is situated between
The surface of matter layer, the barrier laminate structure include the oxide skin(coating) being alternately superimposed on along barrier laminate structural thickness direction and
Oxynitride layer；The accumulation layer includes the nitride layer and oxynitride layer that through-thickness is alternately superimposed on；The tunnel layer
The oxide skin(coating) being intervally arranged including through-thickness and the nitrogen oxides laminated construction between the oxide skin(coating).
16. 3D nand flash memory according to claim 13, it is characterised in that: the 3DNAND flash memory further include:
Gate pitch is located in the laminated construction, and the gate pitch described is partly led through the laminated construction and extending to
In body substrate；
Source region is located in the semiconductor substrate, and is located at the bottom of the gate pitch；
Common source line is located in the gate pitch, and is connected with the source region；
Dielectric isolation layer is located in the gate pitch, and between the common source line and the laminated construction；
Insulating layer is filled, is filled in the channel through-hole, and is located at the surface of the channel layer.
17. 3D nand flash memory according to claim 13, it is characterised in that: the first electric leakage inhibition layer includes oxidation
Nitride layer, the second electric leakage inhibition layer includes oxynitride layer.
18. 3D nand flash memory according to claim 17, it is characterised in that: the first electric leakage inhibition layer includes oxidation
Silicon layer and the second electric leakage inhibition layer include silicon oxynitride layer or the first electric leakage inhibition layer includes hafnium oxide layer and described
Second electric leakage inhibition layer includes nitrogen oxidation hafnium layer.
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| CN201910248966.XA CN110047840B (en) | 2019-03-29 | 2019-03-29 | 3D NAND flash memory and preparation method |
| JP2021546395A JP7523453B2 (en) | 2019-03-29 | 2019-06-28 | 3D Memory Device |
| PCT/CN2019/093455 WO2020199390A1 (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory devices and fabrication methods thereof |
| PCT/CN2019/093442 WO2020199387A1 (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory devices and fabrication methods thereof |
| PCT/CN2019/093447 WO2020199388A1 (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory devices and fabrication methods thereof |
| PCT/CN2019/093454 WO2020199389A1 (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory devices and fabrication methods thereof |
| EP19922600.2A EP3878013B1 (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory devices and fabrication methods thereof |
| PCT/CN2019/093419 WO2020199386A1 (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory devices and fabrication methods thereof |
| CN201980001310.6A CN110914986B (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory device and method of fabricating the same |
| CN201980001305.5A CN110896671B (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory device and method of fabricating the same |
| CN201980001292.1A CN110896672B (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory device and method of fabricating the same |
| KR1020217024007A KR102652212B1 (en) | 2019-03-29 | 2019-06-28 | 3D memory device and manufacturing method thereof |
| CN201980001308.9A CN110914985B (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory device and method of fabricating the same |
| CN201980001304.0A CN110896670B (en) | 2019-03-29 | 2019-06-28 | Three-dimensional memory device and method of fabricating the same |
| US16/541,144 US11004861B2 (en) | 2019-03-29 | 2019-08-14 | Three-dimensional memory devices and fabrication methods thereof |
| US16/541,137 US11943923B2 (en) | 2019-03-29 | 2019-08-14 | Three-dimensional memory devices and fabrication methods thereof |
| US16/541,141 US11081496B2 (en) | 2019-03-29 | 2019-08-14 | Three-dimensional memory devices and fabrication methods thereof |
| US16/541,142 US11011540B2 (en) | 2019-03-29 | 2019-08-14 | Three-dimensional memory devices and fabrication methods thereof |
| US16/541,145 US10964718B2 (en) | 2019-03-29 | 2019-08-14 | Three-dimensional memory devices and fabrication methods thereof |
| TW108130482A TWI749360B (en) | 2019-03-29 | 2019-08-26 | Three-dimensional memory devices and fabrication methods thereof |
| US17/100,869 US11462565B2 (en) | 2019-03-29 | 2020-11-21 | Three-dimensional memory devices and fabrication methods thereof |
| US17/100,868 US11665903B2 (en) | 2019-03-29 | 2020-11-21 | Three-dimensional memory devices and fabrication methods thereof |
| US17/100,871 US11502102B2 (en) | 2019-03-29 | 2020-11-21 | Three-dimensional memory devices and fabrication methods thereof |
| US17/226,056 US11581332B2 (en) | 2019-03-29 | 2021-04-08 | Three-dimensional memory devices and fabrication methods thereof |
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