CN111508841A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN111508841A
CN111508841A CN201910093348.2A CN201910093348A CN111508841A CN 111508841 A CN111508841 A CN 111508841A CN 201910093348 A CN201910093348 A CN 201910093348A CN 111508841 A CN111508841 A CN 111508841A
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gate
layer
drain
source
trench
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不公告发明人
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate with an active region formed on the surface; forming a groove on a semiconductor substrate, and forming a source/drain connected with the groove on the opposite side edges of the groove respectively; forming a grid electrode in the groove, and forming a grid dielectric layer between the grid electrode and the groove; partially removing the gate dielectric layer between the gate and the source/drain overlapping region; an isolation layer is deposited over the gate to form a closed gap layer between the gate and the source/drain overlap region. According to the invention, the gate-drain voltage is reduced and the gate-induced drain leakage current is effectively inhibited by introducing the void layer to replace the gate dielectric layer in the gate-drain overlapping region of the transistor, so that the reliability of the device is improved, the power consumption of the device is reduced, and the data storage and read-write performance of the DRAM device are improved.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
Dram (dynamic Random Access memory), which is a dynamic Random Access memory, is a widely used memory device. As the demand for DRAM storage capacity continues to increase, the device density per unit area of the wafer increases, and the design feature size decreases. In order to ensure that the data storage time and the refresh characteristics of the storage unit can still meet the design requirements when the DRAM device is continuously made small, the development and optimization of the word line structure are important links in the design of the DRAM device.
At present, in the existing DRAM word line structure, a gate oxide layer is arranged between a gate (gate) metal layer and a drain (drain) doped region of a gate-drain overlapping region for isolation, when the gate-drain voltage of the gate-drain overlapping region is higher, band-to-band tunneling (band-to-band tunneling) occurs between a valence band and a conduction band for electrons in a silicon substrate near an interface of the overlapping region, and further leakage current, namely gate-induced drain leakage current (GID L) is formed.
Therefore, it is desirable to provide a new semiconductor structure and a method for fabricating the same to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which are used to solve the problem in the prior art that the reliability and power consumption of a semiconductor device are affected due to too large gate-induced drain leakage current.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the steps of:
providing a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate;
arranging a groove on the active region, and respectively forming an active/drain on opposite side edges of the groove, wherein the active/drain is connected to the groove;
forming a grid electrode in the groove, and forming a grid dielectric layer between the grid electrode and the groove;
partially removing the gate dielectric layer between the gate and the source/drain overlapping region;
and depositing an isolation layer above the grid electrode so as to form a closed gap layer between the grid electrode and the source/drain overlapping region.
As an alternative of the invention, the bottom of the void layer is at least not lower than the bottom of the source/drain.
As an alternative of the invention, the top of the gate is higher than the bottom of the source/drain and lower than the top of the trench.
As an alternative of the invention, the top of the spacer layer is at least not higher than the top of the gate.
As an alternative of the invention, the top of the isolation layer is flush with the top of the trench; the bottom of the isolation layer is flush with the top of the gate.
As an alternative of the present invention, the semiconductor substrate comprises a P-type semiconductor substrate, and the source/drain comprises an N-type doped source/drain.
The present invention also provides a semiconductor structure comprising:
the semiconductor device comprises a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate;
a trench on the active region, opposite sides of the trench having a source/drain formed thereon, respectively, the source/drain being connected to the trench;
a gate located in the trench;
the gate dielectric layer is positioned between the gate and the groove, and the top of the gate dielectric layer is lower than that of the gate;
the isolation layer is positioned above the grid;
and the gap layer is formed between the grid electrode and the source/drain overlapping region and is positioned above the grid dielectric layer.
As an alternative of the invention, the bottom of the void layer is at least not lower than the source/drain bottom.
As an alternative of the invention, the top of the gate is higher than the bottom of the source/drain and lower than the top of the trench.
As an alternative of the invention, the top of the spacer layer is at least not higher than the top of the gate.
As described above, the present invention provides a semiconductor structure and a method for manufacturing the same, which reduces the gate-drain voltage and effectively suppresses the gate-induced drain leakage current by introducing a void layer instead of a gate dielectric layer in the gate-drain overlap region of a transistor, thereby improving the reliability of the device and reducing the power consumption of the device, and improving the data storage and read-write performance of a DRAM device.
Drawings
Fig. 1 is a top view of a semiconductor structure obtained by the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.
Fig. 2 to 10 are cross-sectional views of steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention at aa' of fig. 1.
Fig. 11 to 12 are cross-sectional views of a semiconductor structure provided in a second embodiment of the invention at aa' of fig. 1.
Description of the element reference numerals
100 semiconductor substrate
100a active region
100b shallow trench isolation structure
101 source/drain
102 trench
103 gate dielectric layer
104 grid
104a layer of gate material
105 isolating layer
105a layer of isolating material
106 void layer
106a void trench
107 hard mask layer
107a hard mask material layer
108 gate-drain overlap region
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 10, the present embodiment provides a method for manufacturing a semiconductor structure, including the following steps:
providing a semiconductor substrate 100, wherein an active region is formed on the surface of the semiconductor substrate 100;
providing a trench 102 on the active region, forming a source/drain 101 on opposite sides of the trench 102, respectively, the source/drain 101 being connected to the trench 102;
forming a gate 104 in the trench 102, and forming a gate dielectric layer 103 between the gate and the trench;
partially removing the gate dielectric layer 103 between the overlapping region of the gate 104 and the source/drain 101;
an isolation layer 105 is deposited over the gate 104 to form a hermetically sealed gap layer 106 between the gate 104 and the source/drain 101 overlap region.
Fig. 1 is a top view of a semiconductor structure obtained by the method for manufacturing a semiconductor structure provided in this embodiment. Fig. 2 to 11 are sectional views of steps in the method of manufacturing the semiconductor structure provided in the present embodiment at aa' of fig. 1.
As an example, as shown in fig. 1 to 4, the semiconductor structure in the present embodiment includes a buried word line structure applied to a DRAM device. Forming a plurality of active regions 100a and shallow trench isolation structures 100b separating the active regions on a semiconductor substrate 100; the source/drain 101 is formed on the active region 100 a; the trenches 102 are formed on the active regions 100a and the shallow trench isolation structures 100b and communicate with the active regions 100 a. It is noted that the semiconductor substrate 100 covered by the active region 100a and the shallow trench isolation structure 100b is not shown in fig. 1, and the shallow trench isolation structure 100b is not shown in fig. 2 to 4. In this embodiment, a plurality of active regions 100a and shallow trench isolation structures 100b separating the active regions 100a are formed on the semiconductor substrate 100, and source/drain 101 is formed by performing an ion implantation process on the active regions 100 a. Optionally, the semiconductor substrate 100 includes a P-type silicon substrate, the source/drain 101 includes an N-type doped source/drain, and the shallow trench isolation structure 100b includes a silicon dioxide layer. In this embodiment, the source/drain 101 is formed simultaneously after doping on the active region 100a, and can be further divided into a source or a drain according to the connection relationship in the transistor structure, as shown in fig. 11, in which the source/drain 101 connected to the bit line on the left side of the trench is the source, and the source/drain 101 connected to the capacitor on the right side of the trench is the drain. As shown in fig. 1, the active regions 100a are periodically arranged on the semiconductor substrate 100 at certain intervals, and the trenches 102 are formed to laterally penetrate through a plurality of the active regions 100a and the shallow trench isolation structures 100b between the active regions 100 a. The word line structure is connected to a number of the active regions 100a by forming the word line structure in the trench 102.
As an example, as shown in fig. 2 to 4, a process of forming a trench 102 on the semiconductor substrate 100 includes the steps of:
forming a hard mask material layer 107a on the semiconductor substrate 100, as shown in fig. 2;
forming a patterned hard mask layer 107 by photolithography and etching, as shown in fig. 3;
the trench 102 is formed by dry etching with the hard mask layer 107 as an etching mask, as shown in fig. 4.
In this embodiment, before the trench 102 is formed, a source/drain 101 and a shallow trench isolation structure 100b are formed on the semiconductor substrate 100, and therefore, the hard mask material layer 107a is deposited on the upper surfaces of the source/drain 101 and the shallow trench isolation structure 100b, as shown in fig. 2. Optionally, the hard mask material layer 107a comprises a silicon dioxide layer. The hard mask material layer 107a is subjected to photolithography and etching to obtain a patterned hard mask layer 107, as shown in fig. 3. A trench 102 formed by dry etching penetrates the source/drain 101 and contacts the semiconductor substrate 100, i.e., the bottom of the trench 102 is at least lower than the bottom of the source/drain 101, as shown in fig. 4. In fig. 4, the trench 102 separates the source/drain 101 into a source on the left and a drain on the right. It is to be noted that the order of forming the trench 102, the source/drain 101 and the shallow trench isolation structure 100b is not limited in the present invention. For example, in other embodiments, the trench 102 may be formed on the semiconductor substrate 100, a sacrificial layer is introduced to cover the trench 102, and then the source/drain 101 is formed on the semiconductor substrate 100 by ion implantation. In addition, the hard mask material layer 107a may further include an amorphous carbon layer formed on an upper layer in addition to the silicon dioxide layer, so as to improve an etching selectivity in the dry etching and remove the remaining amorphous carbon layer after the dry etching.
As an example, as shown in fig. 5, a gate dielectric layer 103 is formed on the surface of the trench 102. Optionally, the gate dielectric layer 103 includes a silicon dioxide layer, and the method for forming the silicon dioxide layer includes growing the silicon dioxide layer on the silicon material on the sidewall and the bottom of the trench 102 by using a furnace thermal oxidation process. In the present embodiment, since other positions except the surface of the trench 102 are covered by the silicon dioxide layer, the furnace thermal oxidation process only generates the silicon dioxide layer on the silicon material at the surface position of the trench 102.
As an example, as shown in fig. 6 to 7, the process of forming the gate 104 in the trench 102 includes the following steps:
depositing a gate material layer 104a in the trench 102, the gate material layer 104a at least filling the trench 102;
a portion of the gate material layer 104a in the trench 102 is removed by etching back, and the remaining portion of the gate material layer 104a forms the gate 104, wherein the top of the gate 104 is higher than the bottom of the source/drain 101 and lower than the top of the trench 102.
Optionally, as shown in fig. 6, a gate material layer 104a is deposited on the hard mask layer 107 and in the trench 102 by a chemical vapor deposition or atomic layer deposition process. The gate material layer 104a comprises a tungsten metal layer. In fig. 6, a portion of the gate material layer 104a on the hard mask layer 107 and in the trench 102 is removed by an etch-back process, and the gate 104 is formed in the remaining portion of the bottom of the trench 102, as shown in fig. 7. The etch-back process can be dry etching or wet etching.
In addition, as an alternative of this embodiment, before depositing the gate material layer 104a, an adhesion layer, such as a titanium nitride layer, may be deposited first, so as to improve the bonding performance of the gate material layer 104a and the gate oxide layer on the surface of the trench 102, and prevent the occurrence of delamination cracking. In fig. 7, when a portion of the gate material layer 104a is etched back, the adhesion layer underlying the portion of the gate material layer 104a is also removed at the same time.
As an example, as shown in fig. 8, a method for removing a portion of the gate dielectric layer 103 on the sidewall of the trench 102 includes dry etching or wet etching, and the top of the gate dielectric layer 103 is lower than the top of the gate 104 by etching. Optionally, the gate dielectric layer 103 includes a silicon dioxide layer, and the dry etching may select CF4、CHF3The CF-based gas may be used as an etching gas to perform isotropic etching, or a chemical solution such as DHF may be used to perform wet etching on the silicon dioxide layer. In the etching process, the gate dielectric layer 103 exposed at the upper portion of the sidewall of the trench 102 is etched and removed, and as the etching proceeds, the gate dielectric layer 103 between the gate material layer 104a and the sidewall of the trench 102 is also etchedEtching is performed, and a trench structure, which is defined as a void trench 106a in the present invention, is formed between the source/drain 101, the gate 104 and the gate dielectric layer 103. In fig. 8, one of the void trenches 106a is formed on each of the left and right sides of the gate 104.
Note that, in the present embodiment, the bottom of the void trench 106a is higher than the top of the source/drain 101. That is, the interstitial trenches 106a do not extend into the semiconductor substrate 100 underlying the source/drain 101. The semiconductor substrate 100 and the gate 104 are also isolated by the gate dielectric layer 103, i.e., a silicon dioxide layer. In other embodiments of the present invention, the void trench 106a may also extend further into the semiconductor substrate 100 under the source/drain 101, i.e., a part of the region between the semiconductor substrate 100 and the gate 104 is isolated by the void trench 106 a. The above differences determine the composition of the isolation medium in the gate-drain overlap region and a part of the channel region of the transistor structure obtained in the present invention, and the selection of the isolation medium has an important influence on the performance of the transistor, such as the gate-to-drain leakage current and the switching characteristics. In this embodiment, the isolation dielectric in the channel region is completely formed by the silicon dioxide gate dielectric layer, which ensures that the resulting device has good switching characteristics.
As an example, as shown in fig. 9 to 10, the process of forming the isolation layer 105 over the gate electrode 104 includes the steps of:
depositing a layer of isolation material 105a on the surface of the hard mask layer 107 and over the gate 104 in the trench 102;
removing the isolation material layer 105a on the surface of the hard mask layer 107, forming the isolation layer 105 on the part of the isolation material layer 105a remaining in the trench 102, and forming a gap layer 106 between the source/drain 101, the gate 104 and the gate dielectric layer 103.
Optionally, the top of the void layer 106 is at least no higher than the top of the gate 104. This ensures that the void layer 106 is only present between the gate 104 and the source/drain 101, and does not intrude upward into the isolation layer 105, thereby affecting the isolation effect of the isolation layer 105.
Optionally, an isolation material layer 105a is deposited on the surface of the hard mask layer 107 and above the gate 104 in the trench 102 by chemical vapor deposition or atomic layer deposition, and the isolation material layer 105a includes a silicon nitride layer, as shown in fig. 9. And removing the isolation material layer 105a on the surface of the hard mask layer 107 by an etching back process or chemical mechanical polishing, and forming the isolation layer 105 in the isolation material layer 105a remaining in the trench 102. Optionally, the etch-back process or the chemical mechanical polishing further removes the hard mask layer 107, and finally makes the top of the isolation layer 105 flush with the surface of the source/drain 101, as shown in fig. 10.
Specifically, when the isolation material layer 105a is deposited in the trench 102 above the gate 104, it is necessary to ensure that the void trench 106a is not filled by the deposition of the isolation material layer 105a, so as to form a void layer 106 between the source/drain 101, the gate 104 and the gate dielectric layer 103. Therefore, when the isolation material layer 105a is deposited by using chemical vapor deposition, Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atmospheric Pressure Chemical Vapor Deposition (APCVD) with a high deposition rate and a relatively weak step coverage capability may be used, so that when the isolation material layer 105a is not deposited in the void trench 106a or the isolation material layer 105a is deposited less, the top of the void trench 106a is already sealed and closed by deposition, and the void layer 106 is formed in the void trench 106 a. Since the gate dielectric layer 103 is relatively thin in the transistor structure, and the opening of the void trench 106a formed by the gate dielectric layer 103 is also small, it is fully practical to deposit no or little isolation material layer 105a in the void trench 106a by using the existing deposition process. Optionally, when the isolation material layer 105a is a silicon nitride layer, the silicon nitride layer and the silicon substrate on the sidewall of the trench 102 may have a stress problem, a pad oxygen layer may be deposited on the sidewall of the trench 102 to improve the stress problem, and the thickness of the pad oxygen layer is much smaller than that of the gate dielectric layer 103, so that the formation of the void layer 106 is not affected.
It is noted that fig. 10 shows a case where the isolation material layer 105a is not deposited at all in the void trench 106a in the present embodiment. In other embodiments of the present invention, the void trench 106a may also be formed by depositing a thin layer of the isolation material layer 105a on the sidewalls and bottom thereof, and forming the void layer 106 in the middle of the void trench 106a, based on a deposition process, which does not affect the technical effect achieved by the present invention. In addition, in other embodiments of the present invention, a sacrificial material layer may be filled in the void trench 106a, and then the isolation material layer 105a may be deposited. After the deposition of the isolation material layer 105a is completed, the sacrificial material layer is removed by a dry or wet etching process. This solution also makes it possible to completely avoid the deposition of the layer of isolating material 105a in the interstitial trenches 106 a.
The void layer 106 introduced in the present invention may be a vacuum layer, an air layer, or other low dielectric constant gas filling layer. The vacuum layer is an ideal low dielectric constant (low-k) dielectric layer, the relative dielectric constant of vacuum is 1.0, and the relative dielectric constant of air (-1.0006) is very close to that of vacuum. When used as a low-k medium, the two media have similar performances. Therefore, in the present invention, the void layer 106 is not particularly limited to a vacuum layer or an air layer. If the influence of the vacuum layer or the air layer on the reliability of the device structure is also considered, when the void layer 106 is the air layer, there may be a risk that the device performance is affected due to the expansion of air by heat or moisture contained in the air. Therefore, as an alternative, when the isolation material layer 105a is deposited, a deposition process such as PECVD performed under a vacuum condition may be selected to maintain a vacuum in the void layer, so as to further improve the stability of the obtained device, and the specifically adopted deposition process and process parameters need to be optimized and selected according to the actual requirements of the device design, so as to ensure that the performance and reliability of the obtained semiconductor device are not affected while the relative dielectric constant of the isolation medium in the gate-drain overlapping region is reduced.
Example two
The present embodiment provides a semiconductor structure, as shown in fig. 1 and 10, the semiconductor structure includes:
the semiconductor device comprises a semiconductor substrate 100, wherein an active region is formed on the surface of the semiconductor substrate 100;
a trench 102 on the active region, wherein source/drain regions 101 are respectively formed on opposite sides of the trench 102, and the source/drain regions 101 are connected to the trench 102;
a gate 104 in the trench 102;
a gate dielectric layer 103 located between the gate 104 and the trench 102, wherein the top of the gate dielectric layer 103 is lower than the top of the gate 104;
an isolation layer 105 located above the gate 104;
a void layer 106 formed between the gate 104 and the source/drain 101 overlapping region and located above the gate dielectric layer 103;
as shown in fig. 1, is a top view of the semiconductor structure provided in this embodiment. Fig. 10 is a cross-sectional view of the semiconductor structure provided in the present embodiment at aa' of fig. 1. Alternatively, the semiconductor structure in this embodiment can be obtained according to the method for manufacturing a semiconductor structure in the first embodiment.
As an example, as shown in fig. 1 and 10, the semiconductor structure includes a buried word line structure applied to a DRAM device. The semiconductor substrate 100 further comprises a plurality of active regions 100a and shallow trench isolation structures 100b separating the active regions 100 a; the source/drain 101 is located on the upper surface of the active region 100 a; the trench 102 is located on the active region 100a and the shallow trench isolation structure 100b and connects a plurality of the active regions 100 a. It is noted that the semiconductor substrate 100 covered by the active region 100a and the shallow trench isolation structure 100b is not shown in fig. 1, and the shallow trench isolation structure 100b is not shown in fig. 10. Optionally, the semiconductor substrate 100 comprises a P-type semiconductor substrate, such as a P-type silicon substrate, and the source/drain 101 comprises an N-type doped source/drain. As shown in fig. 1, the active regions 100a are periodically arranged on the semiconductor substrate 100 at certain intervals, and the trenches 102 are formed to laterally penetrate through a plurality of the active regions 100a and the shallow trench isolation structures 100b between the active regions 100 a. The word line structure is connected to a number of the active regions 100a by forming the word line structure in the trench 102.
As an example, as shown in fig. 10, the gate electrode 104 includes a tungsten layer, the gate dielectric layer 103 includes a silicon dioxide layer, the spacer layer 105 includes a silicon nitride layer, and the void layer 106 includes a vacuum layer or an air layer.
As an example, as shown in fig. 10, the top of the gate 104 is higher than the bottom of the source/drain 101 and lower than the top of the trench 102.
As an example, as shown in fig. 10, the top of the void layer 106 is at least not higher than the top of the gate 104.
As an example, as shown in fig. 10, the bottom of the void layer 106 is not lower than at least the bottom of the source/drain 101. In the present embodiment, as shown in fig. 10, most of the space above the gate-drain overlap region 108 is formed by the void layer 106, and a section of the gate dielectric layer 103 is still remained near the bottom of the source/drain 101. This ensures that the gate-to-drain leakage current of the gate-to-drain overlap region 108 is improved by introducing the void layer 106, and also ensures that the gate dielectric layer 103 is still used for isolation in the channel region, thereby having good switching characteristics. Optionally, the bottom of the void layer 106 is flush with the bottom of the source/drain 101, and the isolation medium of the gate-drain overlap region 108 is completely composed of the void layer 106. In this case, the gate-drain overlap region 108 will have better resistance to gate-induced drain leakage current.
In the present embodiment, the top of the gate 104 is not higher than at least the bottom of the source/drain 101, and the top of the second gate 105 is higher than the bottom of the source/drain 101, so that the gate material at the gate-drain overlap region 108 is completely composed of the second gate 105, i.e. composed of a polysilicon layer, rather than a tungsten metal layer. This will significantly reduce the gate-to-drain leakage current generated at the gate-to-drain overlap region 108.
As shown in fig. 11, the buried word line structure provided in the present invention is shown, wherein most of the isolation medium at the gate-drain overlap region 108 is formed by the void layer 106, the source/drain 101 is doped N-type, and the semiconductor substrate 100 is a P-type silicon substrate. When the transistor is turned off and the DRAM stores data, the word line gate is kept biased negatively and the drain of the right-hand connection capacitor is biased positively, so that the gate-drain voltage at this time is the maximum value that the device can reach. As shown in fig. 12, when the isolation dielectric at the gate-drain overlap region 108 is completely formed by the gate dielectric layer 103, i.e., the silicon dioxide layer, a large amount of gate-induced drain leakage current is generated in the direction of the arrow in fig. 12 at a high gate leakage voltage. In the embedded word line structure provided in the invention in fig. 11, since the void layer 106 is used to partially replace the silicon dioxide layer, when the transistor is turned off, the gate-drain voltage at the gate-drain overlapping region 108 is greatly reduced, which greatly reduces the gate-induced drain leakage current at the gate-drain overlapping region 108, even avoids generating the gate-induced drain leakage current. By improving the characteristics of the gate-to-drain leakage current at the gate-drain overlap region 108 of the DRAM memory cell, the reliability and read/write performance of the DRAM device can be significantly improved and the power consumption of the device when turned off can be reduced. It should be noted that, although the present embodiment illustrates the superiority of the semiconductor structure provided by the present invention in improving the gate-induced drain leakage current when applied to the DRAM embedded word line structure, this does not limit the application scope of the semiconductor structure provided by the present invention. The invention has obvious improvement effect on the grid-induced drain leakage current generated by the grid leakage voltage in other transistor structures.
In summary, the present invention provides a semiconductor structure and a method for fabricating the same, the method for fabricating the semiconductor structure includes the following steps: providing a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate; forming a groove on the semiconductor substrate, wherein the groove penetrates through the active region and the bottom of the groove is lower than that of the active region; forming a gate dielectric layer on the surface of the groove; forming a gate in the trench, a top of the gate being higher than a bottom of the active region and lower than a top of the trench; removing part of the gate dielectric layer on the side wall of the groove to enable the top of the gate dielectric layer to be lower than the top of the grid electrode; and forming an isolation layer above the grid, wherein the isolation layer fills the space above the grid in the groove, and a gap layer is formed among the active region, the grid and the grid dielectric layer. The semiconductor structure includes: the semiconductor device comprises a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate; the groove is positioned on the semiconductor substrate, penetrates through the active region and is lower than the bottom of the active region; the grid electrode is positioned in the groove, and the top of the grid electrode is higher than the bottom of the active region and lower than the top of the groove; the gate dielectric layer is positioned between the gate and the semiconductor substrate, and the top of the gate dielectric layer is lower than that of the gate; the gap layer is positioned among the active region, the grid electrode and the grid dielectric layer; and the isolation layer is positioned above the grid electrode and fills the space above the grid electrode in the groove. According to the invention, the gate-drain voltage is reduced and the gate-induced drain leakage current is effectively inhibited by introducing the void layer to replace the gate dielectric layer in the gate-drain overlapping region of the transistor, so that the reliability of the device is improved, the power consumption of the device is reduced, and the data storage and read-write performance of the DRAM device are improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising the steps of:
providing a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate;
arranging a groove on the active region, and respectively forming an active/drain on opposite side edges of the groove, wherein the active/drain is connected to the groove;
forming a grid electrode in the groove, and forming a grid dielectric layer between the grid electrode and the groove;
partially removing the gate dielectric layer between the gate and the source/drain overlapping region;
and depositing an isolation layer above the grid electrode so as to form a closed gap layer between the grid electrode and the source/drain overlapping region.
2. The method of claim 1, wherein a bottom of said void layer is at least not lower than said source/drain bottom.
3. The method as claimed in claim 1, wherein the top of the gate is higher than the bottom of the source/drain and lower than the top of the trench.
4. The method of claim 1, wherein a top of said spacer layer is at least no higher than a top of said gate.
5. The method of claim 1, wherein a top of said isolation layer is flush with a top of said trench; the bottom of the isolation layer is flush with the top of the gate.
6. The method of claim 1, wherein said semiconductor substrate comprises a P-type semiconductor substrate and said source/drain comprises an N-type doped source/drain.
7. A semiconductor structure, comprising:
the semiconductor device comprises a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate;
a trench on the active region, opposite sides of the trench having a source/drain formed thereon, respectively, the source/drain being connected to the trench;
a gate located in the trench;
the gate dielectric layer is positioned between the gate and the groove, and the top of the gate dielectric layer is lower than that of the gate;
the isolation layer is positioned above the grid;
and the gap layer is formed between the grid electrode and the source/drain overlapping region and is positioned above the grid dielectric layer.
8. The semiconductor structure of claim 7, wherein said voided layer has a bottom that is at least not lower than said source/drain bottom.
9. The semiconductor structure of claim 7, wherein the top of said gate is higher than the bottom of said source/drain and lower than the top of said trench.
10. The semiconductor structure of claim 7, wherein the top of said spacer layer is at least no higher than the top of said gate.
CN201910093348.2A 2019-01-30 2019-01-30 Semiconductor structure and manufacturing method thereof Pending CN111508841A (en)

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