WO2014161471A1 - Semiconductor device having u-shaped channel - Google Patents

Semiconductor device having u-shaped channel Download PDF

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Publication number
WO2014161471A1
WO2014161471A1 PCT/CN2014/074529 CN2014074529W WO2014161471A1 WO 2014161471 A1 WO2014161471 A1 WO 2014161471A1 CN 2014074529 W CN2014074529 W CN 2014074529W WO 2014161471 A1 WO2014161471 A1 WO 2014161471A1
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WIPO (PCT)
Prior art keywords
region
floating gate
gate
shaped channel
insulating film
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PCT/CN2014/074529
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French (fr)
Chinese (zh)
Inventor
刘伟
刘磊
王鹏飞
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苏州东微半导体有限公司
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Publication of WO2014161471A1 publication Critical patent/WO2014161471A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

Definitions

  • the present invention relates to the field of semiconductor memory technologies, and relates to a dynamic random access memory, and more particularly to a U Shaped channel semiconductor device.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • Chinese Patent Application No. 200810043070.X discloses a "semiconductor memory device, semiconductor memory array And a writing method", the semiconductor memory device includes a source, a drain, a floating gate region, and a control a gate, a recessed channel region (also known as a U-shaped channel region), and a gated p-n for connecting the floating gate region and the drain a junction diode; the floating gate of the semiconductor memory device is used to store charge, which can be charged by a gate-controlled p-n junction diode Electricity or discharge.
  • the semiconductor memory adopts a recessed channel structure, the current between the source and drain regions is increased.
  • the drain contact body is used as a control gate of the gate-controlled p-n junction diode, so that the semiconductor memory and the logic
  • the compatibility of the circuit is poor; the second is because the floating gate is only located in the U-shaped groove, so that the control gate is capacitively coupled.
  • the area used for the floating gate is only the open area of the U-shaped groove, and the area is small, which reduces the capacitance of the control gate to the floating gate.
  • the coupling ratio which increases the operating voltage of the control gate, reduces the reliability of semiconductor memory operation.
  • Cisokawa patent Application 201310006320.3 discloses "a half of a planar channel"
  • a conductor memory includes: a source region 501, a drain region 502, and a semiconductor substrate 500 formed therein a planar channel region 601; a first insulating film 503 formed over the source region 501, the channel region 601, and the drain region 502, and
  • the floating gate 505 is formed with a p-n junction diode between the floating gate 505 and the drain region 502 through the floating gate opening region 504;
  • the cover floating gate 505 and the p-n junction diode are formed with a second insulating film 506 and a control gate 507.
  • the semiconductor memory The advantage of the memory is that the floating gate is used to store information, and the gate-controlled gate-controlled p-n junction diode is used to control the floating gate. Charging or discharging, can be compatible with the manufacture of logic circuits, and the control gate covers the floating gate on the upper surface and both sides of the floating gate. In order to effectively increase the contact area between the control gate and the floating gate, thereby increasing the capacitive coupling ratio of the control gate to the floating gate, the data Reading and writing only requires a lower operating voltage.
  • the semiconductor memory also has the following disadvantages: to ensure half of the planar channel
  • the performance of the conductor memory not only needs to extend the length of the current channel region between the source and drain regions, but also needs to be extended.
  • the length of the current channel region of the parasitic MOS transistor between the floating gate and the current channel region so that the unit surface of the semiconductor memory
  • the expansion of the product reduces the density of the chip, which is not conducive to the development of the chip toward miniaturization.
  • the object of the present invention is to provide a U-shaped channel semiconductor device for overcoming the deficiencies of the prior art, the present invention
  • the parasitic region between the floating gate and the current channel region is increased by increasing the depth of the drain region.
  • the length of the current channel region of the MOS transistor, etc., thereby obtaining a reduction in cell area and improvement of the semiconductor memory device The chip density can improve the compatibility and operational reliability of the semiconductor memory device and the logic circuit.
  • the present invention provides a U-shaped channel semiconductor device comprising:
  • a first doping type semiconductor substrate provided with a U-shaped channel region
  • a source region and a drain region of a second doping type are disposed in the semiconductor substrate, and the U-shaped channel region is disposed in the source region and the drain region Between districts;
  • the method further includes: a first insulating film disposed on the U-shaped channel region, the first insulating layer is thin The film extends on both sides of the U-shaped channel region to the horizontal surfaces of the source and drain regions, respectively;
  • the floating gate opening region being located on a horizontal surface or a side of the drain region On the wall
  • a gate-controlled diode having a control gate as a gate is composed of a control gate, a second insulating film, and a p-n junction diode.
  • a further optimization of the invention lies in:
  • the first doping type of the invention is n-type, and the second doping type is p-type, then the gate-controlled diode A cathode is connected to the floating gate, and an anode of the gated diode is connected to the drain region.
  • the first doping type of the present invention is p-type, and the second doping type is n-type, and the gate-controlled diode An anode is connected to the floating gate, and a cathode of the gated diode is connected to the drain region.
  • the first insulating film of the present invention is made of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric.
  • An electrically constant insulating material having a physical thickness of 1 to 20 nm.
  • the second insulating film of the present invention is made of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric.
  • An electrically constant insulating material having a physical thickness of 1 to 20 nm.
  • the floating gate of the present invention is made of polysilicon.
  • the control gate of the present invention is made of metal, alloy or doped polysilicon.
  • a doping region is respectively disposed in the source region and the drain region, and the doping region is the same as the doping type of the region, and is doped
  • the impurity concentration is higher than the doping concentration of the region.
  • the present invention forms a floating gate in a U-shaped groove and extends to both sides of the U-shaped groove to the level of the source and drain regions.
  • the floating gate opening region can be formed on the sidewall of the drain region or on the horizontal surface of the drain region.
  • U-shaped channel semiconductor memory and logic can be improved on the basis of extending the current channel region between the source region and the drain region. Circuit compatibility.
  • the present invention extends the length of the floating gate along the length of the current channel region on the basis of the U-shaped channel region. It can increase the area of the control gate acting on the floating gate through capacitive coupling, thereby improving the capacitive coupling of the control gate to the floating gate.
  • the combination rate reduces the operating voltage of the control gate, improves the reliability of the operation of the semiconductor memory, and reduces the peripheral control circuit. The complexity of the design.
  • the present invention increases the drain region depth to increase the current channel of the parasitic MOS transistor between the floating gate and the current channel region.
  • the leakage current of the tube further extends the time for the floating gate to store charge and improves the reliability of operation of the semiconductor memory device.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor memory of a planar channel described in Chinese Patent Application No. 201310006320.3.
  • FIG. 2 is a cross-sectional view showing a first embodiment of a U-shaped channel semiconductor device according to the present invention.
  • FIG 3 is a cross-sectional view showing a second embodiment of a U-shaped channel semiconductor device according to the present invention.
  • FIG. 4 is a cross-sectional view showing a third embodiment of a U-shaped channel semiconductor device according to the present invention.
  • FIG. 5 is an equivalent circuit diagram of a U-shaped channel semiconductor device according to the present invention.
  • FIG. 6 to FIG. 13 are schematic diagrams showing the process flow of an embodiment of a U-shaped channel semiconductor device according to the present invention. Figure.
  • a U proposed by the present invention a channel shaped semiconductor device comprising a semiconductor substrate 200 having a first doping type and a semiconductor a source region 201 and a drain region 202 having a second doping type formed in the substrate 200; a material of the semiconductor substrate 200
  • the quality is monocrystalline silicon, polycrystalline silicon or silicon on insulator; the first doping type is n type, and the second doping type is p Type, or the first doping type is p-type and the second doping type is n-type.
  • the U-shaped channel region 401 of the device is formed in the surface of the U-shaped groove in the bulk substrate, and the U-shaped channel region 401 is the U-shaped groove.
  • the inverting layer formed in the semiconductor substrate 200 during operation of the semiconductor device.
  • a first layer is formed on a horizontal surface covering the entire U-shaped channel region 401 and extending to the source region 201 and the drain region 202
  • the insulating film 203 is formed with a floating gate opening region 204 in the first insulating film 203, and the floating gate opening region 204 It may be formed on the horizontal surface of the drain region 202, as shown in FIGS. 2 and 3, or may be formed in the drain region 202.
  • the first insulating film 203 is made of a dioxygen Silicon, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric constant insulating material having a physical thickness of 1-20 nm.
  • the floating gate 205 has a doping type opposite to the drain region 202, and the doping impurities in the floating gate 205 pass through the floating gate opening region.
  • 204 diffuses into the drain region 202 to form a diffusion region 402 having a first doping type, thereby passing through the floating gate opening region 204
  • a p-n junction diode is formed between the floating gate 205 and the drain region 202.
  • the floating gate 205 and the p-n junction diode are formed with a second insulating film 206, the second insulating film
  • the material of 206 is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric constant insulating material, and its physical thickness is a degree of 1-20 nm;
  • a control gate 207 formed on the second insulating film 206 and covering the floating gate 205 is formed with a device,
  • the control gate 207 is made of metal, alloy or doped polysilicon; the control gate 207, the second insulating film 206,
  • the p-n junction diode constitutes a gated diode with the control gate 207 as the gate.
  • Control gate 207 can be in floating gate 205 The top and sides of the same cover the floating gate to improve the control gate coupling ratio, as shown in Figure 2 and Figure 4; 207 may also cover floating gate 205 at the top of floating gate 205 and on the side near the drain region, as shown in FIG.
  • a gate spacer 208 of the device is formed on both sides of the control gate 207, and the gate spacer 208 is made of dioxane. Silicon or silicon nitride, gate spacers are well known in the art for use in controlling gate 207 and other conductive devices in the device. Layer isolation.
  • Also formed in the source region 201 and the drain region 202 are the same doping type as the source region 201 and the drain region 202, respectively.
  • the doping region 209 and the doping region 210, the doping concentration of the doping region 209 and the doping region 210 are significantly higher than that of the source region 201 and the drain region
  • the doping concentration of region 202 is used to reduce the ohmic contact of the device.
  • the U-shaped channel semiconductor device of the present invention may further include a conductive material formed for the source region, and the control a gate body, a drain region, a contact region 211 of the source region where the semiconductor substrate is connected to the external electrode, a contact body 212 of the control gate, The contact body 213 of the drain region and the contact body 214 of the semiconductor substrate.
  • FIG. 5 An equivalent circuit diagram of a semiconductor device of a U-shaped channel of the present invention is shown.
  • the U-shaped channel of the present invention The semiconductor device includes a MOSFET 336 having a source 332, a drain 330, a floating gate 333, and a control gate 331 And a gated diode 335 having a gate MOSFET 336 as its gate.
  • Floating gate of MOSFET336 333 may be connected to the anode of the gated diode 335 or may be connected to the cathode of the gated diode 335.
  • FIG. 5 An equivalent circuit diagram of a semiconductor device of a U-shaped channel of the present invention is shown.
  • the semiconductor device includes a MOSFET 336 having a source 332, a drain 330, a floating gate 333, and a control gate 331 And a gated diode 335 having a gate MOSFET 336 as its gate.
  • Floating gate of MOSFET336 333 may be
  • the floating gate 333 is connected to the anode of the gated diode 335; 331.
  • the drain 330 and the source 331 apply an appropriate voltage, and the gate diode 335 can charge the floating gate 333 or The discharge thereby changes the amount of charge stored in the floating gate 333, the amount of which determines the semiconductor of the U-shaped channel The logic state of the device.
  • U-shaped channel semiconductor device disclosed in the present invention can be fabricated by various methods. The following is shown in Figure 3. U-shaped channel semiconductor device structure, further illustrating the process flow of one embodiment of the present invention with reference to FIGS. 6 to 13 The specific steps of the process:
  • Step one passes through the shallow trench in the provided semiconductor substrate 200 having the first doping type.
  • the trench isolation (STI) process forms an active region (not shown in Figure 6) which is well known in the art.
  • a lightly doped region 300 having a second doping type is formed in the semiconductor substrate 200 by an ion implantation process; wherein: The material of the semiconductor substrate 200 is monocrystalline silicon, polycrystalline silicon or silicon on insulator.
  • the first type of doping For the p-type, the second doping type is n-type.
  • Step 2 depositing a hard mask layer 301 on the surface of the semiconductor substrate 200.
  • the material of the hard mask layer 301 is Silicon nitride.
  • a layer of photoresist 302 is then deposited over the hard mask layer 301 and masked, exposed, and developed to define the device.
  • Step three stripping the photoresist 303 and continuing to etch away the remaining hard mask layer 301, followed by the semiconductor substrate 200.
  • a first insulating film 203 is grown on the exposed surface, and the first insulating film 203 is made of silicon oxide or silicon nitride. Silicon oxynitride or a high dielectric constant insulating material such as yttria, having a physical thickness of 1-20 nm; Depositing a layer of photoresist on the layer of insulating film 203 and determining the position of the floating gate opening region by photolithography, and then using light The first layer of the insulating film 203 is etched away as a mask, so as to be first on the horizontal surface of the drain region 202.
  • a floating gate opening region 204 is formed in the layer insulating film 203, and then the photoresist is stripped to form a structure as shown in Fig. 8a.
  • the floating gate opening region 204 may also be formed on the side of the drain region 202, that is, on the sidewall of the U-shaped groove.
  • the first insulating film 203 as shown in Fig. 8b.
  • Forming a floating gate opening region 204 as shown in FIG. 8b Thereafter, a U-channel semiconductor device as shown in FIG. 4 can be formed by the same process steps as described below. The structure of each process in the preparation of the structure will not be described in detail in this embodiment.
  • Step 4 depositing a first layer of conductive thin film having a first doping type on the exposed surface of the formed structure a film, the conductive film being polycrystalline silicon having a p-type doping type; and then depositing over the formed first layer of conductive film
  • a layer of photoresist is deposited and the position of the floating gate is determined by a photolithography process, and then exposed by photoresist as a mask a conductive film, the first conductive film remaining after etching forms the floating gate 205 of the device; the floating gate 205 covers at least the entire U-shaped recesses and floating gate opening regions 204, the doping impurities in the floating gate 205 will pass through the floating gate below the floating gate 205
  • the port region 204 diffuses into the drain region 202 to form a p-type diffusion region 402, and passes through the floating gate opening region 204 at the floating gate 205.
  • a p-n junction diode formed between the drain region 202; and then continuing to etch away the exposed first
  • Step 5 depositing a second insulating film 206 on the exposed surface of the formed structure, the second layer is thin
  • the material of the film 206 is a high dielectric constant insulating material such as silicon oxide, silicon nitride, silicon oxynitride or hafnium oxide, and its physics a thickness of 1-20 nm; then depositing a second conductive film 207 over the second insulating film 206, the second The layer conductive film 207 is made of metal, alloy or doped polysilicon; then on the second conductive film 207 Depositing a layer of photoresist and determining the position of the control gate of the device by photolithography, and then etching away with photoresist as a mask The exposed second conductive film, the second conductive film remaining after etching forms the control gate 207 of the device, and the control gate The length of 207 in the direction along the channel should exceed the floating gate 205, and the floating gate 205 is covered on the top and both sides of the floating gate 205, and stripped
  • the second insulating film 206 is etched by controlling the pattern on the lithography mask, Etching off the second conductive film 206 on the side of the floating gate 205 near the source region 201, leaving only the floating gate 205 near the drain region.
  • the second conductive film 206 on one side of the 202 is formed to cover the floating gate 205 only on the top of the floating gate 205 and on the side close to the drain region.
  • the control gate 207 as shown in Figure 10b, is then formed by the same process steps as described below.
  • the structure of the U-channel semiconductor device shown, the structure in each process when the structure is prepared is in this embodiment No longer described in detail.
  • Step six depositing a third insulating film on the exposed surface of the formed structure, and then forming the first
  • the three layers of insulating film are etched back to form gate spacers 208 on both sides of the control gate 207, which is well known in the art. After stripping the photoresist, it is shown in FIG.
  • the gate spacer 208 can be silicon oxide or silicon nitride.
  • Step 7 performing impurity ion implantation of a second doping type (n-type), for the control gate 207 and the uncontrolled gate
  • the semiconductor substrate 200 covered by 207 is doped to form a doping structure of the control gate 207, and is in the source region 201 and the drain region.
  • a high concentration doped region 209 and doped region 210 are formed in 202, respectively, as shown in FIG.
  • Step eight forming a conductive material for using the source region 201, the control gate 207, the drain region 202, and the semiconductor substrate 200
  • the contact body 214 of the conductor substrate is as shown in FIG.

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Abstract

A semiconductor device having U-shaped channel, comprising: a U-shaped channel region (401), a source region (201), and a drain region (202) formed in a semi-conductor substrate, a first insulating thin film layer (203), a floating gate (205), a second insulating thin film layer (206), and a control gate (207) being arranged on the U-shaped channel region (401), a p-n junction diode being arranged between the floating gate (205) and the drain region (202), and a gated diode consisting of the control gate (207), the second insulating thin film layer (206), and the p-n junction diode, the control gate (207) acting as the gate electrode. The semi-conductor device employs a U-shaped channel structure to extend the length of the current channel region, and increases the depth of the drain region to reduce the parasitic drain current of an MOS transistor between the floating gate and the current channel region, thereby allowing the unit surface area of a semiconductor memory device to be reduced and chip density to be increased, whilst also having the effect of increasing the compatibility and operating reliability of a semiconductor memory device and logical circuit.

Description

一种U形沟道的半导体器件 U-shaped channel semiconductor device                  技术领域 Technical field                 
本发明属于半导体存储器技术领域，涉及一种动态随机存储器，特别是涉及一种U 形沟道的半导体器件。 The present invention relates to the field of semiconductor memory technologies, and relates to a dynamic random access memory, and more particularly to a U           Shaped channel semiconductor device.                 
背景技术 Background technique                 
半导体存储器被广泛应用于各种电子产品之中。不同应用领域对半导体存储器的构 造、性能和密度有着不同的要求。如静态随机存储器（SRAM）拥有很高的随机存取速 度和较低的集成密度，而标准的动态随机存储器（DRAM）则具有很高的集成密度和中 等的随机存取速度。当今随着半导体存储器市场需求的不断扩大，动态随机存储器技术 加速发展，许多制约动态随机存储器产品应用的难题正在被不断攻克。 Semiconductor memories are widely used in various electronic products. The structure of semiconductor memory in different application fields           Manufacturing, performance and density have different requirements. Such as static random access memory (SRAM) has a very high random access speed           Degree and low integration density, while standard dynamic random access memory (DRAM) has high integration density and medium           Random access speed. With the ever-expanding demand for semiconductor memory market, dynamic random access memory technology           Accelerated development, many of the problems that constrain the application of dynamic random access memory products are being overcome.                 
中国专利申请200810043070.X公开了一种“半导体存储器器件、半导体存储器阵列 及写入方法”，该半导体存储器器件，包括一个源极、一个漏极、一个浮栅区、一个控制 栅极、一个凹陷沟道区域（亦称U形沟道区）以及一个用于连接浮栅区和漏极的栅控p-n 结二极管；所述半导体存储器器件的浮栅用于存储电荷，它可通过栅控p-n结二极管充 电或放电。虽然该半导体存储器采用了凹陷沟道结构，具有增加源区与漏区之间的电流 沟道区长度和减小芯片尺寸的优点，但也存在以下不足：一是它的源区和漏区凹陷在半 导体衬底内，用漏极接触体作为栅控p-n结二极管的控制栅，使得该半导体存储器与逻 辑电路的兼容性较差；二是由于浮栅仅位于U形的凹槽之内，使得控制栅极通过电容耦 合作用于浮栅的区域仅为U形凹槽的开口区，面积较小，降低了控制栅极对浮栅的电容 耦合率，从而提高了控制栅的操作电压，降低了半导体存储器运行的可靠性。 Chinese Patent Application No. 200810043070.X discloses a "semiconductor memory device, semiconductor memory array           And a writing method", the semiconductor memory device includes a source, a drain, a floating gate region, and a control           a gate, a recessed channel region (also known as a U-shaped channel region), and a gated p-n for connecting the floating gate region and the drain           a junction diode; the floating gate of the semiconductor memory device is used to store charge, which can be charged by a gate-controlled p-n junction diode           Electricity or discharge. Although the semiconductor memory adopts a recessed channel structure, the current between the source and drain regions is increased.           The advantages of the length of the channel region and the reduction of the chip size, but also have the following disadvantages: First, its source and drain regions are recessed in half.           In the conductor substrate, the drain contact body is used as a control gate of the gate-controlled p-n junction diode, so that the semiconductor memory and the logic           The compatibility of the circuit is poor; the second is because the floating gate is only located in the U-shaped groove, so that the control gate is capacitively coupled.           The area used for the floating gate is only the open area of the U-shaped groove, and the area is small, which reduces the capacitance of the control gate to the floating gate.           The coupling ratio, which increases the operating voltage of the control gate, reduces the reliability of semiconductor memory operation.                 
为克服现有技术的不足，中国专利申请201310006320.3公开了“一种平面沟道的半 导体存储器”，如图1所示，它包括：在半导体衬底500内形成的源区501、漏区502和 平面沟道区601；在源区501、沟道区601和漏区502之上形成的第一层绝缘薄膜503和 浮栅505，通过浮栅开口区504在浮栅505与漏区502之间形成有一个p-n结二极管；覆 盖浮栅505和所述的p-n结二极管形成有第二层绝缘薄膜506和控制栅507。该半导体存 储器的优点在于：采用浮栅存储信息，以控制栅为栅极的栅控p-n结二极管对浮栅进行 充电或者放电，可以兼容逻辑电路的制造，而且控制栅在浮栅的上表面及两侧覆盖浮栅， 以有效地增大控制栅与浮栅的接触面积，从而提高了控制栅对浮栅的电容耦合率，数据 读写只需要较低的操作电压。但该半导体存储器也存在以下不足：为保证平面沟道的半 导体存储器的性能，不仅需要延长源区与漏区之间的电流沟道区长度，而且还需要延长 浮栅与电流沟道区之间的寄生MOS管的电流沟道区长度，使得该半导体存储器的单元面 积扩大，从而降低了芯片密度，不利于芯片向微型化方向发展。 In order to overcome the deficiencies of the prior art, Chinese Patent Application 201310006320.3 discloses "a half of a planar channel"           A conductor memory", as shown in FIG. 1, includes: a source region 501, a drain region 502, and a semiconductor substrate 500 formed therein           a planar channel region 601; a first insulating film 503 formed over the source region 501, the channel region 601, and the drain region 502, and           The floating gate 505 is formed with a p-n junction diode between the floating gate 505 and the drain region 502 through the floating gate opening region 504;           The cover floating gate 505 and the p-n junction diode are formed with a second insulating film 506 and a control gate 507. The semiconductor memory           The advantage of the memory is that the floating gate is used to store information, and the gate-controlled gate-controlled p-n junction diode is used to control the floating gate.           Charging or discharging, can be compatible with the manufacture of logic circuits, and the control gate covers the floating gate on the upper surface and both sides of the floating gate.           In order to effectively increase the contact area between the control gate and the floating gate, thereby increasing the capacitive coupling ratio of the control gate to the floating gate, the data           Reading and writing only requires a lower operating voltage. However, the semiconductor memory also has the following disadvantages: to ensure half of the planar channel                               The performance of the conductor memory not only needs to extend the length of the current channel region between the source and drain regions, but also needs to be extended.           The length of the current channel region of the parasitic MOS transistor between the floating gate and the current channel region, so that the unit surface of the semiconductor memory           The expansion of the product reduces the density of the chip, which is not conducive to the development of the chip toward miniaturization.                 
发明内容 Summary of the invention                 
本发明的目的是为克服现有技术的不足而提供一种U形沟道的半导体器件，本发明 是在保持现有技术优点的基础上，通过增加漏区深度来增加浮栅与电流沟道区之间寄生 MOS管的电流沟道区的长度等，从而获得既可降低半导体存储器器件的单元面积和提高 芯片密度，又可提高半导体存储器器件与逻辑电路兼容性及运行可靠性的效果。 The object of the present invention is to provide a U-shaped channel semiconductor device for overcoming the deficiencies of the prior art, the present invention           On the basis of maintaining the advantages of the prior art, the parasitic region between the floating gate and the current channel region is increased by increasing the depth of the drain region.           The length of the current channel region of the MOS transistor, etc., thereby obtaining a reduction in cell area and improvement of the semiconductor memory device           The chip density can improve the compatibility and operational reliability of the semiconductor memory device and the logic circuit.                 
为达到本发明的上述目的，本发明提出了一种U形沟道的半导体器件，它包括： In order to achieve the above object of the present invention, the present invention provides a U-shaped channel semiconductor device comprising:                 
设有U形沟道区的第一种掺杂类型的半导体衬底； a first doping type semiconductor substrate provided with a U-shaped channel region;                 
在所述半导体衬底内设有第二种掺杂类型的源区和漏区，U形沟道区设于源区与漏 区之间； A source region and a drain region of a second doping type are disposed in the semiconductor substrate, and the U-shaped channel region is disposed in the source region and the drain region           Between districts;                 
其特征在于还包括：在所述U形沟道区上设有的第一层绝缘薄膜，该第一层绝缘薄 膜在U形沟道区的两侧分别延伸至源区和漏区的水平表面上； The method further includes: a first insulating film disposed on the U-shaped channel region, the first insulating layer is thin           The film extends on both sides of the U-shaped channel region to the horizontal surfaces of the source and drain regions, respectively;                 
在第一层绝缘薄膜中设有的浮栅开口区，该浮栅开口区位于漏区的水平表面上或侧 壁上； a floating gate opening region provided in the first insulating film, the floating gate opening region being located on a horizontal surface or a side of the drain region           On the wall                 
覆盖所述第一层绝缘薄膜和浮栅开口区的第一种掺杂类型的浮栅； a floating gate of a first doping type covering the first insulating film and the floating gate opening region;                 
在所述浮栅与漏区之间的p-n结二极管； a p-n junction diode between the floating gate and the drain region;                 
覆盖所述浮栅与p-n结二极管的第二层绝缘薄膜，该第二层绝缘薄膜上设有控制栅, 由控制栅、第二层绝缘薄膜和p-n结二极管组成以控制栅为栅极的栅控二极管。 a second insulating film covering the floating gate and the p-n junction diode, and the second insulating film is provided with a control gate.           A gate-controlled diode having a control gate as a gate is composed of a control gate, a second insulating film, and a p-n junction diode.                 
本发明进一步的优化方案在于： A further optimization of the invention lies in:                 
本发明所述第一种掺杂类型为n型、第二种掺杂类型为p型，则所述栅控二极管的 阴极与所述浮栅相连接、栅控二极管的阳极与所述漏区相连接。 The first doping type of the invention is n-type, and the second doping type is p-type, then the gate-controlled diode           A cathode is connected to the floating gate, and an anode of the gated diode is connected to the drain region.                 
本发明所述第一种掺杂类型为p型、第二种掺杂类型为n型，则所述栅控二极管的 阳极与所述浮栅相连接、栅控二极管的阴极与所述漏区相连接。 The first doping type of the present invention is p-type, and the second doping type is n-type, and the gate-controlled diode           An anode is connected to the floating gate, and a cathode of the gated diode is connected to the drain region.                 
本发明所述第一层绝缘薄膜的材质为二氧化硅、氮化硅、氮氧化硅、氧化铪或高介 电常数的绝缘材料，该第一层绝缘薄膜的物理厚度为1-20纳米。 The first insulating film of the present invention is made of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric.           An electrically constant insulating material having a physical thickness of 1 to 20 nm.                 
本发明所述第二层绝缘薄膜的材质为二氧化硅、氮化硅、氮氧化硅、氧化铪或高介 电常数的绝缘材料，该第二层绝缘薄膜的物理厚度为1-20纳米。 The second insulating film of the present invention is made of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric.                               An electrically constant insulating material having a physical thickness of 1 to 20 nm.                 
本发明所述浮栅由多晶硅制成。 The floating gate of the present invention is made of polysilicon.                 
本发明所述控制栅由金属、合金或掺杂的多晶硅制成。 The control gate of the present invention is made of metal, alloy or doped polysilicon.                 
本发明在源区和漏区中分别设有掺杂区，该掺杂区与所属区的掺杂类型相同，且掺 杂浓度高于所属区掺杂浓度。 In the present invention, a doping region is respectively disposed in the source region and the drain region, and the doping region is the same as the doping type of the region, and is doped           The impurity concentration is higher than the doping concentration of the region.                 
本发明与现有技术相比其显著优点在于： The significant advantages of the present invention over the prior art are:                 
一是本发明使浮栅形成于U形凹槽内且向U形凹槽的两侧延伸至源区和漏区的水平 表面上，使得浮栅开口区既可形成于漏区的侧壁上，也可形成于漏区的水平表面上，从 而在延长源区与漏区之间的电流沟道区的基础上还可以提高U形沟道半导体存储器与逻 辑电路的兼容性。 One is that the present invention forms a floating gate in a U-shaped groove and extends to both sides of the U-shaped groove to the level of the source and drain regions.           On the surface, the floating gate opening region can be formed on the sidewall of the drain region or on the horizontal surface of the drain region.           U-shaped channel semiconductor memory and logic can be improved on the basis of extending the current channel region between the source region and the drain region.           Circuit compatibility.                 
二是本发明在U形沟道区的基础上延伸了沿电流沟道区的长度方向上的浮栅长度， 能够增加控制栅通过电容耦合作用于浮栅的面积，从而可以提高控制栅对浮栅的电容耦 合率，降低控制栅操作电压，提高了半导体存储器运行的可靠性并减小了外围控制电路 设计的复杂度。 Second, the present invention extends the length of the floating gate along the length of the current channel region on the basis of the U-shaped channel region.           It can increase the area of the control gate acting on the floating gate through capacitive coupling, thereby improving the capacitive coupling of the control gate to the floating gate.           The combination rate reduces the operating voltage of the control gate, improves the reliability of the operation of the semiconductor memory, and reduces the peripheral control circuit.           The complexity of the design.                 
三是本发明以增加漏区深度来增加浮栅与电流沟道区之间寄生MOS管的电流沟道 区长度，从而可在不增加器件本身尺寸的条件下降低浮栅与电流沟道区之间的寄生MOS 管的漏电流，进一步延长浮栅存储电荷的时间，提高半导体存储器器件运行的可靠性。 Third, the present invention increases the drain region depth to increase the current channel of the parasitic MOS transistor between the floating gate and the current channel region.           The length of the region, so that the parasitic MOS between the floating gate and the current channel region can be reduced without increasing the size of the device itself.           The leakage current of the tube further extends the time for the floating gate to store charge and improves the reliability of operation of the semiconductor memory device.                 
附图说明 DRAWINGS                 
图1为中国专利申请201310006320.3所述平面沟道的半导体存储器的剖面示意图。 1 is a schematic cross-sectional view of a semiconductor memory of a planar channel described in Chinese Patent Application No. 201310006320.3.                 
图2为本发明提出的U形沟道的半导体器件实施例1的剖面示意图。 2 is a cross-sectional view showing a first embodiment of a U-shaped channel semiconductor device according to the present invention.                 
图3为本发明提出的U形沟道的半导体器件实施例2的剖面示意图。 3 is a cross-sectional view showing a second embodiment of a U-shaped channel semiconductor device according to the present invention.                 
图4为本发明提出的U形沟道的半导体器件实施例3的剖面示意图。 4 is a cross-sectional view showing a third embodiment of a U-shaped channel semiconductor device according to the present invention.                 
图5为本发明提出的U形沟道的半导体器件的等效电路示意图。 FIG. 5 is an equivalent circuit diagram of a U-shaped channel semiconductor device according to the present invention.                 
图6至图13为本发明提出的U形沟道的半导体器件的一个实施例的工艺流程示意 图。 6 to FIG. 13 are schematic diagrams showing the process flow of an embodiment of a U-shaped channel semiconductor device according to the present invention.           Figure.                 
具体实施方式 detailed description                                     
为清楚地说明本发明的具体实施方式，说明书附图中所列示图，放大了本发明所述 的层和区域的厚度，且所列图形大小并不代表实际尺寸；附图是示意性的，不应限定本 发明的范围。说明书中所列实施例不应仅限于附图中所示区域的特定形状，而是包括所 得到的形状如制造引起的偏差等、再如刻蚀得到的曲线通常具有弯曲或圆润的特点，但 在本发明实施例中均以矩形表示。 In order to clearly illustrate the specific embodiments of the present invention, the drawings listed in the accompanying drawings illustrate the invention.           The thickness of the layers and regions, and the size of the listed figures does not represent the actual size; the drawings are schematic and should not be limited           The scope of the invention. The embodiments listed in the specification should not be limited to the specific shapes of the regions shown in the drawings, but rather include           The resulting shape is such as a deviation caused by manufacturing, and the curve obtained by etching is usually curved or rounded, but           In the embodiments of the present invention, they are all represented by rectangles.                 
下面结合附图和实施例对本发明的具体实施方式作进一步详细的说明。 The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.                 
图2、图3和图4是本发明所提出的一种U形沟道的半导体器件的三个实施例，它 们是沿器件电流沟道长度方向的剖面图。如图2、图3和图4所示，本发明提出的一种U 形沟道的半导体器件，它包括一个具有第一种掺杂类型的半导体衬底200以及在半导体 衬底200内形成的具有第二种掺杂类型的源区201和漏区202；所述半导体衬底200的材 质为单晶硅、多晶硅或绝缘体上的硅；所述第一种掺杂类型为n型、第二种掺杂类型为p 型，或者所述第一种掺杂类型为p型、第二种掺杂类型为n型。 2, 3 and 4 are three embodiments of a U-shaped channel semiconductor device proposed by the present invention, which           They are cross-sectional views along the length of the current channel of the device. As shown in FIG. 2, FIG. 3 and FIG. 4, a U proposed by the present invention           a channel shaped semiconductor device comprising a semiconductor substrate 200 having a first doping type and a semiconductor           a source region 201 and a drain region 202 having a second doping type formed in the substrate 200; a material of the semiconductor substrate 200           The quality is monocrystalline silicon, polycrystalline silicon or silicon on insulator; the first doping type is n type, and the second doping type is p           Type, or the first doping type is p-type and the second doping type is n-type.                 
凹陷在半导体衬底200内且介于源区201和漏区202之间形成的U形凹槽，在半导 体衬底内、U形凹槽的表面形成有器件的U形沟道区401，U形沟道区401是该U形沟 道的半导体器件在进行工作时在半导体衬底200内形成的反型层。 a U-shaped recess recessed in the semiconductor substrate 200 and between the source region 201 and the drain region 202, in the semiconductor           The U-shaped channel region 401 of the device is formed in the surface of the U-shaped groove in the bulk substrate, and the U-shaped channel region 401 is the U-shaped groove.           The inverting layer formed in the semiconductor substrate 200 during operation of the semiconductor device.                 
覆盖整个U形沟道区401且延伸至源区201和漏区202的水平表面上形成有第一层 绝缘薄膜203，在第一层绝缘薄膜203中形成有一个浮栅开口区204，该浮栅开口区204 可形成位于漏区202的水平表面上，如图2和图3所示的结构，也可形成位于漏区202 侧面上，即位于U形凹槽侧壁上的第一层绝缘薄膜203中，如图4所示的结构。 A first layer is formed on a horizontal surface covering the entire U-shaped channel region 401 and extending to the source region 201 and the drain region 202           The insulating film 203 is formed with a floating gate opening region 204 in the first insulating film 203, and the floating gate opening region 204           It may be formed on the horizontal surface of the drain region 202, as shown in FIGS. 2 and 3, or may be formed in the drain region 202.           On the side, that is, in the first insulating film 203 on the side wall of the U-shaped groove, as shown in FIG.                 
在第一层绝缘薄膜203上且覆盖整个U形沟道区401和浮栅开口区204形成有一个 作为电荷存储节点的具有第一种掺杂类型的浮栅205；第一层绝缘薄膜203的材质为二氧 化硅、氮化硅、氮氧化硅、氧化铪或高介电常数的绝缘材料，其物理厚度为1-20纳米。 浮栅205具有与漏区202相反的掺杂类型，且浮栅205中的掺杂杂质会通过浮栅开口区 204扩散至漏区202中形成具有第一种掺杂类型的扩散区402，从而通过浮栅开口区204 在浮栅205与漏区202之间形成一个p-n结二极管。 Formed on the first insulating film 203 and covering the entire U-shaped channel region 401 and the floating gate opening region 204           a floating gate 205 having a first doping type as a charge storage node; the first insulating film 203 is made of a dioxygen           Silicon, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric constant insulating material having a physical thickness of 1-20 nm.           The floating gate 205 has a doping type opposite to the drain region 202, and the doping impurities in the floating gate 205 pass through the floating gate opening region.           204 diffuses into the drain region 202 to form a diffusion region 402 having a first doping type, thereby passing through the floating gate opening region 204           A p-n junction diode is formed between the floating gate 205 and the drain region 202.                 
覆盖浮栅205和所述的p-n结二极管形成有第二层绝缘薄膜206，该第二层绝缘薄膜 206的材质为二氧化硅、氮化硅、氮氧化硅、氧化铪或高介电常数的绝缘材料，其物理厚 度为1-20纳米；在第二层绝缘薄膜206之上且覆盖浮栅205形成有器件的控制栅207， 该控制栅207的材质为金属、合金或为掺杂的多晶硅；控制栅207、第二层绝缘薄膜206、 所述p-n结二极管组成以控制栅207为栅极的栅控二极管。控制栅207既可在浮栅205 的顶部及两侧同时覆盖浮栅，以提高控制栅耦合率，如图2和图4所示的结构；控制栅 207也可在浮栅205的顶部及靠近漏区的一侧覆盖浮栅205，如图3所示的结构。 The floating gate 205 and the p-n junction diode are formed with a second insulating film 206, the second insulating film           The material of 206 is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric constant insulating material, and its physical thickness is           a degree of 1-20 nm; a control gate 207 formed on the second insulating film 206 and covering the floating gate 205 is formed with a device,           The control gate 207 is made of metal, alloy or doped polysilicon; the control gate 207, the second insulating film 206,           The p-n junction diode constitutes a gated diode with the control gate 207 as the gate. Control gate 207 can be in floating gate 205                               The top and sides of the same cover the floating gate to improve the control gate coupling ratio, as shown in Figure 2 and Figure 4;           207 may also cover floating gate 205 at the top of floating gate 205 and on the side near the drain region, as shown in FIG.                 
在所述控制栅207的两侧形成有器件的栅极侧墙208，该栅极侧墙208的材质为二氧 化硅或氮化硅，栅极侧墙是业界所熟知的结构，用于将控制栅207与器件中的其它导电 层隔离。 A gate spacer 208 of the device is formed on both sides of the control gate 207, and the gate spacer 208 is made of dioxane.           Silicon or silicon nitride, gate spacers are well known in the art for use in controlling gate 207 and other conductive devices in the device.           Layer isolation.                 
在所述源区201和漏区202内还分别形成有与源区201和漏区202相同掺杂类型的 掺杂区209和掺杂区210，该掺杂区209和掺杂区210的掺杂浓度明显高于源区201和漏 区202的掺杂浓度，用于降低器件的欧姆接触。 Also formed in the source region 201 and the drain region 202 are the same doping type as the source region 201 and the drain region 202, respectively.           The doping region 209 and the doping region 210, the doping concentration of the doping region 209 and the doping region 210 are significantly higher than that of the source region 201 and the drain region           The doping concentration of region 202 is used to reduce the ohmic contact of the device.                 
本发明的U形沟道的半导体器件还可以包括由导电材料形成的用于将所述源区、控 制栅、漏区、半导体衬底与外部电极相连接的源区的接触体211、控制栅的接触体212、 漏区的接触体213和半导体衬底的接触体214。 The U-shaped channel semiconductor device of the present invention may further include a conductive material formed for the source region, and the control           a gate body, a drain region, a contact region 211 of the source region where the semiconductor substrate is connected to the external electrode, a contact body 212 of the control gate,           The contact body 213 of the drain region and the contact body 214 of the semiconductor substrate.                 
为进一步详细地描述本发明所公开的U形沟道的半导体器件的结构和功能，图5展 示了本发明的U形沟道的半导体器件的等效电路图。如图5所示，本发明的U形沟道的 半导体器件包含一个具有源极332、漏极330、浮栅333和控制栅331的MOSFET336 以及一个以MOSFET336的控制栅331为栅极的栅控二极管335。MOSFET336的浮栅 333可以与栅控二极管335的阳极相连接，也可以与栅控二极管335的阴极相连接，在本 发明的图5所示的实施例中，浮栅333与栅控二极管335的阳极相连接；通过对控制栅 331、漏极330和源极331施加适当的电压，栅控二极管335可以对浮栅333进行充电或 放电以此来改变储存在浮栅333内的电荷数量，该电荷数量决定了该U形沟道的半导体 器件的逻辑状态。 To further describe in detail the structure and function of the U-shaped channel semiconductor device disclosed in the present invention, FIG.           An equivalent circuit diagram of a semiconductor device of a U-shaped channel of the present invention is shown. As shown in FIG. 5, the U-shaped channel of the present invention           The semiconductor device includes a MOSFET 336 having a source 332, a drain 330, a floating gate 333, and a control gate 331           And a gated diode 335 having a gate MOSFET 336 as its gate. Floating gate of MOSFET336           333 may be connected to the anode of the gated diode 335 or may be connected to the cathode of the gated diode 335.           In the embodiment shown in FIG. 5 of the invention, the floating gate 333 is connected to the anode of the gated diode 335;           331. The drain 330 and the source 331 apply an appropriate voltage, and the gate diode 335 can charge the floating gate 333 or           The discharge thereby changes the amount of charge stored in the floating gate 333, the amount of which determines the semiconductor of the U-shaped channel           The logic state of the device.                 
以上本发明公开的U形沟道的半导体器件可通过多种方法制造。以下根据图3所示 的U形沟道的半导体器件结构，结合图6至图13进一步说明本发明一个实施例的工艺流 程的具体步骤： The above U-shaped channel semiconductor device disclosed in the present invention can be fabricated by various methods. The following is shown in Figure 3.           U-shaped channel semiconductor device structure, further illustrating the process flow of one embodiment of the present invention with reference to FIGS. 6 to 13           The specific steps of the process:                 
步骤一，如图6所示，在提供的具有第一种掺杂类型的半导体衬底200内通过浅沟 槽隔离（STI）工序形成有源区（图6中未示出）,这种STI工艺是业界所熟知的。然后 通过离子注入工艺在半导体衬底200内形成具有第二种掺杂类型的轻掺杂区300；其中： 半导体衬底200的材质为单晶硅、多晶硅或者为绝缘体上的硅。所述的第一种掺杂类型 为p型，所述的第二种掺杂类型为n型。 Step one, as shown in FIG. 6, passes through the shallow trench in the provided semiconductor substrate 200 having the first doping type.           The trench isolation (STI) process forms an active region (not shown in Figure 6) which is well known in the art. then           A lightly doped region 300 having a second doping type is formed in the semiconductor substrate 200 by an ion implantation process; wherein:           The material of the semiconductor substrate 200 is monocrystalline silicon, polycrystalline silicon or silicon on insulator. The first type of doping           For the p-type, the second doping type is n-type.                 
步骤二，在半导体衬底200的表面淀积一层硬掩膜层301，该硬掩膜层301的材质为 氮化硅。接着在硬掩膜层301之上淀积一层光刻胶302并掩膜、曝光、显影定义出器件 的U形沟道区的位置，然后刻蚀掉暴露的硬掩膜层301，并以硬掩膜层301为掩膜通过 湿法刻蚀和干法刻蚀相结合的方法刻蚀暴露出的半导体衬底200，从而形成凹陷在半导体 衬底200的U形凹槽，该U形凹槽将具有第二种掺杂类型的轻掺杂区300隔离成两个部 分，分别作为器件的源区201和漏区202，如图7所示。 Step 2, depositing a hard mask layer 301 on the surface of the semiconductor substrate 200. The material of the hard mask layer 301 is           Silicon nitride. A layer of photoresist 302 is then deposited over the hard mask layer 301 and masked, exposed, and developed to define the device.                               Position of the U-shaped channel region, then etching away the exposed hard mask layer 301 and passing the hard mask layer 301 as a mask           A combination of wet etching and dry etching etches the exposed semiconductor substrate 200 to form a recess in the semiconductor           a U-shaped groove of the substrate 200, the U-shaped groove isolating the lightly doped region 300 having the second doping type into two portions           The points are respectively taken as the source region 201 and the drain region 202 of the device, as shown in FIG.                 
步骤三，剥除光刻胶303并继续刻蚀掉剩余的硬掩膜层301，接着在半导体衬底200 的暴露表面上生长第一层绝缘薄膜203，该第一层绝缘薄膜203的材质为氧化硅、氮化硅、 氮氧化硅或者为氧化铪等高介电常数的绝缘材料，其物理厚度为1-20纳米；接着在第一 层绝缘薄膜203之上淀积一层光刻胶并通过光刻工艺确定浮栅开口区的位置，然后以光 刻胶为掩膜刻蚀掉暴露出的第一层绝缘薄膜203，从而在位于漏区202水平表面上的第一 层绝缘薄膜203中形成一个浮栅开口区204，然后剥除光刻胶，形成如图8a所示的结构。 Step three, stripping the photoresist 303 and continuing to etch away the remaining hard mask layer 301, followed by the semiconductor substrate 200.           A first insulating film 203 is grown on the exposed surface, and the first insulating film 203 is made of silicon oxide or silicon nitride.           Silicon oxynitride or a high dielectric constant insulating material such as yttria, having a physical thickness of 1-20 nm;           Depositing a layer of photoresist on the layer of insulating film 203 and determining the position of the floating gate opening region by photolithography, and then using light           The first layer of the insulating film 203 is etched away as a mask, so as to be first on the horizontal surface of the drain region 202.           A floating gate opening region 204 is formed in the layer insulating film 203, and then the photoresist is stripped to form a structure as shown in Fig. 8a.                 
可选的，浮栅开口区204也可形成位于漏区202侧面之上，即位于U形凹槽侧壁上 的第一层绝缘薄膜203中，如图8b所示的结构。在形成如图8b所示的浮栅开口区204 之后，通过与下面所描述的相同的工艺步骤即可形成如图4所示的U形沟道半导体器件 的结构，制备该结构时的各个工艺过程中的结构在本实施例中不再详细描述。 Optionally, the floating gate opening region 204 may also be formed on the side of the drain region 202, that is, on the sidewall of the U-shaped groove.           In the first insulating film 203, as shown in Fig. 8b. Forming a floating gate opening region 204 as shown in FIG. 8b           Thereafter, a U-channel semiconductor device as shown in FIG. 4 can be formed by the same process steps as described below.           The structure of each process in the preparation of the structure will not be described in detail in this embodiment.                 
步骤四，在已形成结构的暴露表面上淀积一层具有第一种掺杂类型的第一层导电薄 膜，该导电薄膜为具有p型掺杂类型的多晶硅；接着在所形成的第一层导电薄膜之上淀 积一层光刻胶并通过光刻工艺确定浮栅的位置，然后以光刻胶为掩膜刻蚀掉暴露出的第 一层导电薄膜，刻蚀后剩余的第一层导电薄膜形成器件的浮栅205；浮栅205至少覆盖整 个U形凹槽和浮栅开口区204，浮栅205中的掺杂杂质会通过在浮栅205之下的浮栅开 口区域204扩散至漏区202中形成p型扩散区402，且通过浮栅开口区域204在浮栅205 与漏区202之间形成的一个p-n结二极管；接着继续刻蚀掉暴露出的第一层绝缘薄膜203， 剥除光刻胶后如图9所示。 Step 4, depositing a first layer of conductive thin film having a first doping type on the exposed surface of the formed structure           a film, the conductive film being polycrystalline silicon having a p-type doping type; and then depositing over the formed first layer of conductive film           A layer of photoresist is deposited and the position of the floating gate is determined by a photolithography process, and then exposed by photoresist as a mask           a conductive film, the first conductive film remaining after etching forms the floating gate 205 of the device; the floating gate 205 covers at least the entire           U-shaped recesses and floating gate opening regions 204, the doping impurities in the floating gate 205 will pass through the floating gate below the floating gate 205           The port region 204 diffuses into the drain region 202 to form a p-type diffusion region 402, and passes through the floating gate opening region 204 at the floating gate 205.           a p-n junction diode formed between the drain region 202; and then continuing to etch away the exposed first insulating film 203,           After stripping the photoresist, it is as shown in FIG.                 
步骤五，在已形成结构的暴露表面上淀积形成第二层绝缘薄膜206，该第二层绝缘薄 膜206的材质为氧化硅、氮化硅、氮氧化硅或氧化铪等高介电常数的绝缘材料，其物理 厚度为1-20纳米；接着在第二层绝缘薄膜206之上淀积形成第二层导电薄膜207，第二 层导电薄膜207的材质为金属、合金或掺杂的多晶硅；然后在第二层导电薄膜207之上 淀积一层光刻胶并通过光刻工艺确定器件的控制栅的位置，接着以光刻胶为掩膜刻蚀掉 暴露出的第二层导电薄膜，刻蚀后剩余的第二层导电薄膜形成器件的控制栅207，控制栅 207在沿沟道方向上的长度应超过浮栅205，在浮栅205的顶部及两侧覆盖浮栅205，剥 除光刻胶后如图10a所示。 Step 5, depositing a second insulating film 206 on the exposed surface of the formed structure, the second layer is thin           The material of the film 206 is a high dielectric constant insulating material such as silicon oxide, silicon nitride, silicon oxynitride or hafnium oxide, and its physics           a thickness of 1-20 nm; then depositing a second conductive film 207 over the second insulating film 206, the second           The layer conductive film 207 is made of metal, alloy or doped polysilicon; then on the second conductive film 207           Depositing a layer of photoresist and determining the position of the control gate of the device by photolithography, and then etching away with photoresist as a mask           The exposed second conductive film, the second conductive film remaining after etching forms the control gate 207 of the device, and the control gate           The length of 207 in the direction along the channel should exceed the floating gate 205, and the floating gate 205 is covered on the top and both sides of the floating gate 205, and stripped           This is shown in Figure 10a except for the photoresist.                                     
可选的，通过控制光刻掩膜版上的图形，对第二层绝缘薄膜206进行刻蚀时，可以 刻蚀掉在浮栅205靠近源区201一侧的第二层导电薄膜206，仅保留在浮栅205靠近漏区 202一侧的第二层导电薄膜206，以形成只在浮栅205顶部及靠近漏区的一侧覆盖浮栅205 的控制栅207，如图10b所示，然后通过与下面所描述的相同的工艺步骤即可形成如图2 所示U形沟道半导体器件的结构，制备该结构时的各个工艺过程中的结构在本实施例中 不再详细描述。 Optionally, when the second insulating film 206 is etched by controlling the pattern on the lithography mask,           Etching off the second conductive film 206 on the side of the floating gate 205 near the source region 201, leaving only the floating gate 205 near the drain region           The second conductive film 206 on one side of the 202 is formed to cover the floating gate 205 only on the top of the floating gate 205 and on the side close to the drain region.           The control gate 207, as shown in Figure 10b, is then formed by the same process steps as described below.           The structure of the U-channel semiconductor device shown, the structure in each process when the structure is prepared is in this embodiment           No longer described in detail.                 
步骤六，在已形成结构的暴露表面上淀积形成第三层绝缘薄膜，接着对所形成的第 三层绝缘薄膜进行回刻以在控制栅207的两侧形成栅极侧墙208，该工艺是业界所熟知 的，剥除光刻胶后如图10所示。栅极侧墙208可以为氧化硅或者氮化硅。 Step six, depositing a third insulating film on the exposed surface of the formed structure, and then forming the first           The three layers of insulating film are etched back to form gate spacers 208 on both sides of the control gate 207, which is well known in the art.           After stripping the photoresist, it is shown in FIG. The gate spacer 208 can be silicon oxide or silicon nitride.                 
步骤七，进行第二种掺杂类型（n型）的杂质离子注入，对控制栅207和未被控制栅 207覆盖的半导体衬底200进行掺杂，形成控制栅207的掺杂结构，并在源区201和漏区 202中分别形成高浓度的掺杂区209和掺杂区210，如图12所示。 Step 7: performing impurity ion implantation of a second doping type (n-type), for the control gate 207 and the uncontrolled gate           The semiconductor substrate 200 covered by 207 is doped to form a doping structure of the control gate 207, and is in the source region 201 and the drain region.           A high concentration doped region 209 and doped region 210 are formed in 202, respectively, as shown in FIG.                 
步骤八，以导电材料形成用于将源区201、控制栅207、漏区202、半导体衬底200 与外部电极相连接的源区的接触体211、控制栅的接触体212、漏区的接触体213以及半 导体衬底的接触体214，如图13所示。 Step eight, forming a conductive material for using the source region 201, the control gate 207, the drain region 202, and the semiconductor substrate 200           Contact body 211 of source region connected to external electrode, contact body 212 of control gate, contact body 213 of drain region, and half           The contact body 214 of the conductor substrate is as shown in FIG.                 
本发明的具体实施方式中凡未涉到的说明属于本领域的公知技术，可参考公知技术 加以实施。 The descriptions not mentioned in the specific embodiments of the present invention belong to the well-known technology in the art, and can refer to the known technology.           Implement it.                 
以上具体实施方式及实施例是对本发明提出的一种U形沟道的半导体器件技术思想 的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本 技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范 围。 The above specific embodiments and examples are the technical idea of a U-shaped channel semiconductor device proposed by the present invention.           The specific support cannot limit the scope of protection of the present invention, and the technical idea according to the present invention is           Any equivalent changes or equivalent changes made on the basis of the technical solutions still belong to the scope of protection of the technical solutions of the present invention.           Wai.                                     

Claims (7)

  1. 一种U形沟道的半导体器件，它包括： A U-shaped channel semiconductor device comprising:                       
    设有U形沟道区的第一种掺杂类型的半导体衬底； a first doping type semiconductor substrate provided with a U-shaped channel region;                       
    在所述半导体衬底内设有第二种掺杂类型的源区和漏区，U形沟道区设于源区与漏区 之间； Providing a source region and a drain region of a second doping type in the semiconductor substrate, the U-shaped channel region being disposed in the source region and the drain region              between;                       
    其特征在于还包括： It is also characterized by:                       
    在所述U形沟道区上设有的第一层绝缘薄膜，该第一层绝缘薄膜在U形沟道区的两 侧分别延伸至源区和漏区的水平表面上； a first insulating film disposed on the U-shaped channel region, the first insulating film in the U-shaped channel region              The sides extend to the horizontal surfaces of the source and drain regions, respectively;                       
    在第一层绝缘薄膜中设有的浮栅开口区，该浮栅开口区位于漏区的水平表面上或侧 壁上； a floating gate opening region provided in the first insulating film, the floating gate opening region being located on a horizontal surface or a side of the drain region              On the wall                       
    覆盖所述第一层绝缘薄膜和浮栅开口区的第一种掺杂类型的浮栅； a floating gate of a first doping type covering the first insulating film and the floating gate opening region;                       
    在所述浮栅与漏区之间的p-n结二极管； a p-n junction diode between the floating gate and the drain region;                       
    覆盖所述浮栅与p-n结二极管的第二层绝缘薄膜，该第二层绝缘薄膜上设有控制栅, 由控制栅、第二层绝缘薄膜和p-n结二极管组成以控制栅为栅极的栅控二极管。 a second insulating film covering the floating gate and the p-n junction diode, and the second insulating film is provided with a control gate.              A gate-controlled diode having a control gate as a gate is composed of a control gate, a second insulating film, and a p-n junction diode.                       
  2. 根据权利要求1所述的U形沟道的半导体器件，其特征在于所述第一种掺杂类型 为n型、第二种掺杂类型为p型，则所述栅控二极管的阴极与所述浮栅相连接、栅控二 极管的阳极与所述漏区相连接。 The U-channel semiconductor device of claim 1 wherein said first doping type              The n-type, the second doping type is p-type, the cathode of the gate-controlled diode is connected to the floating gate, and the gate is controlled              The anode of the pole tube is connected to the drain region.                       
  3. 根据权利要求1所述的U形沟道的半导体器件，其特征在于所述第一种掺杂类型 为p型、第二种掺杂类型为n型，则所述栅控二极管的阳极与所述浮栅相连接、栅控二 极管的阴极与所述漏区相连接。 The U-channel semiconductor device of claim 1 wherein said first doping type              a p-type, the second doping type is n-type, the anode of the gated diode is connected to the floating gate, and the gate is controlled              A cathode of the pole tube is connected to the drain region.                       
  4. 根据权利要求1至3所述的U形沟道的半导体器件，其特征在于所述第一层绝缘 薄膜的材质为二氧化硅、氮化硅、氮氧化硅、氧化铪或高介电常数的绝缘材料，该第一 层绝缘薄膜的物理厚度为1-20纳米。 The U-shaped channel semiconductor device according to any one of claims 1 to 3, characterized in that said first layer is insulated              The material of the film is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or high dielectric constant insulating material, the first              The layer insulating film has a physical thickness of 1 to 20 nm.                       
  5. 根据权利要求1至3所述的U形沟道的半导体器件，其特征在于所述第二层绝缘 薄膜的材质为二氧化硅、氮化硅、氮氧化硅、氧化铪或高介电常数的绝缘材料，该第二 层绝缘薄膜的物理厚度为1-20纳米。 The U-shaped channel semiconductor device according to any one of claims 1 to 3, characterized in that said second layer is insulated              The material of the film is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide or a high dielectric constant insulating material, the second              The layer insulating film has a physical thickness of 1 to 20 nm.                       
  6. 根据权利要求1至3所述的U形沟道的半导体器件，其特征在于所述浮栅由多晶 硅制成。 The U-shaped channel semiconductor device according to any one of claims 1 to 3, wherein said floating gate is polycrystalline              Made of silicon.                       
  7. 根据权利要求1至3所述的U形沟道的半导体器件，其特征在于在源区和漏区中 分别设有掺杂区，该掺杂区与所属区的掺杂类型相同，且掺杂浓度高于所属区掺杂浓 度。 The U-shaped channel semiconductor device according to any one of claims 1 to 3, characterized in that in the source region and the drain region              Doped regions are respectively provided, the doping region is the same as the doping type of the region, and the doping concentration is higher than the doping concentration of the region              degree.                                                 
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