WO2015131527A1

WO2015131527A1 - Semi-floating gate device and preparation method therefor

Info

Publication number: WO2015131527A1
Application number: PCT/CN2014/090364
Authority: WO
Inventors: 杨喜超; 赵静; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2014-03-04
Filing date: 2014-11-05
Publication date: 2015-09-11
Also published as: CN103887313B; CN103887313A

Abstract

A semi-floating gate device and a preparation method therefor, which are used for solving a plurality of defects that the existing semi-floating gate transistor has. The semi-floating device comprises: a semiconductor substrate (300) having a first doping type; a convex body (301) formed on the surface of the semiconductor substrate (300); a drain region (310) which is formed at one side of the semiconductor substrate (300) and has a second doping type, wherein the drain region is connected to the convex body; a source region (309) which is formed at the other side of the semiconductor substrate and has a second doping type, wherein the source region is connected to the drain region via a channel region (302); a first layer of an insulation thin film (303) which covers the channel region and a side wall of the convex body facing the source region; a floating gate (305) which is formed on the first layer of an insulation thin film and the convex body and has a first doping type, wherein the floating gate is connected to the drain region via the convex body; a second layer of an insulation thin film (306); and a control gate (307) which is formed on the second layer of an insulation thin film and covers the floating gate and the convex body.

Description

Semi-floating gate device and preparation method thereof

The present application claims priority to Chinese Patent Application No. 201410077052.9, entitled "A Semi-Floating Gate Device and Its Preparation Method", filed on March 4, 2014, the entire contents of In this application.

Technical field

The present invention relates to the field of semiconductor technologies, and in particular, to a semi-floating gate device and a method for fabricating the same.

Background technique

Semiconductor memories are used in various electronic fields. Among them, Nonvolatile Memory (NVM) can save data for a long time in case of power failure. Floating Gate Transistor (FGT) is the mainstream structure for many variants of non-volatile memory.

FGT is similar in structure to Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It can be seen as a single-layer gate dielectric layer in a MOSFET. A charge storage layer is embedded in two insulators. The "sandwich" grid of layer) is shown in Figure 1. Among them, the charge storage layer is called a floating gate because it is surrounded by an insulating layer. The amount of stored charge in the floating gate can adjust the magnitude of the transistor threshold voltage, ie, "0" and "1" corresponding to logic. There are two ways to charge the floating gate: tunneling (Fowler-Nordheim) and hot carrier injection. Both of these methods require higher operating voltages and lower carrier injection efficiency, so there are power and speed issues.

In order to further improve the performance of non-volatile memory, a concept of a semi-floating gate transistor (SFGT) is proposed, that is, a window is opened at the insulating layer of the drain region and the floating gate transistor, and tunneling is performed through the plane embedded in the drain region. A Field Effect Field Effect Transistor (TFET) implements charging and discharging of the floating gate. The semi-floating gate transistor uses a tunneling mechanism between the layers, which greatly reduces the operating voltage of the device and increases the operating speed of the device.

A conventional semi-floating gate transistor is shown in Figure 2a. The key change of the semi-floating gate transistor shown in FIG. 2a relative to the floating gate transistor is that the insulating layer 503 between the floating gate 505 and the drain region 510 opens a window 504, thereby doping the region 602, doping region 502, doping The drain region 510 and the control gate 507 and the insulating layer 506 form a planar TFET such that the originally electrically insulated floating gate becomes the semi-floating gate 505. In Fig. 2a, reference numeral 500 denotes a substrate, 509 denotes a doped source region, 501 is a doped region, and 508 is Insulating spacers, 511, 512, and 513 are electrodes.

Taking an N-type semi-floating gate device as an example, when the control gate 507 applies a negative bias voltage and the drain region 510 applies a positive bias voltage, the planar TFET device is turned on, and inter-band tunneling occurs, and charges are injected into the doped region 602. Among the half floating gates 505, the amount of charge in the half floating gate 505 is increased, that is, the logic "1" is written; when the control gate 507 applies a positive bias and the drain region 510 applies a negative bias, the embedded diode (doped region) 602 and PMOS junction 502 form a positive bias, which will cause the stored charge in the half floating gate 505 to be released through the doped region 602, resulting in a decrease in the amount of charge in the half floating gate, ie, writing a logic "0". Due to its unique charge injection/release mechanism, the operating voltage of the device is greatly reduced and the device speed is greatly improved.

However, the SFGT shown in Figure 2a has the following drawbacks:

1. The embedded TFET is a planar structure and needs to occupy more substrate area; and the size of the window is limited by the lithography precision; therefore, the integration density of the chip will be reduced.

2. The doped region 602 of the embedded planar TFET is opposite to the doping type of the drain region 510 of the SFGT, and an additional barrier is introduced in the drain region, which affects carrier transport of the gate dielectric layer and the semiconductor interface, reducing leakage. The efficiency of the extraction of the carrier, thereby detracting from the read rate of the stored data.

3. The doped region 602 and the doped region 502 form a PN junction. The built-in potential mainly exists in the doped region 502, and the restriction on the carrier in the semi-floating gate region is weak, so that the leakage control of the semi-floating gate is weak. , affecting the stability of data storage.

Another conventional semi-floating gate transistor is shown in Figure 2b. The SFGT shown in Figure 2b reduces the area of the overall SFGT device by employing a vertical channel 401. The source region 201 is placed at the bottom of the trench by shallow trench isolation techniques, and the source region 201 is connected to the drain region 210 by a vertical channel 401. The semi-floating gate 205 and the control gate 207 are both placed inside the trench, saving device footprint. The doped region 402, the doped region 202, and the doped source region 210 constitute a TFET structure, and the half floating gate 205 is connected to the drain region 210 through the sidewall window 204 to charge and discharge the floating gate 205. In Fig. 2b, reference numeral 200 denotes a substrate, 203 and 206 denote insulating layers, 208 is an insulating spacer, and 211, 212, 213 are electrodes.

As shown in Fig. 2b, by opening the trench, the occupied area of the device is reduced, the integration density of the chip is improved, and the first defect of the SFGT shown in Fig. 2a can be effectively improved.

However, as shown in Fig. 2b, the SFGT, whose embedded TFET is still a planar structure, still has the above-mentioned second and third defects of the SFGT as shown in Fig. 2a.

In addition, the SFGT shown in Figure 2b uses a vertical channel, and the carrier mobility in the vertical direction is reduced (refer to the industry's conventional 100 silicon substrate, the vertical direction is 110, the electron mobility is decreased), The data read speed of the device is reduced; and the process of the SFGT shown in FIG. 2b is complicated, for example, the lithography step of the sidewall window 204 presents a very large challenge.

Summary of the invention

Embodiments of the present invention provide a semi-floating gate device and a method of fabricating the same to solve the above various defects of the conventional semi-floating gate transistor.

A first aspect of the present invention provides a semi-floating gate device comprising: a semiconductor substrate having a first doping type; a protrusion formed on a surface of the semiconductor substrate, the protrusion being perpendicular to the semiconductor liner a silicon fin or a silicon nanowire of a bottom surface; a drain region having a second doping type formed on one side of the semiconductor substrate, a partial region of the drain region being located under the protrusion and a convex body connected; a source region having a second doping type formed on the other side of the semiconductor substrate, the source region passing through the semiconductor substrate having a first doping type a channel region and the drain region; a first insulating film covering the channel region and a sidewall of the protrusion facing the source region; and the first insulating film and the protrusion a floating gate formed on the first doping type, the floating gate being connected to the drain region through the convex body; covering the source region, the floating gate, the drain region, and the a second insulating film of the convex body; formed on the second insulating film to cover the floating And a control gate of the convex body.

In a first possible implementation, the semi-floating gate device further includes: electrodes formed on the drain region and the source region and the control gate respectively; and, in the drain region and the Between the control gates, an insulating spacer is formed between the source region and the control gate, respectively.

In conjunction with the first aspect of the present invention or the first possible implementation of the first aspect, in a second possible implementation, the floating gate serves as a charge storage layer; the floating gate, the convex body, the a drain region, the second insulating film, and the control gate form a vertical tunneling field effect transistor TFET having a gate as the gate, the protrusion serving as a channel connection of the vertical TFET The floating gate and the drain region, the control gate is capable of controlling the on and off of current in the vertical TFET by electric field regulation; and the control gate is located on the second insulating film above the channel region In the above, the on and off of the current in the channel region can be controlled by electric field regulation.

In conjunction with the first aspect of the present invention or any one of the first to second possible implementations of the first aspect, in a third possible implementation, the first doping type is n-type, The second doping type is p-type; or the first doping type is p-type and the second doping type is n-type.

With reference to the first aspect of the present invention or any one of the first to third possible implementations of the first aspect, in a fourth possible implementation, the first insulating film is silicon dioxide, Silicon nitride or silicon oxynitride, the second insulating film is silicon dioxide, silicon nitride or silicon oxynitride, the floating gate is doped polysilicon, and the control gate is metal, alloy or doped Polysilicon.

In combination with the first aspect of the invention or any one of the first to fourth possible implementations of the first aspect, in a fifth possible implementation, the electrode is aluminum or copper or aluminum alloy or copper An alloy; the spacer is silicon dioxide, silicon nitride or silicon oxynitride.

A second aspect of the present invention provides a method of fabricating a semi-floating gate device as described above, comprising: depositing a first hard mask layer on a surface of a semiconductor substrate having a first doping type and performing a photolithography process and etching The process defines a position of a convex body of the device, the convex body is a silicon fin or a silicon nanowire; etching the exposed semiconductor substrate by using the first hard mask layer as a mask to form the convex body, engraving The depth of the etch is greater than the thickness of the first insulating film; the first insulating film is formed on the surface of the formed structure; the remaining first hard mask layer is etched; and the surface of the semiconductor substrate is deposited a first conductive film of a doping type; a second hard mask layer is deposited on the surface of the first conductive film, and a floating gate of the device is defined by a photolithography process and an etching process, the second hard Masking layer covering the convex body; etching the first conductive film with the second hard mask layer as a mask to form the floating gate, and etching the semiconductor substrate and the first layer Interface of the insulating film; etching away the remaining second hard mask layer; Forming a second insulating film on the surface of the formed structure; depositing a second conductive film on the second insulating film, and processing the second conductive film by a photolithography process and an etching process to form a cover The floating gate and the control gate of the protrusion; conducting a second doping type of ion implantation to dope the semiconductor substrate not covered by the control gate to form a source region and a drain region of the device.

In a first possible implementation, before performing the ion implantation of the second doping type, the method further comprises: respectively forming spacers on both sides of the control gate.

In combination with the second aspect of the invention or the first possible implementation of the second aspect, In an energy implementation manner, the method further includes: opening the drain and source regions and the electrode window of the control gate by photolithography, depositing metal in the electrode window, and forming electrodes on the drain region and the source region and the control gate, respectively.

In conjunction with the second aspect of the present invention or any one of the first to second possible implementations of the second aspect, in a third possible implementation, the first doping type is an n-type, The second doping type is p-type; or the first doping type is p-type and the second doping type is n-type.

It can be seen from the above that the semi-floating gate device of the embodiment of the present invention forms a vertical structure TFET embedded in the floating gate by a convex body formed on the surface of the semiconductor substrate, and thus has the following technical effects:

1. The embedded vertical TFET occupies a small area of the semiconductor substrate, which is beneficial to the improvement of chip integration density; during the process of manufacturing, the width of the convex body can be further reduced, and the requirement of the semiconductor substrate area of the device is reduced. The increased integration density of the chip provides room for optimization.

2. The vertical TFET does not introduce an additional barrier in the drain region, thereby minimizing the effect of the embedded TFET on the drain-extracting carriers, increasing the read rate of stored data in the half-floating device.

3. The semi-floating gate and the drain region of the semi-floating gate device are only connected by the convex body, and the area of the leakage path is only the physical width of the precisely controllable convex body, and the PN junction interface formed by ion implantation and annealing in the prior art. The built-in barrier in the bump prevents the carrier diffusion between the half floating gate and the drain region in an inactive state. Therefore, the leakage of the stored charge in the half floating gate is greatly reduced, and the stability of the stored information is improved.

4. The horizontal direction channel is adopted between the source region and the drain region of the semi-floating gate device of the present invention (refer to the conventional 100 silicon substrate in the industry), and the data reading speed of the device is not lowered.

5. The semi-floating gate device embedding the vertical TFET of the present invention is completely compatible with the fabrication process of the mature floating gate transistor except for the process of making the convex body; the embedded vertical TFET is used as the convex body of the channel, and the like. The components are multiplexed with the overall semi-floating gate device and have a simple structure. Therefore, the semi-floating gate device embedding the vertical TFET of the present invention has the advantages of simple process and low cost.

6. The floating gate of the semi-floating gate device of the present invention stores information and charges or discharges the floating gate through a vertical TFET, and has higher chip integration density, stronger data retention capability, and data than the existing scheme. The advantage of faster reading.

It can be seen that the technical solutions of the embodiments of the present invention completely solve various defects in the prior art.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments and the prior art description will be briefly described below. Obviously, the drawings in the following description are only some implementations of the present invention. For example, other drawings may be obtained from those skilled in the art without any inventive effort.

1 is a schematic view of a floating gate transistor;

2a is a schematic diagram of a conventional semi-floating gate transistor;

2b is a schematic diagram of another conventional semi-floating gate transistor;

3 is a schematic diagram of a semi-floating gate device according to an embodiment of the present invention;

4 is a flow chart of a method for fabricating a semi-floating gate device according to an embodiment of the present invention;

Figures 5a to 5j are schematic illustrations of various process steps of the process of the invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is an embodiment of the invention, but not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of the present invention.

The detailed description will be respectively made below through specific embodiments.

Referring to FIG. 3, an embodiment of the present invention provides a semi-floating gate device, which may include:

a semiconductor substrate 300 having a first doping type;

a protrusion 301 formed on a surface of the semiconductor substrate 300, the protrusion 301 being a silicon fin or a silicon nanowire (Si Fin or Nanowire) perpendicular to a surface of the semiconductor substrate 300;

a drain region 310 having a second doping type formed on one side of the semiconductor substrate 300, a partial region of the drain region 310 being located below the convex body 301 and with the convex body 301 is connected;

a source region 309 having a second doping type formed on the other side of the semiconductor substrate 300, the source region 309 having a first doping class within the semiconductor substrate 300 a type channel channel 302 is connected to the drain region 310;

Covering the channel region 302 and the first layer of insulating film 303 of the convex body 301 facing the side wall 3011 of the source region;

a floating gate 305 having a first doping type formed on the first insulating film 303 and the convex body 301, and the floating gate 305 is connected to the drain region 310 through the convex body 301;

Covering the source region 309, the floating gate 305 (ie, a semi-floating gate), the drain region 310, and the second insulating film 306 of the protrusion 301;

A control gate 307 is formed on the second insulating film 306 to cover the floating gate 305 and the protrusion 301.

In some embodiments of the present invention, the semi-floating gate device may further include:

Electrodes formed on the drain region 310 and the source region 309 and the control gate 307 respectively include: a drain region electrode 313, a control gate electrode 312, and a source region electrode 311.

And an insulating spacer 308 formed between the drain region and the control gate, between the source region and the control gate, respectively.

Optionally, the first doping type is n-type, and the second doping type is p-type; or the first doping type is p-type, and the second doping type It is n type.

Optionally, the first insulating film is silicon dioxide, silicon nitride or silicon oxynitride, and the second insulating film is silicon dioxide, silicon nitride or silicon oxynitride, and the floating gate is doped Miscellaneous polysilicon, the control gate is metal, alloy or doped polysilicon.

Optionally, the electrode is a metal such as aluminum or copper or an aluminum alloy or a copper alloy; and the spacer is a conventional insulating spacer such as silicon dioxide, silicon nitride or silicon oxynitride.

In the semi-floating gate device of the embodiment of the invention:

The floating gate serves as a charge storage layer; the floating gate, the protrusion, the drain region, the second insulating film, and the control gate form a vertical tunnel with the control gate as a gate a field effect transistor (TFET) that connects the floating gate and the drain region as a channel of the vertical TFET, and the control gate is capable of controlling current flow in the vertical TFET by electric field regulation And the control gate is located above the second insulating film above the channel region, and can control the on and off of current in the channel region of the semi-floating gate device by electric field regulation.

It should be noted that the control gate 307 serves as the gate of the TFET, and the portion of the protrusion 301 outside the sidewall 3012 of the protrusion 301 controls the TFET, and the sidewall 3012 refers to the sidewall of the protrusion 301 facing the drain region 310.

The principle of the technical solution of the embodiment of the present invention is as follows:

In the embodiment of the present invention, the SFGT uses a vertical TFET as a channel for charge injection or release connecting a semi-floating gate (SFG) and a drain region in a semi-floating gate device. The SFGT controls the switching state of the vertical TFET through a control gate (CG) that is covered by a convex sidewall (toward the sidewall of the drain). Taking the N-type SFGT as an example, the source and drain regions of the SFGT are both n-type doped, the polysilicon of the semi-floating gate is p-type doped, and the convex between the two (ie, silicon fins or silicon nanowires) acts as a TFET. The channel is the same as the doping of the semiconductor substrate and is p-type doped. When the control gate applies a negative bias and the drain region applies a positive bias, the surface of the bump and the gate dielectric layer will enter an accumulation state, and a large number of holes will accumulate on the surface, forming a high-concentration electron with the drain region itself. Tunneling PN junction, therefore, the vertical TFET is turned on, electrons tunnel from the convex body to the drain region, and the number of positive charges in the semi-floating gate increases, that is, the logic "1" is written; when the control gate is positively biased and the drain region is reversed When biased, the diode formed by the convex and the drain regions will enter a forward-biased state, and the carriers in the semi-floating gate will be released through the convex body, and the amount of stored charge is reduced, that is, the logic "0" is written.

In order to better implement the above-described aspects of the embodiments of the present invention, a related method for fabricating the above-described semi-floating gate device is also provided below. In the drawings, the thickness of layers and regions are exaggerated for convenience of explanation, and the illustrated sizes do not represent actual dimensions. The drawings are schematic illustrations of idealized embodiments of the present invention, and the illustrated embodiments of the present invention should not be considered limited to the specific shapes of the regions shown in the figures, but rather the resulting shapes, such as manufacturing-induced variations. For example, etched protrusions, semi-floating gates and the like have the characteristics of being curved or rounded, but in the embodiments of the present invention, they are all represented by rectangles, but this should not be considered as limiting the scope of the invention.

Referring to FIG. 3 and FIG. 4 and FIG. 5a to FIG. 5j, an embodiment of the present invention provides a method for fabricating a semi-floating gate device, which may include:

101. As shown in FIG. 5a, a first hard mask layer 201 is deposited on a surface of a semiconductor substrate 300 having a first doping type and a device is defined by a photolithography process and an etching (RIE) process. a position of the protrusion, wherein the protrusion may be a silicon fin or a silicon nanowire, the first type of doping may be n-doped or p-doped, and the first hard mask layer 201 is a certain thickness The dielectric layer may specifically be Si3N4 or the like. The semiconductor substrate 300 may be monocrystalline silicon, polycrystalline silicon, or silicon on insulator.

102, as shown in FIG. 5b, etching the exposed semiconductor substrate 300 by using the first hard mask layer 201 as a mask to form the convex body 301, and the etching depth is greater than that of the first insulating film. thickness.

103, as shown in FIG. 5c, forming the first insulating film 303 on the surface of the formed structure; in a specific application, dry oxidation may be used to grow on the surface of the semiconductor substrate 300 and the sidewall of the protrusion 301. The layer oxide layer, or a dielectric layer material may be deposited by a method such as CVD (Chemical Vapor Deposition) as the first insulating film 303. The first insulating film 303 will be subsequently used as a gate dielectric layer.

104, as shown in FIG. 5d, etching away the remaining first hard mask layer 201; and depositing a first conductive film 305 having a first doping type on the surface of the semiconductor substrate 300, and The formed first conductive film is polished and planarized, and the first planar conductive film 305 having a certain thickness above the convex body is polished and planarized. The first doping type may be n-doped or p-doped, and the first conductive film 305 may specifically be polysilicon, which is subsequently used to form a floating gate (ie, a semi-floating gate). Alternatively, the first type of doping may be performed on the top of the protrusion before the first layer of the conductive film 305 having the first doping type is deposited after the first hard mask layer 201 is removed.

105, as shown in FIG. 5e, depositing a second hard mask layer 202 on the surface of the first conductive film, and defining a floating gate of the device by a photolithography process and an etching process, the second hard mask layer The first conductive film is etched by using the second hard mask layer 202 as a mask to form a floating gate 305, and the etch is stopped on the semiconductor substrate and the first The interface of the layer of insulating film. Optionally, this step may enable the second hard mask layer 202 to cover only a portion of the protrusions 301, further reducing the lateral dimension of the protrusions 301.

106. Etching the remaining second hard mask layer as shown in FIG. 5f; and forming a second insulating film 306 on the surface of the formed structure. In a specific application, an oxide layer such as SiO2 may be formed by dry oxidation, or a dielectric layer material such as SiO2 or Si3N4 or a high-k material may be deposited by CVD or the like as the second insulating film 306.

107. As shown in FIG. 5g, a second conductive film is deposited on the second insulating film 306, and the control gate 307 of the device is formed by the second conductive film by a photolithography process and an etching process. The control gate 307 covers the floating gate 305 and the protrusion 301. The second conductive film 307 may be doped polysilicon, and specifically may be a second type of doped polysilicon.

108. As shown in FIG. 5h, before 109, the method further includes: separately forming spacers 308 on both sides of the control gate 307 to isolate the control gate 307 from the drain electrode and the source region electrode to be formed later. open.

109. As shown in FIG. 5i, ion implantation of a second doping type is performed, and the semiconductor substrate 300 not covered by the control gate 307 is doped to form a source region 309 and a drain region 310 of the device. It should be noted that during the annealing process after ion implantation, the doped impurities will diffuse to some extent along the convex body 301, and form a PN junction with the convex body 301 of the first doping type.

110, as shown in FIG. 5j, opening the drain region 310 and the source region 309 and the electrode window of the control gate 307 by photolithography, depositing metal in the electrode window, and performing lift-off, respectively in the drain region 310 and the source region. An electrode is formed on 309 and control gate 307. The formed electrode specifically includes a drain region electrode 313, a control gate electrode 312, and a source region electrode 311.

It should be noted that the first doping type is n-type, and the second doping type is p-type; or the first doping type is p-type, the second doping Type is n type.

Optionally, in the above process, the sidewall pattern transfer technology in the Fin Field-Effect Transistor (FinFET) can be used to break the limitation of the current lithography precision, and the width of the convex body is made. Further reduction, thereby increasing the integration density of the chip.

The method of the embodiment of the present invention is described above. The semi-floating gate device of the embodiment of FIG. 3 can be obtained by the above preparation method.

In summary, the embodiment of the invention discloses a semi-floating gate device and a preparation method thereof. The technical solution of the embodiment of the invention forms a vertical structure TFET embedded in the interior of the semi-floating gate by a convex body formed on the surface of the semiconductor substrate. Therefore, the following technical effects have been achieved:

1. The embedded vertical TFET occupies a small area of the semiconductor substrate, which is beneficial to the improvement of chip integration density; In the process of manufacturing, the width of the convex body can be further reduced, reducing the requirement of the semiconductor substrate area of the device, and providing an optimization space for the integration density of the device chip.

In the above embodiments, the descriptions of the various embodiments are different, and the parts that are not described in detail in a certain embodiment can be referred to the related description of other embodiments.

It should be noted that, for the foregoing method embodiments, for the sake of brevity, they are all described as a series of action combinations, but those skilled in the art should understand that the present invention is not limited by the described action sequence, because In accordance with the present invention, certain steps may be performed in other sequences or concurrently. In addition, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

The semi-floating gate device and the preparation method thereof provided by the embodiments of the present invention are detailed above. The present invention has been described with reference to specific examples. The description of the embodiments above is only for the purpose of helping to understand the method of the present invention and its core idea; at the same time, for those skilled in the art, based on The present invention is not limited by the scope of the present invention.

Claims

A semi-floating gate device characterized by comprising:

a semiconductor substrate having a first doping type;

a protrusion formed on a surface of the semiconductor substrate, the protrusion being a silicon fin or a silicon nanowire perpendicular to a surface of the semiconductor substrate;

a drain region having a second doping type formed on one side of the semiconductor substrate, a partial region of the drain region being located below the protrusion and in contact with the protrusion;

a source region having a second doping type formed on the other side of the semiconductor substrate, the source region passing through a channel region having a first doping type in the semiconductor substrate and Drainage zone connection

a first insulating film covering the channel region and the sidewall of the protrusion facing the source region;

a floating gate having a first doping type formed on the first insulating film and the convex body, the floating gate being connected to the drain region through the convex body;

Covering the source region, the floating gate, the drain region, and the second insulating film of the protrusion;

a control gate formed on the second insulating film covering the floating gate and the protrusion.
The device of claim 1 further comprising:

Electrodes formed on the drain region and the source region and the control gate, respectively;

And an insulating spacer formed between the drain region and the control gate between the source region and the control gate.
The semi-floating gate device according to claim 1, wherein:

The floating gate serves as a charge storage layer;

The floating gate, the protrusion, the drain region, the second layer of insulating film and the control gate form a vertical tunneling field effect transistor TFET with the control gate as a gate, the convex The body is connected to the floating gate and the drain region as a channel of the vertical TFET, and the control gate is capable of controlling the on and off of current in the vertical TFET by electric field regulation;

Moreover, the control gate is located above the second insulating film above the channel region, and can control the on and off of current in the channel region by electric field regulation.
A semi-floating gate device according to any one of claims 1 to 3, characterized in that:

The first doping type is n-type, and the second doping type is p-type;

Alternatively, the first doping type is p-type and the second doping type is n-type.
A semi-floating gate device according to any one of claims 1 to 3, characterized in that:

The first insulating film is silicon dioxide, silicon nitride or silicon oxynitride, the second insulating film is silicon dioxide, silicon nitride or silicon oxynitride, and the floating gate is doped polysilicon. The control gate is a metal, alloy or doped polysilicon.
The semi-floating gate device according to claim 2, wherein:

The electrode is aluminum or copper or an aluminum alloy or a copper alloy;

The spacer is silicon dioxide, silicon nitride or silicon oxynitride.
A method of fabricating a semi-floating gate device according to claim 1, comprising:

Depositing a first hard mask layer on a surface of a semiconductor substrate having a first doping type and defining a position of a protrusion of the device by a photolithography process and an etching process, the protrusion being a silicon fin or a silicon nanowire;

Etching the exposed semiconductor substrate with the first hard mask layer as a mask to form the protrusion, and the etching depth is greater than the thickness of the first insulating film;

Forming the first insulating film on a surface of the formed structure;

Etching off the remaining first hard mask layer;

Depositing a first conductive film having a first doping type on a surface of the semiconductor substrate;

Depositing a second hard mask layer on the surface of the first conductive film, and defining a floating gate of the device by a photolithography process and an etching process, the second hard mask layer covering the protrusion;

Etching the first conductive film with the second hard mask layer as a mask to form the floating gate, and etching the interface between the semiconductor substrate and the first insulating film;

Etching off the remaining second hard mask layer;

Forming a second insulating film on the surface of the formed structure;

Depositing a second conductive film on the second insulating film, and processing the second conductive film by a photolithography process and an etching process to form a control gate covering the floating gate and the convex body ;

A second doping type of ion implantation is performed to dope the semiconductor substrate not covered by the control gate to form the source and drain regions of the device.
The method according to claim 7, wherein the performing the ion implantation of the second doping type further comprises:

A spacer is separately formed on both sides of the control gate.
The method of claim 7 further comprising:

The drain and source regions and the electrode window of the control gate are opened by photolithography, and metal is deposited in the electrode window to form electrodes on the drain and source regions and the control gate, respectively.
A semi-floating gate device according to any one of claims 7 to 9, wherein:

The first doping type is n-type, and the second doping type is p-type;

Alternatively, the first doping type is p-type and the second doping type is n-type.