WO2015131527A1 - Dispositif à grille semi-flottante et son procédé de préparation - Google Patents

Dispositif à grille semi-flottante et son procédé de préparation Download PDF

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WO2015131527A1
WO2015131527A1 PCT/CN2014/090364 CN2014090364W WO2015131527A1 WO 2015131527 A1 WO2015131527 A1 WO 2015131527A1 CN 2014090364 W CN2014090364 W CN 2014090364W WO 2015131527 A1 WO2015131527 A1 WO 2015131527A1
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floating gate
doping type
semi
semiconductor substrate
insulating film
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PCT/CN2014/090364
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English (en)
Chinese (zh)
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杨喜超
赵静
张臣雄
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a semi-floating gate device and a method for fabricating the same.
  • Nonvolatile Memory NVM
  • FGT Floating Gate Transistor
  • FGT is similar in structure to Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It can be seen as a single-layer gate dielectric layer in a MOSFET. A charge storage layer is embedded in two insulators. The "sandwich" grid of layer) is shown in Figure 1. Among them, the charge storage layer is called a floating gate because it is surrounded by an insulating layer. The amount of stored charge in the floating gate can adjust the magnitude of the transistor threshold voltage, ie, "0" and "1" corresponding to logic. There are two ways to charge the floating gate: tunneling (Fowler-Nordheim) and hot carrier injection. Both of these methods require higher operating voltages and lower carrier injection efficiency, so there are power and speed issues.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • SFGT semi-floating gate transistor
  • TFET Field Effect Field Effect Transistor
  • FIG. 2a A conventional semi-floating gate transistor is shown in Figure 2a.
  • the key change of the semi-floating gate transistor shown in FIG. 2a relative to the floating gate transistor is that the insulating layer 503 between the floating gate 505 and the drain region 510 opens a window 504, thereby doping the region 602, doping region 502, doping
  • the drain region 510 and the control gate 507 and the insulating layer 506 form a planar TFET such that the originally electrically insulated floating gate becomes the semi-floating gate 505.
  • reference numeral 500 denotes a substrate
  • 509 denotes a doped source region
  • 501 is a doped region
  • 508 Insulating spacers
  • 511, 512, and 513 are electrodes.
  • the planar TFET device when the control gate 507 applies a negative bias voltage and the drain region 510 applies a positive bias voltage, the planar TFET device is turned on, and inter-band tunneling occurs, and charges are injected into the doped region 602.
  • the amount of charge in the half floating gate 505 is increased, that is, the logic "1" is written; when the control gate 507 applies a positive bias and the drain region 510 applies a negative bias, the embedded diode (doped region) 602 and PMOS junction 502 form a positive bias, which will cause the stored charge in the half floating gate 505 to be released through the doped region 602, resulting in a decrease in the amount of charge in the half floating gate, ie, writing a logic "0". Due to its unique charge injection/release mechanism, the operating voltage of the device is greatly reduced and the device speed is greatly improved.
  • the embedded TFET is a planar structure and needs to occupy more substrate area; and the size of the window is limited by the lithography precision; therefore, the integration density of the chip will be reduced.
  • the doped region 602 of the embedded planar TFET is opposite to the doping type of the drain region 510 of the SFGT, and an additional barrier is introduced in the drain region, which affects carrier transport of the gate dielectric layer and the semiconductor interface, reducing leakage. The efficiency of the extraction of the carrier, thereby detracting from the read rate of the stored data.
  • the doped region 602 and the doped region 502 form a PN junction.
  • the built-in potential mainly exists in the doped region 502, and the restriction on the carrier in the semi-floating gate region is weak, so that the leakage control of the semi-floating gate is weak. , affecting the stability of data storage.
  • FIG. 2b Another conventional semi-floating gate transistor is shown in Figure 2b.
  • the SFGT shown in Figure 2b reduces the area of the overall SFGT device by employing a vertical channel 401.
  • the source region 201 is placed at the bottom of the trench by shallow trench isolation techniques, and the source region 201 is connected to the drain region 210 by a vertical channel 401.
  • the semi-floating gate 205 and the control gate 207 are both placed inside the trench, saving device footprint.
  • the doped region 402, the doped region 202, and the doped source region 210 constitute a TFET structure, and the half floating gate 205 is connected to the drain region 210 through the sidewall window 204 to charge and discharge the floating gate 205.
  • reference numeral 200 denotes a substrate
  • 203 and 206 denote insulating layers
  • 208 is an insulating spacer
  • 211, 212, 213 are electrodes.
  • the SFGT whose embedded TFET is still a planar structure, still has the above-mentioned second and third defects of the SFGT as shown in Fig. 2a.
  • the SFGT shown in Figure 2b uses a vertical channel, and the carrier mobility in the vertical direction is reduced (refer to the industry's conventional 100 silicon substrate, the vertical direction is 110, the electron mobility is decreased), The data read speed of the device is reduced; and the process of the SFGT shown in FIG. 2b is complicated, for example, the lithography step of the sidewall window 204 presents a very large challenge.
  • Embodiments of the present invention provide a semi-floating gate device and a method of fabricating the same to solve the above various defects of the conventional semi-floating gate transistor.
  • a first aspect of the present invention provides a semi-floating gate device comprising: a semiconductor substrate having a first doping type; a protrusion formed on a surface of the semiconductor substrate, the protrusion being perpendicular to the semiconductor liner a silicon fin or a silicon nanowire of a bottom surface; a drain region having a second doping type formed on one side of the semiconductor substrate, a partial region of the drain region being located under the protrusion and a convex body connected; a source region having a second doping type formed on the other side of the semiconductor substrate, the source region passing through the semiconductor substrate having a first doping type a channel region and the drain region; a first insulating film covering the channel region and a sidewall of the protrusion facing the source region; and the first insulating film and the protrusion a floating gate formed on the first doping type, the floating gate being connected to the drain region through the convex body; covering the source region, the floating gate, the drain region, and the a second insulating film of
  • the semi-floating gate device further includes: electrodes formed on the drain region and the source region and the control gate respectively; and, in the drain region and the Between the control gates, an insulating spacer is formed between the source region and the control gate, respectively.
  • the floating gate serves as a charge storage layer; the floating gate, the convex body, the a drain region, the second insulating film, and the control gate form a vertical tunneling field effect transistor TFET having a gate as the gate, the protrusion serving as a channel connection of the vertical TFET
  • the floating gate and the drain region, the control gate is capable of controlling the on and off of current in the vertical TFET by electric field regulation; and the control gate is located on the second insulating film above the channel region In the above, the on and off of the current in the channel region can be controlled by electric field regulation.
  • the first doping type is n-type
  • the second doping type is p-type; or the first doping type is p-type and the second doping type is n-type.
  • the first insulating film is silicon dioxide, Silicon nitride or silicon oxynitride
  • the second insulating film is silicon dioxide, silicon nitride or silicon oxynitride
  • the floating gate is doped polysilicon
  • the control gate is metal, alloy or doped Polysilicon.
  • the electrode is aluminum or copper or aluminum alloy or copper An alloy;
  • the spacer is silicon dioxide, silicon nitride or silicon oxynitride.
  • a second aspect of the present invention provides a method of fabricating a semi-floating gate device as described above, comprising: depositing a first hard mask layer on a surface of a semiconductor substrate having a first doping type and performing a photolithography process and etching The process defines a position of a convex body of the device, the convex body is a silicon fin or a silicon nanowire; etching the exposed semiconductor substrate by using the first hard mask layer as a mask to form the convex body, engraving The depth of the etch is greater than the thickness of the first insulating film; the first insulating film is formed on the surface of the formed structure; the remaining first hard mask layer is etched; and the surface of the semiconductor substrate is deposited a first conductive film of a doping type; a second hard mask layer is deposited on the surface of the first conductive film, and a floating gate of the device is defined by a photolithography process and an etching process, the second hard Masking layer covering the convex body; etching the
  • the method before performing the ion implantation of the second doping type, the method further comprises: respectively forming spacers on both sides of the control gate.
  • the method further includes: opening the drain and source regions and the electrode window of the control gate by photolithography, depositing metal in the electrode window, and forming electrodes on the drain region and the source region and the control gate, respectively.
  • the first doping type is an n-type
  • the second doping type is p-type; or the first doping type is p-type and the second doping type is n-type.
  • the semi-floating gate device of the embodiment of the present invention forms a vertical structure TFET embedded in the floating gate by a convex body formed on the surface of the semiconductor substrate, and thus has the following technical effects:
  • the embedded vertical TFET occupies a small area of the semiconductor substrate, which is beneficial to the improvement of chip integration density; during the process of manufacturing, the width of the convex body can be further reduced, and the requirement of the semiconductor substrate area of the device is reduced.
  • the increased integration density of the chip provides room for optimization.
  • the vertical TFET does not introduce an additional barrier in the drain region, thereby minimizing the effect of the embedded TFET on the drain-extracting carriers, increasing the read rate of stored data in the half-floating device.
  • the semi-floating gate and the drain region of the semi-floating gate device are only connected by the convex body, and the area of the leakage path is only the physical width of the precisely controllable convex body, and the PN junction interface formed by ion implantation and annealing in the prior art.
  • the built-in barrier in the bump prevents the carrier diffusion between the half floating gate and the drain region in an inactive state. Therefore, the leakage of the stored charge in the half floating gate is greatly reduced, and the stability of the stored information is improved.
  • the horizontal direction channel is adopted between the source region and the drain region of the semi-floating gate device of the present invention (refer to the conventional 100 silicon substrate in the industry), and the data reading speed of the device is not lowered.
  • the semi-floating gate device embedding the vertical TFET of the present invention is completely compatible with the fabrication process of the mature floating gate transistor except for the process of making the convex body; the embedded vertical TFET is used as the convex body of the channel, and the like.
  • the components are multiplexed with the overall semi-floating gate device and have a simple structure. Therefore, the semi-floating gate device embedding the vertical TFET of the present invention has the advantages of simple process and low cost.
  • the floating gate of the semi-floating gate device of the present invention stores information and charges or discharges the floating gate through a vertical TFET, and has higher chip integration density, stronger data retention capability, and data than the existing scheme. The advantage of faster reading.
  • 1 is a schematic view of a floating gate transistor
  • 2a is a schematic diagram of a conventional semi-floating gate transistor
  • 2b is a schematic diagram of another conventional semi-floating gate transistor
  • FIG. 3 is a schematic diagram of a semi-floating gate device according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of a method for fabricating a semi-floating gate device according to an embodiment of the present invention
  • FIGS 5a to 5j are schematic illustrations of various process steps of the process of the invention.
  • Embodiments of the present invention provide a semi-floating gate device and a method of fabricating the same to solve the above various defects of the conventional semi-floating gate transistor.
  • an embodiment of the present invention provides a semi-floating gate device, which may include:
  • drain region 310 having a second doping type formed on one side of the semiconductor substrate 300, a partial region of the drain region 310 being located below the convex body 301 and with the convex body 301 is connected;
  • a control gate 307 is formed on the second insulating film 306 to cover the floating gate 305 and the protrusion 301.
  • the semi-floating gate device may further include:
  • Electrodes formed on the drain region 310 and the source region 309 and the control gate 307 respectively include: a drain region electrode 313, a control gate electrode 312, and a source region electrode 311.
  • an insulating spacer 308 formed between the drain region and the control gate, between the source region and the control gate, respectively.
  • the first doping type is n-type, and the second doping type is p-type; or the first doping type is p-type, and the second doping type It is n type.
  • the first insulating film is silicon dioxide, silicon nitride or silicon oxynitride
  • the second insulating film is silicon dioxide, silicon nitride or silicon oxynitride
  • the floating gate is doped Miscellaneous polysilicon
  • the control gate is metal, alloy or doped polysilicon.
  • the electrode is a metal such as aluminum or copper or an aluminum alloy or a copper alloy; and the spacer is a conventional insulating spacer such as silicon dioxide, silicon nitride or silicon oxynitride.
  • the floating gate serves as a charge storage layer; the floating gate, the protrusion, the drain region, the second insulating film, and the control gate form a vertical tunnel with the control gate as a gate a field effect transistor (TFET) that connects the floating gate and the drain region as a channel of the vertical TFET, and the control gate is capable of controlling current flow in the vertical TFET by electric field regulation And the control gate is located above the second insulating film above the channel region, and can control the on and off of current in the channel region of the semi-floating gate device by electric field regulation.
  • TFET field effect transistor
  • control gate 307 serves as the gate of the TFET, and the portion of the protrusion 301 outside the sidewall 3012 of the protrusion 301 controls the TFET, and the sidewall 3012 refers to the sidewall of the protrusion 301 facing the drain region 310.
  • the SFGT uses a vertical TFET as a channel for charge injection or release connecting a semi-floating gate (SFG) and a drain region in a semi-floating gate device.
  • the SFGT controls the switching state of the vertical TFET through a control gate (CG) that is covered by a convex sidewall (toward the sidewall of the drain).
  • CG control gate
  • the source and drain regions of the SFGT are both n-type doped
  • the polysilicon of the semi-floating gate is p-type doped
  • the convex between the two ie, silicon fins or silicon nanowires
  • the channel is the same as the doping of the semiconductor substrate and is p-type doped.
  • the control gate applies a negative bias and the drain region applies a positive bias, the surface of the bump and the gate dielectric layer will enter an accumulation state, and a large number of holes will accumulate on the surface, forming a high-concentration electron with the drain region itself.
  • Tunneling PN junction therefore, the vertical TFET is turned on, electrons tunnel from the convex body to the drain region, and the number of positive charges in the semi-floating gate increases, that is, the logic "1" is written; when the control gate is positively biased and the drain region is reversed When biased, the diode formed by the convex and the drain regions will enter a forward-biased state, and the carriers in the semi-floating gate will be released through the convex body, and the amount of stored charge is reduced, that is, the logic "0" is written.
  • an embodiment of the present invention provides a method for fabricating a semi-floating gate device, which may include:
  • a first hard mask layer 201 is deposited on a surface of a semiconductor substrate 300 having a first doping type and a device is defined by a photolithography process and an etching (RIE) process.
  • RIE etching
  • the dielectric layer may specifically be Si3N4 or the like.
  • the semiconductor substrate 300 may be monocrystalline silicon, polycrystalline silicon, or silicon on insulator.
  • the first insulating film 303 on the surface of the formed structure; in a specific application, dry oxidation may be used to grow on the surface of the semiconductor substrate 300 and the sidewall of the protrusion 301.
  • the layer oxide layer, or a dielectric layer material may be deposited by a method such as CVD (Chemical Vapor Deposition) as the first insulating film 303.
  • CVD Chemical Vapor Deposition
  • the first insulating film 303 will be subsequently used as a gate dielectric layer.
  • first conductive film 305 having a first doping type etching away the remaining first hard mask layer 201; and depositing a first conductive film 305 having a first doping type on the surface of the semiconductor substrate 300, and The formed first conductive film is polished and planarized, and the first planar conductive film 305 having a certain thickness above the convex body is polished and planarized.
  • the first doping type may be n-doped or p-doped, and the first conductive film 305 may specifically be polysilicon, which is subsequently used to form a floating gate (ie, a semi-floating gate).
  • the first type of doping may be performed on the top of the protrusion before the first layer of the conductive film 305 having the first doping type is deposited after the first hard mask layer 201 is removed.
  • this step may enable the second hard mask layer 202 to cover only a portion of the protrusions 301, further reducing the lateral dimension of the protrusions 301.
  • an oxide layer such as SiO2 may be formed by dry oxidation, or a dielectric layer material such as SiO2 or Si3N4 or a high-k material may be deposited by CVD or the like as the second insulating film 306.
  • a second conductive film is deposited on the second insulating film 306, and the control gate 307 of the device is formed by the second conductive film by a photolithography process and an etching process.
  • the control gate 307 covers the floating gate 305 and the protrusion 301.
  • the second conductive film 307 may be doped polysilicon, and specifically may be a second type of doped polysilicon.
  • the method further includes: separately forming spacers 308 on both sides of the control gate 307 to isolate the control gate 307 from the drain electrode and the source region electrode to be formed later. open.
  • ion implantation of a second doping type is performed, and the semiconductor substrate 300 not covered by the control gate 307 is doped to form a source region 309 and a drain region 310 of the device. It should be noted that during the annealing process after ion implantation, the doped impurities will diffuse to some extent along the convex body 301, and form a PN junction with the convex body 301 of the first doping type.
  • the formed electrode specifically includes a drain region electrode 313, a control gate electrode 312, and a source region electrode 311.
  • the first doping type is n-type
  • the second doping type is p-type
  • the first doping type is p-type
  • the second doping Type is n type.
  • the first insulating film is silicon dioxide, silicon nitride or silicon oxynitride
  • the second insulating film is silicon dioxide, silicon nitride or silicon oxynitride
  • the floating gate is doped Miscellaneous polysilicon
  • the control gate is metal, alloy or doped polysilicon.
  • the electrode is a metal such as aluminum or copper or an aluminum alloy or a copper alloy; and the spacer is a conventional insulating spacer such as silicon dioxide, silicon nitride or silicon oxynitride.
  • the sidewall pattern transfer technology in the Fin Field-Effect Transistor can be used to break the limitation of the current lithography precision, and the width of the convex body is made. Further reduction, thereby increasing the integration density of the chip.
  • the method of the embodiment of the present invention is described above.
  • the semi-floating gate device of the embodiment of FIG. 3 can be obtained by the above preparation method.
  • the embodiment of the invention discloses a semi-floating gate device and a preparation method thereof.
  • the technical solution of the embodiment of the invention forms a vertical structure TFET embedded in the interior of the semi-floating gate by a convex body formed on the surface of the semiconductor substrate. Therefore, the following technical effects have been achieved:
  • the embedded vertical TFET occupies a small area of the semiconductor substrate, which is beneficial to the improvement of chip integration density; In the process of manufacturing, the width of the convex body can be further reduced, reducing the requirement of the semiconductor substrate area of the device, and providing an optimization space for the integration density of the device chip.
  • the vertical TFET does not introduce an additional barrier in the drain region, thereby minimizing the effect of the embedded TFET on the drain-extracting carriers, increasing the read rate of stored data in the half-floating device.
  • the semi-floating gate and the drain region of the semi-floating gate device are only connected by the convex body, and the area of the leakage path is only the physical width of the precisely controllable convex body, and the PN junction interface formed by ion implantation and annealing in the prior art.
  • the built-in barrier in the bump prevents the carrier diffusion between the half floating gate and the drain region in an inactive state. Therefore, the leakage of the stored charge in the half floating gate is greatly reduced, and the stability of the stored information is improved.
  • the horizontal direction channel is adopted between the source region and the drain region of the semi-floating gate device of the present invention (refer to the conventional 100 silicon substrate in the industry), and the data reading speed of the device is not lowered.
  • the semi-floating gate device embedding the vertical TFET of the present invention is completely compatible with the fabrication process of the mature floating gate transistor except for the process of making the convex body; the embedded vertical TFET is used as the convex body of the channel, and the like.
  • the components are multiplexed with the overall semi-floating gate device and have a simple structure. Therefore, the semi-floating gate device embedding the vertical TFET of the present invention has the advantages of simple process and low cost.
  • the floating gate of the semi-floating gate device of the present invention stores information and charges or discharges the floating gate through a vertical TFET, and has higher chip integration density, stronger data retention capability, and data than the existing scheme. The advantage of faster reading.

Abstract

La présente invention concerne un dispositif à grille semi-flottante et son procédé de préparation, qui sont utilisés pour résoudre une pluralité de défauts présentés par le transistor à grille semi-flottante existant. Le dispositif à grille semi-flottante comprend : un substrat semi-conducteur (300) présentant un premier type de dopage ; un corps convexe (301) formé sur la surface du substrat semi-conducteur (300) ; une région déversoir (310) qui est formée au niveau d'un côté du substrat semi-conducteur (300) et qui présente un second type de dopage, la région déversoir étant raccordée au corps convexe ; une région source (309) qui est formée au niveau de l'autre côté du substrat semi-conducteur et qui présente un second type de dopage, la région source étant raccordée à la région déversoir par l'intermédiaire d'une région canal (302) ; une première couche d'un film mince d'isolation (303) qui recouvre la région canal et une paroi latérale du corps convexe faisant face à la région source ; une grille flottante (305) qui est formée sur la première couche d'un film mince d'isolation et sur le corps convexe et qui présente un premier type de dopage, la grille flottante étant raccordée à la région déversoir par l'intermédiaire du corps convexe ; une seconde couche d'un film mince d'isolation (306) ; et une grille de commande (307) qui est formée sur la seconde couche d'un film mince d'isolation et qui recouvre la grille flottante et le corps convexe.
PCT/CN2014/090364 2014-03-04 2014-11-05 Dispositif à grille semi-flottante et son procédé de préparation WO2015131527A1 (fr)

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CN201410077052.9A CN103887313B (zh) 2014-03-04 2014-03-04 一种半浮栅器件及其制备方法
CN201410077052.9 2014-03-04

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9799776B2 (en) * 2015-06-15 2017-10-24 Stmicroelectronics, Inc. Semi-floating gate FET
CN112838089A (zh) * 2021-03-25 2021-05-25 复旦大学 半浮栅存储器及其制造方法
CN112909000A (zh) * 2021-03-25 2021-06-04 复旦大学 半浮栅存储器及其制造工艺
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887313B (zh) * 2014-03-04 2016-08-31 华为技术有限公司 一种半浮栅器件及其制备方法
CN108028271B (zh) * 2016-08-17 2020-08-14 华为技术有限公司 存储装置及其制作方法、数据读写方法
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CN112864221B (zh) * 2019-11-27 2022-04-15 苏州东微半导体股份有限公司 半导体超结功率器件
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376711A (zh) * 2010-08-16 2012-03-14 苏州东微半导体有限公司 半导体存储器器件及其制造方法
CN103247626A (zh) * 2013-05-02 2013-08-14 复旦大学 一种半浮栅器件及其制造方法
CN103887313A (zh) * 2014-03-04 2014-06-25 华为技术有限公司 一种半浮栅器件及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6897518B1 (en) * 2003-07-10 2005-05-24 Advanced Micro Devices, Inc. Flash memory cell having reduced leakage current
US7005700B2 (en) * 2004-01-06 2006-02-28 Jong Ho Lee Double-gate flash memory device
US7847338B2 (en) * 2007-10-24 2010-12-07 Yuniarto Widjaja Semiconductor memory having both volatile and non-volatile functionality and method of operating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376711A (zh) * 2010-08-16 2012-03-14 苏州东微半导体有限公司 半导体存储器器件及其制造方法
CN103247626A (zh) * 2013-05-02 2013-08-14 复旦大学 一种半浮栅器件及其制造方法
CN103887313A (zh) * 2014-03-04 2014-06-25 华为技术有限公司 一种半浮栅器件及其制备方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9799776B2 (en) * 2015-06-15 2017-10-24 Stmicroelectronics, Inc. Semi-floating gate FET
US10741698B2 (en) 2015-06-15 2020-08-11 Stmicroelectronics, Inc. Semi-floating gate FET
CN112838089A (zh) * 2021-03-25 2021-05-25 复旦大学 半浮栅存储器及其制造方法
CN112909000A (zh) * 2021-03-25 2021-06-04 复旦大学 半浮栅存储器及其制造工艺
CN112838089B (zh) * 2021-03-25 2022-10-21 复旦大学 半浮栅存储器及其制造方法
CN113506826A (zh) * 2021-06-17 2021-10-15 重庆伟特森电子科技有限公司 一种沟槽型碳化硅晶体管及其制备方法
CN113506826B (zh) * 2021-06-17 2023-07-07 重庆伟特森电子科技有限公司 一种沟槽型碳化硅晶体管及其制备方法
CN113823566A (zh) * 2021-09-23 2021-12-21 武汉新芯集成电路制造有限公司 存储器件的制作方法
CN113823566B (zh) * 2021-09-23 2023-12-01 武汉新芯集成电路制造有限公司 存储器件的制作方法
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CN113990890B (zh) * 2021-10-25 2024-04-09 南京大学 基于复合介质栅pn结的全局快门光敏探测器及工作方法

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