CN112864221B - 半导体超结功率器件 - Google Patents

半导体超结功率器件 Download PDF

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CN112864221B
CN112864221B CN201911184048.1A CN201911184048A CN112864221B CN 112864221 B CN112864221 B CN 112864221B CN 201911184048 A CN201911184048 A CN 201911184048A CN 112864221 B CN112864221 B CN 112864221B
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CN112864221A (zh
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龚轶
刘伟
袁愿林
刘磊
王睿
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Suzhou Dongwei Semiconductor Co ltd
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Abstract

本发明实施例提供的一种半导体超结功率器件，包括由多个超结MOSFET单元组成的超结MOSFET单元阵列，该超结MOSFET单元包括位于n型漂移区顶部的p型体区，位于p型体区下方的p型柱状掺杂区，位于p型体区内的n型源区，位于p型体区之上栅介质层，位于栅介质层之上的栅极和n型浮栅，且在横向上，栅极位于靠近n型源区的一侧，n型浮栅位于靠近n型漂移区的一侧，栅极通过电容耦合作用于n型浮栅；位于栅介质层中的一个开口，n型浮栅通过所述开口与p型体区接触形成p‑n结二极管。本发明实施例提高了半导体超结功率器件的反向恢复速度。

Description

半导体超结功率器件
技术领域
本发明属于半导体超结功率器件技术领域，特别是涉及一种反向恢复速度快的半导体超结功率器件。
背景技术
现有技术的半导体超结功率器件的等效电路如图1所示，包括源极101、漏极102、栅极103和体二极管104，其中，体二极管104是半导体超结功率器件中的本征寄生结构。现有技术的半导体超结功率器件的工作机理是：1)当栅源电压Vgs小于半导体超结功率器件的阈值电压Vth，漏源电压Vds大于0V时，半导体超结功率器件处于关断状态；2)当栅源电压Vgs大于半导体超结功率器件的阈值电压Vth，漏源电压Vds大于0V时，半导体超结功率器件正向开启，此时电流从漏极经栅极处的电流沟道流到源极。现有技术的半导体超结功率器件在关断时，当漏源电压Vds小于0V时，半导体超结功率器件的体二极管处于正偏压状态，反向电流从源极经体二极管流至漏极，此时体二极管的电流存在注入少子载流子现象，而这些少子载流子在半导体超结功率器件再一次开启时进行反向恢复，导致较大的反向恢复电流，反向恢复时间长。
发明内容
有鉴于此，本发明的目的是提供一种反向恢复速度快的半导体超结功率器件，以解决现有技术中的半导体超结功率器件因少子载流子注入问题造成的反向恢复时间长的技术问题。
本发明实施例提供的一种半导体超结功率器件，包括：
n型漏区，位于所述n型漏区之上的n型漂移区，以及由多个超结MOSFET单元组成的超结MOSFET单元阵列，所述超结MOSFET单元包括：
p型体区，所述p型体区位于所述n型漂移区顶部；
位于所述p型体区下方的p型柱状掺杂区；
位于所述p型体区内的n型源区；
位于所述p型体区之上的栅极结构，所述栅极结构包括栅介质层、栅极和n型浮栅，所述栅极和所述n型浮栅位于所述栅介质层之上，且在横向上，所述栅极位于靠近所述n型源区的一侧，所述n型浮栅位于靠近所述n型漂移区的一侧，所述栅极通过电容耦合作用于所述n型浮栅；
位于所述栅介质层中的一个开口，所述n型浮栅通过所述开口与所述p型体区接触形成p-n结二极管。
可选的，本发明的半导体超结功率器件，所述栅极延伸至所述n型浮栅之上。
可选的，本发明的半导体超结功率器件，所述栅极延伸至所述n型浮栅之上且覆盖所述n型浮栅靠近所述n型漂移区一侧的侧壁。
可选的，本发明的半导体超结功率器件，所述开口位于所述n型浮栅下方且靠近所述n型漂移区的一侧。
可选的，本发明的半导体超结功率器件，在超结MOSFET单元阵列中，至少有一个所述超结MOSFET单元的栅极与所述n型源区电性连接。
本发明实施例提供的一种半导体超结功率器件，在正向阻断状态和正向开启时具有高阈值电压；在反向导通时超结MOSFET单元具有低阈值电压，使得超结MOSFET单元在低栅极电压(或0V电压)下导通，从而能够增加流过超结MOSFET单元的反向电流，减少流过半导体超结功率器件中寄生的体二极管的电流，提高半导体超结功率器件的反向恢复速度。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是现有技术的半导体超结功率器件的等效电路示意图；
图2是本发明提供的一种半导体超结功率器件的第一个实施例的剖面结构示意图；
图3是本发明提供的一种半导体超结功率器件的第二个实施例的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体实施方式，完整地描述本发明的技术方案。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的尺寸，且所列图形大小并不代表实际尺寸。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图2是本发明提供的一种半导体超结功率器件的第一个实施例的剖面结构示意图，如图2所示，本发明实施例提供的一种半导体超结功率器件包括n型漏区20，位于n型漏区20之上的n型漂移区21，以及由多个超结MOSFET单元200组成的超结MOSFET单元阵列，在图2中仅示例性的示出了一个超结MOSFET单元200。
本发明实施例的超结MOSFET单元200包括p型体区22，p型体区22位于n型漂移区21顶部；位于p型体区22下方的p型柱状掺杂区29，p型柱状掺杂区29与相邻的n型漂移区21之间形成电荷平衡，用以提高半导体超结功率器件的耐压；位于p型体区22内的n型源区23；位于p型体区22之上的栅极结构，该栅极结构包括栅介质层24、n型浮栅25和栅极26，栅极26和n型浮栅25位于栅介质层24之上，且在横向上，栅极26位于靠近n型源区23的一侧，n型浮栅25位于靠近n型漂移区21的一侧，栅极26和n型浮栅25由绝缘介质层27隔离，栅极26通过电容耦合作用于n型浮栅25。绝缘介质层27通常为二氧化硅。
本发明实施例的半导体超结功率器件，在横向上，n型浮栅25位于栅介质层24之上且靠近n型漂移区21的一侧，即n型浮栅25靠近n型漂移区21设置，而栅极26可以是位于栅介质层24之上且靠近n型源区23的一侧，即栅极26仅位于n型浮栅25靠近n型源区23的一侧(该结构在本发明实施例中未具体展示)；栅极26也可以是一部分位于n型浮栅25靠近n型源区23的一侧，而另一部分延伸至n型浮栅25之上(如图2所示)。栅极26向n型漂移区21一侧延伸至n型浮栅25之上可以增大栅极26覆盖n型浮栅25的面积，进而能够增大栅极26对n型浮栅26的电容耦合率。
在栅介质层24中形成有一个开口28，n型浮栅25通过栅介质层24中的开口28与p型体区22接触形成p-n结二极管。
本发明实施例的半导体超结功率器件，在正向阻断状态时，n型漏区20被施加高电压，由n型浮栅25与p型体区22接触形成的p-n结二极管被正向偏置，n型浮栅25被充入正电荷，这使得n型浮栅25下面的电流沟道的阈值电压Vht1降低。可选的，开口28位于n型浮栅25下方且靠近n型漂移区21的一侧，即在横向上，开口28的中心到栅介质层24的靠近n型漂移区21的一侧端的距离小于开口28的中心到栅介质层24的靠近n型源区23的一侧端的距离，由此将开口28在栅介质层24中更靠近n型漂移区21设置，这可以使n型浮栅25更容易被充入正电荷，从而可以提高n型浮栅25的电压，降低n型浮栅25下面的电流沟道的阈值电压Vht1。
本发明实施例的半导体超结功率器件在正向阻断状态和正向开启状态时，漏源电压Vds大于0V，n型浮栅25下面的电流沟道的阈值电压Vht1对整个超结MOSFET单元的阈值电压Vth的影响很低，半导体超结功率器件仍具有高阈值电压。本发明实施例的半导体超结功率器件在关断时，当源漏电压Vsd大于0V时，n型浮栅25下面的电流沟道的阈值电压Vht1对整个超结MOSFET单元的阈值电压Vth的影响很大，使得超结MOSFET单元具有低阈值电压Vth，从而使超结MOSFET单元的电流沟道在低栅极电压(或0V电压)下导通，从而能够增加流过超结MOSFET单元的电流，减少流过半导体超结功率器件中寄生的体二极管的电流，提高半导体超结功率器件的反向恢复速度。
本发明实施例的半导体超结功率器件的超结MOSFET单元阵列中，可以使得至少一个超结MOSFET单元200的栅极26与n型源区23电性连接，即该部分栅极26接源极电压，这可以降低半导体超结功率器件的栅电荷。
图3是本发明提供的一种半导体超结功率器件的第二个实施例的剖面结构示意图，如图3所示，该实施例与图2所示的本发明的第一个实施例的半导体超结功率器件结构不同的是，本实施例中的栅极26向n型漂移区21的一侧延伸至n型浮栅25之上且覆盖n型浮栅25靠近n型漂移区21一侧的侧壁，这能够进一步增大栅极26覆盖n型浮栅25的面积，进而能够进一步增大栅极26对n型浮栅26的电容耦合率。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (5)

1.一种半导体超结功率器件，其特征在于，包括：
n型漏区，位于所述n型漏区之上的n型漂移区，以及由多个超结MOSFET单元组成的超结MOSFET单元阵列，所述超结MOSFET单元包括：
p型体区，所述p型体区位于所述n型漂移区顶部；
位于所述p型体区下方的p型柱状掺杂区；
位于所述p型体区内的n型源区；
位于所述p型体区之上的栅极结构，所述栅极结构包括栅介质层、栅极和n型浮栅，所述栅极和所述n型浮栅位于所述栅介质层之上，且在横向上，所述栅极位于靠近所述n型源区的一侧，所述n型浮栅位于靠近所述n型漂移区的一侧，所述栅极通过电容耦合作用于所述n型浮栅；
位于所述栅介质层中的一个开口，所述n型浮栅通过所述开口与所述p型体区接触形成p-n结二极管。
2.如权利要求1所述的半导体超结功率器件，其特征在于，所述栅极延伸至所述n型浮栅之上。
3.如权利要求1所述的半导体超结功率器件，其特征在于，所述栅极延伸至所述n型浮栅之上且覆盖所述n型浮栅靠近所述n型漂移区一侧的侧壁。
4.如权利要求1所述的半导体超结功率器件，其特征在于，所述开口位于所述n型浮栅下方且靠近所述n型漂移区的一侧。
5.如权利要求1所述的半导体超结功率器件，其特征在于，在所述超结MOSFET单元阵列中，至少有一个所述超结MOSFET单元的栅极与所述n型源区电性连接。
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Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1074959A (ja) * 1996-07-03 1998-03-17 Toshiba Corp 電力用半導体素子
US6882573B2 (en) * 2002-08-13 2005-04-19 General Semiconductor, Inc. DMOS device with a programmable threshold voltage
DE102005039564B4 (de) * 2004-09-02 2011-03-31 Fuji Electric Systems Co., Ltd. Verfahren zum Herstellen eines Halbleiterbauteils
JP4825424B2 (ja) * 2005-01-18 2011-11-30 株式会社東芝 電力用半導体装置
US7378317B2 (en) * 2005-12-14 2008-05-27 Freescale Semiconductor, Inc. Superjunction power MOSFET
JP5050364B2 (ja) * 2006-02-13 2012-10-17 サンケン電気株式会社 電界効果半導体装置及びその製造方法
JP2009099911A (ja) * 2007-10-19 2009-05-07 Toshiba Corp 半導体装置
CN102270663B (zh) * 2011-07-26 2013-01-23 无锡新洁能功率半导体有限公司 具有超结结构的平面型功率mosfet器件及其制造方法
CN103367157B (zh) * 2012-04-06 2015-12-09 北大方正集团有限公司 一种超结mosfet的制备方法
CN104465381B (zh) * 2013-09-23 2017-12-01 苏州东微半导体有限公司 一种平面沟道的半浮栅器件的制造方法
CN103247626A (zh) * 2013-05-02 2013-08-14 复旦大学 一种半浮栅器件及其制造方法
CN203659877U (zh) * 2013-10-30 2014-06-18 英飞凌科技奥地利有限公司 超结器件和包括所述超结器件的半导体结构
CN103887313B (zh) * 2014-03-04 2016-08-31 华为技术有限公司 一种半浮栅器件及其制备方法
US10388650B2 (en) * 2014-08-17 2019-08-20 Fudan University Semi-floating-gate power device and manufacturing method therefor
CN104882447B (zh) * 2015-05-27 2018-10-16 上海集成电路研发中心有限公司 一种漏区嵌入反型层的半浮栅器件及制造方法
KR102117467B1 (ko) * 2015-06-22 2020-06-01 삼성전기주식회사 전력 반도체 소자
US10573722B2 (en) * 2016-02-17 2020-02-25 General Electric Company Systems and methods for in-situ doped semiconductor gate electrodes for wide bandgap semiconductor power devices
CN106098761B (zh) * 2016-06-29 2019-06-07 黄嘉杰 一种绝缘栅双极型晶体管结构及其制造方法
CN106229343B (zh) * 2016-08-12 2019-05-03 上海鼎阳通半导体科技有限公司 超结器件
JP6461063B2 (ja) * 2016-09-28 2019-01-30 トヨタ自動車株式会社 半導体装置とその製造方法
JP7055725B2 (ja) * 2018-09-14 2022-04-18 株式会社東芝 半導体装置
CN110212026B (zh) * 2019-05-06 2022-09-16 上海功成半导体科技有限公司 超结mos器件结构及其制备方法

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