CN103247626A - 一种半浮栅器件及其制造方法 - Google Patents

一种半浮栅器件及其制造方法 Download PDF

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CN103247626A
CN103247626A CN2013101589714A CN201310158971A CN103247626A CN 103247626 A CN103247626 A CN 103247626A CN 2013101589714 A CN2013101589714 A CN 2013101589714A CN 201310158971 A CN201310158971 A CN 201310158971A CN 103247626 A CN103247626 A CN 103247626A
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gate
floating boom
insulation film
doping type
region
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王鹏飞
张卫
孙清清
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Fudan University
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Fudan University
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Priority to CN2013101589714A priority Critical patent/CN103247626A/zh
Publication of CN103247626A publication Critical patent/CN103247626A/zh
Priority to EP14791834.6A priority patent/EP2993695A4/en
Priority to US14/651,997 priority patent/US9508811B2/en
Priority to PCT/CN2014/076438 priority patent/WO2014177045A1/zh
Priority to US15/342,328 priority patent/US9748406B2/en
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

Abstract

本发明属于半导体存储器技术领域，具体涉及一种半浮栅器件，包括至少一个半导体衬底、一个源区、一个漏区、一个浮栅、一个控制栅、一个垂直沟道区以及一个用于连接所述浮栅与所述漏区的栅控p-n结二极管。本发明所提出的半浮栅器件用浮栅存储信息，并通过所述栅控p-n结二极管对浮栅进行充电或放电，具有单元面积小、芯片密度高、对数据进行存储时操作电压低、数据保持能力强等优点。

Description

一种半浮栅器件及其制造方法
技术领域
本发明属于半导体存储器技术领域，具体涉及一种半浮栅器件及其制造方法，特别涉及一种带垂直沟道区的半浮栅器件及其制造方法。
背景技术
半导体存储器被广泛应用于各种电子产品之中。不同应用领域对半导体存储器的构造、性能和密度有着不同的要求。比如，静态随机存储器（SRAM）拥有很高的随机存取速度和较低的集成密度，而标准的动态随机存储器（DRAM）则具有很高的密度和中等的随机存取速度。
图1为现有技术的的一种平面沟道的半导体存储器，包括：在半导体衬底500内形成的具有与半导体衬底相反掺杂类型的源区501和漏区502，半导体衬底500可以为单晶硅、多晶硅或者为绝缘体上的硅。在半导体衬底500内、介于源区501和漏区502之间形成有器件的平面沟道区601，平面沟道区601是该半导体存储器在进行工作时在半导体衬底500内形成的反型层。在源区501和漏区502内还分别形成有高掺杂浓度的掺杂区509和掺杂区510，掺杂区509和掺杂区510与源区501和漏区502具有相同的掺杂类型。
在源区501、沟道区601和漏区502之上形成有第一层绝缘薄膜503，且在漏区502之上的第一层绝缘薄膜503中形成有一个浮栅开口区域504。在第一层绝缘薄膜503之上、覆盖整个平面沟道区601和浮栅开口区域504形成有一个作为电荷存储节点的浮栅505，浮栅505具有与漏区502相反的掺杂类型，且浮栅505中的掺杂杂质会通过浮栅开口区域504扩散至漏区502中形成扩散区602，从而通过浮栅开口区域504在浮栅505与漏区502之间形成一个p-n结二极管。
覆盖浮栅205和所述的p-n结二极管结构形成有第二层绝缘薄膜506。在第二层绝缘薄膜506之上、覆盖并包围浮栅505形成有器件的控制栅507。在控制栅507的两侧还形成有栅极侧墙508。该半导体存储器还包括由导电材料形成的用于将源区501、控制栅507、漏区502、半导体衬底500与外部电极相连接的源区的接触体511、控制栅的接触体512、漏区的接触体513和半导体衬底的接触体514。
为保证半导体存储器的性能，平面沟道的半导体存储器需要较长的沟道长度，这使得半导体存储器的单元面积较大，从而降低了芯片密度，不利于芯片向微型化的方向发展。
发明内容
本发明的目的在于提出一种带垂直沟道区的半浮栅器件，从而可以降低半导体存储器的单元面积，提高芯片密度。
本发明提供的一种带垂直沟道区的半浮栅器件，由于其浮栅和漏区之间通过p-n结二极管相连，使浮栅呈“半浮”状态。所述半浮栅器件具体包括：
一个具有第一种掺杂类型的半导体衬底；
在所述半导体衬底内形成的垂直沟道区；
所述垂直沟道区的底部与具有第二种掺杂类型的源区连接，所述垂直沟道区的顶部与具有第二种种掺杂类型的漏区连接；
覆盖所述源区、漏区与垂直沟道区形成的第一层绝缘薄膜；
在半导体衬底水平表面上且覆盖所述漏区的第一层绝缘薄膜中，形成的一个浮栅开口区域；
覆盖所述第一层绝缘薄膜和浮栅开口区域,形成一个具有第一种掺杂类型的浮栅；该浮栅作为电荷存储节点，位于垂直沟道区和浮栅开口区之上，一方面通过所述浮栅开口区，在所述浮栅与漏区之间形成一个p-n结二极管；另一方面因为覆盖在垂直沟道区的第一层绝缘薄膜上，可以通过电场调控来控制沟道区内电流的通与断； 
覆盖所述源区、浮栅与p-n结二极管形成的第二层绝缘薄膜；
在所述第二层绝缘薄膜之上，且覆盖所述浮栅与栅控p-n结二极管形成的控制栅。
本发明中，所述的第一种掺杂类型为n型，所述的第二种掺杂类型为p型；或者，所述的第一种掺杂类型为p型，所述的第二种掺杂类型为n型。
本发明中，所述的第一层绝缘薄膜、第二层绝缘薄膜由二氧化硅、氮化硅、氮氧化硅或者高介电常数的绝缘材料形成，所述的浮栅由掺杂的多晶硅形成，所述的控制栅由金属、合金或者掺杂的多晶硅形成。
本发明中，所述的p-n结二极管、第二层绝缘薄膜和控制栅构成了一个以所述控制栅作为栅极的栅控二极管，所述栅控二极管的阳极与所述浮栅相连接，所述栅控二极管的阴极与所述漏区相连接；或者，所述栅控二极管的阴极与所述浮栅相连接，所述栅控二极管的阳极与所述漏区相连接。
本发明提出了所述半浮栅器件的制备方法，具体步骤如下：
在具有第一掺杂类型的半导体衬底内形成具有第二种掺杂类型的轻掺杂区；
在所述半导体衬底表面淀积一硬掩膜层并通过光刻工艺和刻蚀工艺定义出器件的垂直沟道区的位置；
以所述硬掩膜层为掩膜刻蚀暴露出的半导体衬底，形成器件的垂直沟道区区域，刻蚀的深度需深于所形成的具有第二种掺杂类型的轻掺杂区的深度，此时具有第二种掺杂类型的轻掺杂区会被刻蚀掉一部分，剩余的具有第二种掺杂类型的轻掺杂区形成器件的漏区；
刻蚀掉剩余的硬掩膜层；
在半导体衬底的暴露表面上生长第一层绝缘薄膜并刻蚀所形成的第一层绝缘薄膜形成浮栅开口区域，所形成的浮栅开口区域在垂直沟道区顶部的将漏区暴露出来；
接着，在所形成结构的暴露表面上淀积具有第一种掺杂类型的第一层导电薄膜，并对所形成的第一层导电薄膜进行回刻以形成器件的浮栅，其中，浮栅至少覆盖所形成的垂直沟道区和浮栅开口区域；
接着，在已形成结构的暴露表面上生长第二层绝缘薄膜；
在所述第二层绝缘薄膜之上淀积形成第二层导电薄膜，然后通过光刻工艺和刻蚀工艺刻蚀所形成的第二层导电薄膜以形成器件的控制栅；
进行第二种掺杂类型的离子注入，对控制栅和未被控制栅覆盖的半导体衬底进行掺杂以形成器件的源区以及漏区和控制栅的掺杂结构。
如上所述的半浮栅器件的制备方法，所述的第一种掺杂类型为n型，所述的第二种掺杂类型为p型；或者，所述的第一种掺杂类型为p型，所述的第二种掺杂类型为n型。
如上所述的半浮栅器件的制备方法，所述的第一层绝缘薄膜和第二层绝缘薄膜为二氧化硅、氮化硅、氮氧化硅或者为高介电常数的绝缘材料，所述的第一层导电薄膜为掺杂的多晶硅，所述的第二层导电薄膜为金属、合金或者为掺杂的多晶硅。
本发明所提出的半浮栅器件用浮栅存储信息，并通过栅控p-n结二极管对浮栅进行充电或放电，具有单元面积小、芯片密度高、对数据进行存储时操作电压低、数据保持能力强等优点。
附图说明
图1为现有技术的的一种平面沟道的半导体存储器的剖面图。
图2为本发明所提出的半浮栅器件的一个实施例的剖面图及等效电路图。
图3至图10为本发明提出的半浮栅器件的制造方法的一个实施例的工艺流程图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细的说明。在图中，为了方便说明，放大了层和区域的厚度，所示大小并不代表实际尺寸。参考图是本发明的理想化实施例的示意图，本发明所示的实施例不应该被认为仅限于图中所示区域的特定形状，而是包括所得到的形状，比如制造引起的偏差。例如刻蚀得到的曲线通常具有弯曲或圆润的特点，但在本发明实施例中，均以矩形表示，图中的表示是示意性的，但这不应该被认为是限制本发明的范围。
图2a是本发明所提出的半浮栅器件的三个实施例，它是沿该器件沟道长度方向的剖面图。如图2a所示，本发明所提出的半浮栅器件包括一个具有第一种掺杂类型的半导体衬底200以及在半导体衬底200内形成的垂直沟道区401，垂直沟道区401是该半浮栅器件在进行工作时在半导体衬底200内形成的反型层。在半导体衬底200内位于垂直沟道区401的底部形成有具有第二种掺杂类型的源区201以及位于垂直沟道区401的顶部形成有具有第二种掺杂类型的漏区202。半导体衬底200可以为单晶硅、多晶硅或者为绝缘体上的硅。所述的第一种掺杂类型为n型，所述的第二种掺杂类型为p型，或者，所述的第一种掺杂类型为p型，所述的第二种掺杂类型为n型。
覆盖源区201、漏区202和垂直沟道区401形成有第一层绝缘薄膜203，在垂直沟道区401的顶部覆盖漏区202的第一层绝缘薄膜203中形成有一个浮栅开口区域204。第一层绝缘薄膜203可以为二氧化硅、氮化硅、氮氧化硅或者为氧化铪等高介电常数的绝缘材料，其物理厚度范围优选为1-20纳米。
在第一层绝缘薄膜203之上且覆盖垂直沟道区401和浮栅开口区域204形成有一个作为电荷存储节点的具有第一种掺杂类型的浮栅205。浮栅205具有与漏区202相反的掺杂类型，且浮栅205中的掺杂杂质会通过浮栅开口区域204扩散至漏区202中形成具有第一种掺杂类型的扩散区402，从而通过浮栅开口区域204在浮栅205与漏区202之间形成一个p-n结二极管。
覆盖浮栅205和所述的p-n结二极管结构形成有第二层绝缘薄膜206，第二层绝缘薄膜206可以为二氧化硅、氮化硅、氮氧化硅或者为氧化铪等高介电常数的绝缘材料，其物理厚度范围优选为1-20纳米。
在第二层绝缘薄膜206之上且覆盖浮栅205和所述的p-n结二极管形成有器件的控制栅207，控制栅207可以为金属、合金或者为掺杂的多晶硅。
在控制栅207的两侧还形成有器件的栅极侧墙208，栅极侧墙208可以为二氧化硅或者氮化硅，栅极侧墙是业界所熟知的结构，用于将控制栅207与器件中的其它导电层隔离。
在漏区202内还分别形成有与漏区202相同掺杂类型的掺杂区210，掺杂区210的掺杂浓度明显高于漏区202的掺杂浓度，用于降低器件的欧姆接触。
本发明的半浮栅器件还包括由导电材料形成的用于将所述源区201、控制栅207、漏区202、半导体衬底200与外部电极相连接的源区的接触体211、控制栅的接触体212、漏区的接触体213和半导体衬底的接触体214。
为进一步详细地描述本发明所公开的半浮栅器件的结构和功能，图2b展示了本发明的半浮栅器件的等效电路图。如图2b所示，本发明的半浮栅器件包含一个具有源极32、漏极30、浮栅33和控制栅31的MOSFET 36以及一个以MOSFET 36的控制栅31为栅极的栅控二极管35。MOSFET 36的浮栅33可以与栅控二极管35的阳极相连接，也可以与栅控二极管35的阴极相连接，在本发明的图2b所示的实施例中，浮栅33与栅控二极管35的阳极相连接。通过对控制栅31、漏极30和源极31施加适当的电压，栅控二极管35可以对浮栅33进行充电或放电以此来改变储存在浮栅33内的电荷数量，此电荷数量决定了该半浮栅器件的逻辑状态。
本发明所公开的半浮栅器件可以通过很多方法制造，以下所叙述的是本发明所提出的制造如图2a所示结构的具有n型沟道的半浮栅器件的一个实施例的工艺流程。
首先，如图3所示，在提供的具有第一种掺杂类型的半导体衬底200内通过浅沟槽隔离（STI）工序形成有源区（图中未示出）,这种STI工艺是业界所熟知的。然后通过离子注入工艺在半导体衬底200内形成具有第二种掺杂类型的轻掺杂区300。半导体衬底200可以为单晶硅、多晶硅或者为绝缘体上的硅。所述的第一种掺杂类型为p型，所述的第二种掺杂类型为n型。
接下来，在半导体衬底200的表面淀积一层硬掩膜层301，硬掩膜层301比如为氮化硅。接着在硬掩膜层301之上淀积一层光刻胶302并掩膜、曝光、显影定义出器件的垂直沟道区的位置，然后刻蚀掉暴露的硬掩膜层301，并以硬掩膜层301为掩膜通过干法刻蚀的方法刻蚀暴露出的半导体衬底200，从而形成在半导体衬底200内的垂直沟道区区域。对半导体衬底200的刻蚀深度需深于具有第二种掺杂类型的轻掺杂区300的深度，此时具有第二种掺杂类型的轻掺杂区300也会被刻蚀掉一部分，剩余的具有第二种掺杂类型的轻掺杂区300形成器件的漏区202，如图4所示。
接下来，剥除光刻胶303并续刻蚀掉剩余的硬掩膜层301，接着在半导体衬底200的暴露表面上生长第一层绝缘薄膜203，第一层绝缘薄膜203可以为氧化硅、氮化硅、氮氧化硅或者为氧化铪等高介电常数的绝缘材料，其物理厚度优选为1-20纳米。接着在第一层绝缘薄膜203之上淀积一层光刻胶并通过光刻工艺定义出浮栅开口区域的位置，然后以光刻胶为掩膜刻蚀掉暴露出的第一层绝缘薄膜203，从而在垂直沟道区的顶部覆盖漏区202的第一层绝缘薄膜203中形成一个浮栅开口区域204，剥除光刻胶如图5所示。
接下来，在已形成结构的暴露表面上淀积一层具有第一种掺杂类型的第一层导电薄膜，该导电薄膜为具有p型掺杂类型的多晶硅。接着对所形成的第一层导电薄膜进行回刻以形成器件的浮栅205。浮栅205至少覆盖垂直沟道区和浮栅开口区域204。浮栅205中的掺杂杂质会通过浮栅开口区域204扩散至漏区202中形成p型扩散区402，且通过浮栅开口区域204在浮栅205与漏区202之间形成的一个p-n结二极管。剥除光刻胶后如图6所示。
接下来，刻蚀掉暴露出的第一层绝缘薄膜203，并在已形成结构的暴露表面上生长第二层绝缘薄膜206，第二层绝缘薄膜206可以为氧化硅、氮化硅、氮氧化硅或者为氧化铪等高介电常数的绝缘材料，其物理厚度优选为1-20纳米。接着在第二层绝缘薄膜206之上淀积形成第二层导电薄膜207，第二层导电薄膜207可以为金属、合金或者为掺杂的多晶硅。然后在第二层导电薄膜207之上淀积一层光刻胶并通过光刻工艺定义出器件的控制栅的位置，接着以光刻胶为掩膜刻蚀掉暴露出的第二层导电薄膜，刻蚀后剩余的第二层导电薄膜形成器件的控制栅207，控制栅207应覆盖浮栅205与所形成的p-n结二极管，剥除光刻胶后如图7所示。
接下来，在已形成结构的暴露表面上淀积形成第三层绝缘薄膜，接着在所形成的第三层绝缘薄膜之上淀积一层光刻胶并通过光刻工艺形成图形，然后刻蚀掉暴露出的第三层绝缘薄膜，并继续刻蚀掉暴露出的第二层绝缘薄膜206，刻蚀后剩余的第三层绝缘薄膜在控制栅207的两侧形成栅极侧墙208，该工艺是业界所熟知的，剥除光刻胶后如图8所示。栅极侧墙208可以为氧化硅或者氮化硅。
接下来，进行第二种掺杂类型（n型）的杂质离子注入，对控制栅207和未被控制栅207覆盖的半导体衬底200进行掺杂，形成源区201和控制栅207的掺杂结构，并在漏区202中形成高浓度的掺杂区210，如图9所示。
最后，以导电材料形成用于将源区201、控制栅207、漏区202、半导体衬底200与外部电极相连接的源区的接触体211、控制栅的接触体212、漏区的接触体213以及半导体衬底的接触体214，如图10所示。
如上所述，在不偏离本发明精神和范围的情况下，还可以构成许多有很大差别的实施例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。

Claims (8)

1. 一种半浮栅器件，其特征在于，包括：
一个具有第一种掺杂类型的半导体衬底；
在所述半导体衬底内形成的垂直沟道区；
所述垂直沟道区的底部与具有第二种掺杂类型的源区连接，所述垂直沟道区的顶部与具有第二种种掺杂类型的漏区连接；
覆盖所述源区、漏区与垂直沟道区形成的第一层绝缘薄膜；
在半导体衬底水平表面上且覆盖所述漏区的第一层绝缘薄膜中，形成的一个浮栅开口区域；
覆盖所述第一层绝缘薄膜和浮栅开口区域,形成一个具有第一种掺杂类型的浮栅；该浮栅作为电荷存储节点，位于垂直沟道区和浮栅开口区之上，一方面通过所述浮栅开口区，在所述浮栅与漏区之间形成一个p-n结二极管；另一方面因为覆盖在垂直沟道区的第一层绝缘薄膜上，可以通过电场调控来控制沟道区内电流的通与断； 
覆盖所述源区、浮栅与p-n结二极管形成的第二层绝缘薄膜；
在所述第二层绝缘薄膜之上，且覆盖所述浮栅与栅控p-n结二极管形成的控制栅。
2. 根据权利要求1所述的半浮栅器件，其特征在于，所述的第一种掺杂类型为n型，所述的第二种掺杂类型为p型；或者，所述的第一种掺杂类型为p型，所述的第二种掺杂类型为n型。
3. 根据权利要求1所述的半浮栅器件，其特征在于，所述的第一层绝缘薄膜、第二层绝缘薄膜由二氧化硅、氮化硅、氮氧化硅或者高介电常数的绝缘材料形成，所述的浮栅由掺杂的多晶硅形成，所述的控制栅由金属、合金或者掺杂的多晶硅形成。
4. 根据权利要求1所述的半浮栅器件，其特征在于，所述的p-n结二极管、第二层绝缘薄膜和控制栅构成了一个以所述控制栅作为栅极的栅控二极管，所述栅控二极管的阳极与所述浮栅相连接，所述栅控二极管的阴极与所述漏区相连接；或者，所述栅控二极管的阴极与所述浮栅相连接，所述栅控二极管的阳极与所述漏区相连接。
5. 如权利要求1所述的半浮栅器件的制备方法，其特征在于，具体步骤如下：
在具有第一种掺杂类型的半导体衬底内形成具有第二种掺杂类型的轻掺杂区；
在所述半导体衬底表面淀积一硬掩膜层并通过光刻工艺和刻蚀工艺定义出器件的垂直沟道区的位置；
以所述硬掩膜层为掩膜刻蚀暴露出的半导体衬底，形成器件的垂直沟道区区域，刻蚀的深度需深于所形成的具有第二种掺杂类型的轻掺杂区的深度，此时具有第二种掺杂类型的轻掺杂区会被刻蚀掉一部分，剩余的具有第二种掺杂类型的轻掺杂区形成器件的漏区；
刻蚀掉剩余的硬掩膜层；
在半导体衬底的暴露表面上生长第一层绝缘薄膜并刻蚀所形成的第一层绝缘薄膜形成浮栅开口区域，所形成的浮栅开口区域在垂直沟道区的顶部将漏区暴露出来；
接着，在所形成结构的暴露表面上淀积具有第一种掺杂类型的第一层导电薄膜，并对所形成的第一层导电薄膜进行回刻以形成器件的浮栅，其中，浮栅至少覆盖所形成的垂直沟道区和浮栅开口区域；
接着，在已形成结构的暴露表面上生长第二层绝缘薄膜；
在所述第二层绝缘薄膜之上淀积形成第二层导电薄膜，然后通过光刻工艺和刻蚀工艺刻蚀所形成的第二层导电薄膜以形成器件的控制栅；
进行第二种掺杂类型的离子注入，对控制栅和未被控制栅覆盖的半导体衬底进行掺杂以形成器件的源区以及漏区和控制栅的掺杂结构。
6. 根据权利要求5所述的半浮栅器件的制备方法，其特征在于，还包括以导电材料形成用于将所述源区、控制栅、漏区、半导体衬底与外部电极相连接的源区的接触体、控制栅的接触体、漏区的接触体和半导体衬底的接触体。
7. 根据权利要求5所述的半浮栅器件的制备方法，其特征在于，所述的第一种掺杂类型为n型，所述的第二种掺杂类型为p型；或者，所述的第一种掺杂类型为p型，所述的第二种掺杂类型为n型。
8. 根据权利要求5所述的半浮栅器件的制备方法，其特征在于，所述的第一层绝缘薄膜、第二层绝缘薄膜为二氧化硅、氮化硅、氮氧化硅或者为高介电常数的绝缘材料，所述的第一层导电薄膜为掺杂的多晶硅，所述的第二层导电薄膜为金属、合金或者为掺杂的多晶硅。
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