WO2021109160A1 - 半导体功率器件的制造方法 - Google Patents

半导体功率器件的制造方法 Download PDF

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WO2021109160A1
WO2021109160A1 PCT/CN2019/123906 CN2019123906W WO2021109160A1 WO 2021109160 A1 WO2021109160 A1 WO 2021109160A1 CN 2019123906 W CN2019123906 W CN 2019123906W WO 2021109160 A1 WO2021109160 A1 WO 2021109160A1
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type
power device
semiconductor power
dielectric layer
floating gate
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PCT/CN2019/123906
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English (en)
French (fr)
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龚轶
刘伟
刘磊
袁愿林
王睿
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苏州东微半导体有限公司
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Publication of WO2021109160A1 publication Critical patent/WO2021109160A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors

Definitions

  • This application relates to the technical field of semiconductor power devices, for example, to a method of manufacturing a semiconductor power device.
  • FIG. 1 is a schematic cross-sectional structure diagram of a related art semiconductor power device.
  • a related art semiconductor power device includes an n-type drain region 31 and an n-type drift region located on the n-type drain region 31 30.
  • a p-type body region 33 is provided in the n-type drift region 30, and a parasitic body diode structure in the semiconductor power device is formed between the p-type body region 33 and the n-type drift region 30.
  • An n-type source region 34 is provided in the p-type body region 33, and the p-type body region contact region 38 and the source metal contact layer 47 form an ohmic contact structure.
  • the gate dielectric layer 35 and the gate 36 are located above the current channel in the p-type body region 33.
  • the n-type source region 34 and the p-type body region contact region 38 are connected to the source voltage through the source metal contact layer 47.
  • the source metal contact layer 47 is separated from other conductive layers by an interlayer insulating layer 50.
  • the parasitic body diode in the semiconductor power device When the related art semiconductor power device is turned off, when the drain-source voltage Vds is less than 0V, the parasitic body diode in the semiconductor power device is in a forward bias state, and the reverse current flows from the source to the drain through the body diode.
  • the current of the body diode has the phenomenon of injecting minority carrier carriers, and these minority carrier carriers undergo reverse recovery when the semiconductor power device is turned on again, resulting in a larger reverse recovery current and a long reverse recovery time.
  • the present application provides a method for manufacturing a semiconductor power device with a fast reverse recovery speed, so as to solve the technical problem of long reverse recovery time caused by the minority carrier injection problem of the semiconductor power device in the related art.
  • the manufacturing method of a semiconductor power device includes:
  • n-type floating gate on the first insulating dielectric layer, and the n-type floating gate is in contact with the p-type body region through the opening to form a p-n junction diode;
  • An n-type source region is formed in the p-type body region.
  • the distance from the center of the opening to the side edge of the n-type floating gate close to the n-type source region is greater than the center of the opening to the other side of the n-type floating gate. The distance from one side edge.
  • the gate In the length direction of the current channel, the gate is used to control the opening and closing of the current channel of a section close to the n-type source region, and the n-type floating gate is used to control the current channel of the remaining section Turning on and turning off, the gate extends above the n-type floating gate.
  • the gate covers the edge of the n-type floating gate that is far from the n-type source region.
  • the material of the first insulating dielectric layer is silicon dioxide.
  • the first insulating dielectric layer is formed by a thermal oxidation method.
  • the material of the second insulating dielectric layer is silicon dioxide.
  • the second insulating dielectric layer is formed by a thermal oxidation method.
  • the manufacturing method of a semiconductor power device provided by the present application is compatible with the manufacturing method of a related art semiconductor power device, the manufacturing process is simple and stable, and the manufactured semiconductor power device has a fast reverse recovery speed.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor power device in the related art.
  • FIGS. 2 to 6 are schematic cross-sectional structure diagrams of main process node structures in a method of manufacturing a semiconductor power device provided by an embodiment of the present application.
  • FIG. 2 to 6 are schematic cross-sectional structural diagrams of the main process node structure in a method for manufacturing a semiconductor power device provided by an embodiment of the present application.
  • a semiconductor substrate 20 is provided.
  • the material of is usually silicon with n-type doping.
  • the position of the p-type body region is defined by a photolithography process and an etching process, and then p-type ion implantation is performed to form a p-type body region 21 on the top of the semiconductor substrate 20.
  • a semiconductor power device usually includes a p-type body region array formed by a plurality of p-type body regions, and only one p-type body region 21 is exemplarily shown in the embodiment of the present application.
  • a first insulating dielectric layer 22 is formed on the surface of the semiconductor substrate 20 through a thermal oxidation process.
  • the material of the first insulating dielectric layer 22 is usually silicon dioxide.
  • the position of the opening in the first insulating dielectric layer 22 is defined by a photolithography process, and then the first insulating dielectric layer 22 is etched to form an opening 10 in the first insulating dielectric layer 22, and the opening 10 is a p-type body Zone 21 is exposed.
  • n-type polysilicon is formed on the first insulating dielectric layer 22, and then the formed n-type polysilicon layer is etched and the exposed first insulating dielectric layer 22 is continuously etched away.
  • the remaining n-type polysilicon after etching forms the n-type floating gate 23 of the semiconductor power device, and the n-type floating gate 23 contacts the p-type body region 21 through the opening 30 to form a pn junction diode.
  • a second insulating dielectric layer 24 is formed on the surface of the semiconductor substrate 20 and covering the n-type floating gate 23, and then doped polysilicon is formed on the second insulating dielectric layer 24, and then The formed polysilicon is etched and the exposed second insulating dielectric layer 24 is continuously etched away. The remaining polysilicon after etching forms the gate 25 of the semiconductor power device, and the gate 25 is capacitively coupled to the n-type floating gate 23.
  • the second insulating dielectric layer 24 is usually silicon dioxide formed by a thermal oxidation process.
  • an n-type source region 26 is formed in the p-type body region 21.
  • the gate 25 is used to control the turn-on and turn-off of the current channel near the n-type source region 26.
  • the floating gate 23 is used to control the opening and closing of the current channel of the remaining section.
  • the gate 25 extends above the n-type floating gate 23 to increase the area of the gate 25 covering the n-type floating gate 23, thereby increasing the gate area.
  • the gate 25 when the gate 25 extends above the n-type floating gate 23, it can also cover the edge of the n-type floating gate 23 away from the n-type source region 26, thereby further increasing the influence of the gate 25 on the n-type floating gate.
  • the capacitive coupling ratio of the gate when the gate 25 extends above the n-type floating gate 23, it can also cover the edge of the n-type floating gate 23 away from the n-type source region 26, thereby further increasing the influence of the gate 25 on the n-type floating gate.
  • the source contact metal layer, the gate contact metal layer, the n-type drain region, and the drain contact metal layer of the semiconductor power device can be prepared by the manufacturing method of the semiconductor power device in the related art. Show this step in detail.
  • the n-type floating gate 23 contacts the p-type body region 21 to form a pn junction diode.
  • the drain is applied high Voltage
  • the pn junction diode formed by the n-type floating gate 23 and the p-type body region 21 is forward biased
  • the n-type floating gate 23 is charged with a positive charge, which makes the threshold of the current channel under the n-type floating gate 23
  • the voltage Vht1 decreases.
  • the center of the opening 10 can be made close to the n-type floating gate 23 in the length direction of the current channel.
  • the distance between one side edge of the n-type source region 26 is greater than the distance from the center of the opening 10 to the other side edge of the n-type floating gate 23, that is, the opening 10 is arranged closer to the edge of the p-type body region 21, so that the n-type floating The gate 23 is more easily charged with positive charges.
  • the drain-source voltage Vds is greater than 0V, and the threshold voltage Vht1 of the current channel under the n-type floating gate 23 has a very low impact on the threshold voltage Vth of the entire semiconductor power device.
  • the semiconductor power device still has a high threshold voltage Vth.
  • the semiconductor power device of the embodiment of the present application is turned off, when the source-drain voltage Vsd is greater than 0V, the threshold voltage Vht1 of the current channel under the n-type floating gate 23 has a great influence on the threshold voltage Vth of the entire semiconductor power device.
  • the semiconductor power device have a low threshold voltage Vth, so that the semiconductor power device is turned on at a low gate voltage (or 0V voltage), thereby increasing the reverse current flowing through the current channel in the semiconductor power device and reducing the power flowing through the semiconductor
  • the current of the parasitic body diode in the device improves the reverse recovery speed of the semiconductor power device.

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Abstract

本申请提供的半导体功率器件的制造方法，包括：在提供的半导体衬底的顶部形成p型体区；形成第一绝缘介质层并在第一绝缘介质层中形成开口；形成n型浮栅并使得n型浮栅通过所述开口与所述p型体区接触形成p-n结二极管，形成栅极。

Description

半导体功率器件的制造方法
本公开要求在2019年12月03日提交中国专利局、申请号为201911223282.0的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请涉及半导体功率器件技术领域，例如涉及一种半导体功率器件的制造方法。
背景技术
图1是相关技术的一种半导体功率器件的剖面结构示意图，如图1所示，相关技术的一种半导体功率器件包括n型漏区31和位于n型漏区31之上的n型漂移区30，在n型漂移区30内设有p型体区33，p型体区33和n型漂移区30之间形成半导体功率器件中寄生的体二极管结构。在p型体区33内设有n型源区34，p型体区接触区38和源极金属接触层47形成欧姆接触结构。栅介质层35和栅极36位于p型体区33内的电流沟道之上。n型源区34和p型体区接触区38通过源极金属接触层47接源极电压。源极金属接触层47与其它导电层之间由层间绝缘层50隔离。
相关技术的半导体功率器件在关断时，当漏源电压Vds小于0V时，半导体功率器件内寄生的体二极管处于正偏压状态，反向电流从源极经体二极管流至漏极，此时体二极管的电流存在注入少子载流子现象，而这些少子载流子在半导体功率器件再一次开启时进行反向恢复，导致较大的反向恢复电流，反向恢复时间长。
发明内容
本申请提供一种反向恢复速度快的半导体功率器件的制造方法，以解决相关技术中的半导体功率器件因少子载流子注入问题造成的反向恢复时间长的技术问题。
本申请提供的一种半导体功率器件的制造方法，包括：
提供一半导体衬底；
在所述半导体衬底的顶部形成p型体区；
在所述半导体衬底的表面形成第一绝缘介质层；
在所述第一绝缘介质层中形成开口，所述开口将所述p型体区露出；
在所述第一绝缘介质层之上形成n型浮栅，所述n型浮栅通过所述开口与所述p型体区接触形成p-n结二极管；
在所述半导体衬底的表面并覆盖所述n型浮栅形成第二绝缘介质层；
在所述第二绝缘介质层之上形成栅极，所述栅极通过电容耦合作用于所述n型浮栅；
在所述p型体区内形成n型源区。
在电流沟道的长度方向上，所述开口的中心到所述n型浮栅的靠近所述n型源区的一侧边沿的距离大于所述开口的中心到所述n型浮栅的另一侧边沿的距离。
在电流沟道的长度方向上，所述栅极用于控制靠近所述n型源区的一段的电流沟道的开启和关断，所述n型浮栅用于控制剩余一段的电流沟道的开启和关断，所述栅极延伸至所述n型浮栅之上。
所述栅极覆盖所述n型浮栅的远离所述n型源区的一侧的边沿。
所述第一绝缘介质层的材质为二氧化硅。
所述第一绝缘介质层通过热氧化的方法形成。
所述第二绝缘介质层的材质为二氧化硅。
所述第二绝缘介质层通过热氧化的方法形成。
本申请提供的一种半导体功率器件的制造方法，与相关技术的半导体功率器件的制造方法兼容，制造工艺简单稳定，所制造得到的半导体功率器件具有快的反向恢复速度。
附图说明
图1是相关技术的一种半导体功率器件的剖面结构示意图。
图2至图6是本申请实施例提供的一种半导体功率器件的制造方法中的主要工艺节点结构的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过具体实施方式，完整地描述本申 请的技术方案。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的尺寸，且所列图形大小并不代表实际尺寸。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图2至图6是本申请实施例提供的一种半导体功率器件的制造方法中的主要工艺节点结构的剖面结构示意图，首先，如图2所示，提供一半导体衬底20，半导体衬底20的材质通常为硅且具有n型掺杂。通过光刻工艺和刻蚀工艺定义p型体区的位置，然后进行p型离子注入在半导体衬底20的顶部形成p型体区21。
需要说明的是，根据半导体功率器件所设计需要的功能，在提供的半导体衬底20中可以已经形成有其它结构，如沟槽结构、用于形成超结结构的p型柱状掺杂区等，这些结构在本申请实施例中不再具体展示。
半导体功率器件中通常包含由多个p型体区形成的p型体区阵列，本申请实施例中仅示例性的示出了一个p型体区21。
接下来，如图3所示，通过热氧化工艺，在半导体衬底20的表面形成第一绝缘介质层22，第一绝缘介质层22的材质通常为二氧化硅。然后通过光刻工艺定义出位于第一绝缘介质层22中的开口的位置，之后对第一绝缘介质层22进行刻蚀，在第一绝缘介质层22中形成开口10，开口10将p型体区21暴露出来。
接下来，如4所示，在第一绝缘介质层22之上形成一层n型多晶硅，然后对所形成的n型多晶硅层进行刻蚀并继续刻蚀掉暴露出的第一绝缘介质层22，刻蚀后剩余的n型多晶硅形成半导体功率器件的n型浮栅23，n型浮栅23通过开口30与p型体区21接触形成p-n结二极管。
接下来，如图5所示，在半导体衬底20的表面并覆盖n型浮栅23形成第二绝缘介质层24，并继续在第二绝缘介质层24之上形成掺杂的多晶硅，然后对所形成多晶硅进行刻蚀并继续刻蚀掉暴露出的第二绝缘介质层24，刻蚀后剩余的多晶硅形成半导体功率器件的栅极25，栅极25通过电容耦合作用与n型浮栅23。第二绝缘介质层24通常为通过热氧化工艺形成的二氧化硅。
接下来，如图6所示，在p型体区21内形成n型源区26。
通过本申请提供的半导体功率器件的制造方法制备得到n型浮栅23和栅极25时，使得栅极25用于控制靠近n型源区26的一段的电流沟道的开启和关断，n型浮栅23用于控制剩余一段的电流沟道的开启和关断，栅极25延伸至n型浮栅23之上可以增大栅极25覆盖n型浮栅23的面积，进而增大栅极25对n型浮栅23的电容耦合率。可选的，栅极25延伸至n型浮栅23之上时还可以覆盖n型浮栅23的远离n型源区26的一侧的边沿，由此进一步增大栅极25对n型浮栅的电容耦合率。
最后，通过相关技术的半导体功率器件的制造方法制备得到半导体功率器件的源极接触金属层、栅极接触金属层、n型漏区、漏极接触金属层即可，本申请实施例中不再具体展示该步骤。
通过本申请提供的半导体功率器件的制造方法得到的半导体功率器件，n型浮栅23与p型体区21接触形成p-n结二极管，半导体功率器件在正向阻断状态时，漏极被施加高电压，由n型浮栅23与p型体区21形成的p-n结二极管被正向偏置，n型浮栅23被充入正电荷，这使得n型浮栅23下面的电流沟道的阈值电压Vht1降低。本申请的半导体功率器件的制造方法，在制造得到位于第一绝缘介质层22中的开口10时，可以在电流沟道的长度方向上，使得开口10的中心到n型浮栅23的靠近n型源区26的一侧边沿的距离大于开口10的中心到n型浮栅23的另一侧边沿的距离，即使得开口10更靠近p型体区21的边沿设置，这样可使n型浮栅23更容易的被充入正电荷。
半导体功率器件在正向阻断状态和正向开启状态时，漏源电压Vds大于0V，n型浮栅23下面的电流沟道的阈值电压Vht1对整个半导体功率器件的阈值电压Vth的影响很低，半导体功率器件仍具有高阈值电压Vth。本申请实施例的半导体功率器件在关断时，当源漏电压Vsd大于0V时，n型浮栅23下面的电流沟道的阈值电压Vht1对整个半导体功率器件的阈值电压Vth的影响很大，使得半导体功率器件具有低阈值电压Vth，从而使半导体功率器件在低栅极电压(或0V电压)下开启，从而能够增加流过半导体功率器件中电流沟道的反向电流，减少流过半导体功率器件中寄生的体二极管的电流，提高半导体功率器件的反向恢复速度。

Claims (8)

  1. 半导体功率器件的制造方法，包括：
    提供一半导体衬底；
    在所述半导体衬底的顶部形成p型体区；
    在所述半导体衬底的表面形成第一绝缘介质层；
    在所述第一绝缘介质层中形成开口，所述开口将所述p型体区露出；
    在所述第一绝缘介质层之上形成n型浮栅，所述n型浮栅通过所述开口与所述p型体区接触形成p-n结二极管；
    在所述半导体衬底的表面并覆盖所述n型浮栅形成第二绝缘介质层；
    在所述第二绝缘介质层之上形成栅极，所述栅极通过电容耦合作用于所述n型浮栅；
    在所述p型体区内形成n型源区。
  2. 如权利要求1所述的半导体功率器件的制造方法，其中，在电流沟道的长度方向上，所述开口的中心到所述n型浮栅的靠近所述n型源区的一侧边沿的距离大于所述开口的中心到所述n型浮栅的另一侧边沿的距离。
  3. 如权利要求1所述的半导体功率器件的制造方法，其中，在电流沟道的长度方向上，所述栅极用于控制靠近所述n型源区的一段的电流沟道的开启和关断，所述n型浮栅用于控制剩余一段的电流沟道的开启和关断，所述栅极延伸至所述n型浮栅之上。
  4. 如权利要求1所述的半导体功率器件的制造方法，其中，所述栅极覆盖所述n型浮栅的远离所述n型源区的一侧的边沿。
  5. 如权利要求1所述的半导体功率器件的制造方法，其中，所述第一绝缘介质层的材质为二氧化硅。
  6. 如权利要求5所述的半导体功率器件的制造方法，其中，所述第一绝缘介质层通过热氧化的方法形成。
  7. 如权利要求1所述的半导体功率器件的制造方法，其中，所述第二绝缘介质层的材质为二氧化硅。
  8. 如权利要求7所述的半导体功率器件的制造方法，其中，所述第二绝缘介质层通过热氧化的方法形成。
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