WO2019085752A1 - 功率mosfet器件 - Google Patents

功率mosfet器件 Download PDF

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Publication number
WO2019085752A1
WO2019085752A1 PCT/CN2018/110570 CN2018110570W WO2019085752A1 WO 2019085752 A1 WO2019085752 A1 WO 2019085752A1 CN 2018110570 W CN2018110570 W CN 2018110570W WO 2019085752 A1 WO2019085752 A1 WO 2019085752A1
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region
type
source
gate
diode
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PCT/CN2018/110570
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English (en)
French (fr)
Inventor
刘磊
袁愿林
刘伟
毛振东
龚轶
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苏州东微半导体有限公司
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Priority claimed from CN201711058065.1A external-priority patent/CN109755309B/zh
Priority claimed from CN201711058204.0A external-priority patent/CN109755241B/zh
Application filed by 苏州东微半导体有限公司 filed Critical 苏州东微半导体有限公司
Priority to KR1020197037283A priority Critical patent/KR102288862B1/ko
Priority to JP2020510097A priority patent/JP6995187B2/ja
Priority to US16/644,998 priority patent/US11296216B2/en
Publication of WO2019085752A1 publication Critical patent/WO2019085752A1/zh

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Definitions

  • the present disclosure relates to the field of semiconductor power device technology, for example, to a power MOSFET device.
  • FIG. 1 An equivalent circuit of a related art metal oxide semiconductor field effect transistor (MOSFET) device is shown in FIG. 1 and includes a drain 101, a source 102, a gate 103, and a body diode 104. Among them, the body diode 104 is an intrinsic parasitic structure in a power MOSFET device. The gate of the power MOSFET device controls the turn-on and turn-off of the current channel of the power MOSFET device through the gate voltage.
  • MOSFET metal oxide semiconductor field effect transistor
  • the working mechanism of the power MOSFET device is: 1) when the gate-source voltage Vgs is smaller than the threshold voltage Vth of the power MOSFET device, the drain source When the voltage Vds is greater than 0V, the power MOSFET device is in the off state; 2) when the gate-source voltage Vgs is greater than the threshold voltage Vth of the power MOSFET device, and the drain-source voltage Vds is greater than 0V, the power MOSFET device is turned on, and the current is drained. The current channel at the pole through the gate flows to the source.
  • the body diode of the power MOSFET device When the power MOSFET device is turned off, when the drain-source voltage Vds is less than 0V, the body diode of the power MOSFET device is in a positive bias state, and the reverse current flows from the source through the body diode to the drain, and the current of the body diode exists.
  • the minority carrier phenomenon is injected, and these minority carriers are reverse-recovered when the power MOSFET device is turned on again, resulting in a large reverse recovery current of the power MOSFET device and a long reverse recovery time.
  • parasitic body diodes in power MOSFET devices experience a process of minority carrier carrier reverse recovery.
  • the reverse recovery current generated by the minority carrier causes an increase in the loss of the power MOSFET device, which reduces the efficiency of the system, and also causes the upper and lower transistors to directly burn out the device and affect the safe operation of the power MOSFET device.
  • the method for improving the reverse recovery speed of the power MOSFET device includes the following: (1) reverse parallel fast recovery diode, the disadvantage of the method is that the package volume is increased, and the manufacturing cost is greatly increased; (2) the integration Xiao Special base diodes, the disadvantages of this method are low withstand voltage, large leakage current, and increased power consumption; (3) life control techniques such as: electron irradiation, particle irradiation (protons, alpha particles), deep level composite At the center, etc., the disadvantage of this method is that the process difficulty is increased, the manufacturing cost is increased, and the device leakage current and the on-resistance become large, and the power consumption increases.
  • the present disclosure provides a power MOSFET device having a fast reverse recovery function to solve the problem of a long reverse recovery time of a power MOSFET device in the related art due to a minority carrier injection problem.
  • a power MOSFET device includes a source, a drain, a first gate, a second gate, a body diode, and a body contact diode, and the source, the drain, and the first gate constitute a first MOSFET structure.
  • the source, the drain, and the second gate constitute a second MOSFET structure, the cathode of the body diode is connected to the drain, and the anode of the body contact diode is connected to the anode of the body diode, the body a cathode of the area contact diode is connected to the source, the first gate controls opening and closing of the first MOSFET structure by a gate voltage, and the second gate is connected to the source, The second gate controls the turn-on and turn-off of the second MOSFET structure by a source voltage.
  • a threshold voltage of the first MOSFET structure is greater than a threshold voltage of the second MOSFET structure.
  • the power MOSFET device includes: an n-type drain region and an n-type drift region above the n-type drain region, wherein the n-type drift region is provided with a p-type body region, the p a p-type body contact region, a first n-type source region and a second n-type source region are disposed in the body region; a conductive layer above the p-type body region contact region, the conductive layer and the p The body region contact region forms the body region contact diode, wherein the conductive layer is a cathode of the body region contact diode, and the p-type body region contact region is an anode of the body region contact diode; a first current channel in the body region and between the first n-type source region and the n-type drift region, covering a gate dielectric layer of the first current channel and the first gate The first gate controls opening and closing of the first current channel by a gate voltage; is located in the p-type body region and inter
  • the conductive layer is a source metal contact layer over the p-type body region, and a doping concentration of the p-type body region contact region is lower than a doping of the p-type body region.
  • the maximum peak concentration, the p-type body region contact region and the source metal contact layer form a Schottky barrier diode structure.
  • the second gate is connected to the first n-type source region and the second n-type source region through the source metal contact layer, and the source metal contact layer is externally connected to the source Voltage.
  • the conductive layer is an n-type polysilicon layer over the p-type body region, and the n-type polysilicon layer and the p-type body region contact region form a silicon-based body region contact diode structure.
  • the n-type polysilicon layer is directly connected to the second gate, the first n-type source region, and the second n-type source region, and the n-type polysilicon layer passes through a source metal
  • the contact layer is externally connected to the source voltage.
  • the conductive layer is an n-type doped region located in the contact region of the p-type body region, and the n-type doped region is disposed in the first n-type source region and the second n-type region Between the source regions, the n-type doped region and the p-type body region contact region form a silicon-based body region contact diode structure.
  • the second gate is connected to the first n-type source region, the second n-type source region, and the n-type doped region through a source metal contact layer, the source The metal contact layer is externally connected to the source voltage.
  • the turn-on voltage of the first current channel is greater than the turn-on voltage of the second current channel.
  • the power MOSFET device further includes a p-type columnar epitaxial doped region under the p-type body region, doping impurities of the p-type columnar epitaxial doping region and adjacent n-type drift Doping impurities in the region form a charge balance to form a superjunction structure.
  • the power MOSFET device provided by the present disclosure When the power MOSFET device provided by the present disclosure is turned off, when the source-drain voltage is greater than 0V, the body contact diode is in a negative bias state, thereby greatly reducing the reverse current flowing through the body diode, thereby greatly reducing the body diode.
  • the minority carrier which in turn reduces the reverse recovery charge and reverse recovery time of the power MOSFET device, enabling the power MOSFET device to achieve fast reverse recovery while simultaneously sinking the source-drain voltage to the threshold voltage of the second MOSFET structure
  • the second current channel of the second MOSFET structure is turned on, and the reverse current flows from the source to the drain through the second current channel of the second MOSFET structure.
  • 1 is an equivalent circuit diagram of a related art power MOSFET device
  • FIG. 2 is a schematic diagram of an equivalent circuit of a power MOSFET device according to an embodiment
  • FIG. 3 is a cross-sectional structural view of a power MOSFET device according to an embodiment
  • FIG. 4 is a schematic top plan view of a power MOSFET device according to an embodiment
  • FIG. 5 is a cross-sectional structural view of the power MOSFET device shown in FIG. 4 along the AA direction;
  • FIG. 6 is a schematic cross-sectional structural view of a power MOSFET device according to an embodiment
  • FIG. 7 is a schematic cross-sectional structural view of a power MOSFET device according to an embodiment
  • FIG. 8 is a test comparison diagram of a Vf curve of a power MOSFET device and a related art power MOSFET device according to an embodiment
  • the power MOSFET device includes a cell region for obtaining low on-resistance and a termination region for increasing the withstand voltage of the most marginal cell in the cell region.
  • the termination area is a general structure in power MOSFET devices. There are different design structures according to the requirements of different products. The structure of the termination region of the power MOSFET device is not shown or described in this embodiment. The MOSFET device described in this embodiment refers to the structure of the cell region in the power MOSFET device.
  • FIG. 2 is a schematic diagram showing an equivalent circuit of an embodiment of a power MOSFET device according to an embodiment of the present invention.
  • the power MOSFET device provided in this embodiment includes a drain 301, a source 302, a first gate 303a, a second gate 303b, a body diode 304, and a body contact diode 305, and a second gate 303b.
  • the body contact diode 305 can be a silicon-based diode or a Schottky barrier diode, and the cathode of the body diode 304 is connected to the drain 301, and the body region contacts the anode of the diode 305 and the anode of the body diode 304.
  • the cathode of the body contact diode 305 is connected to the source 302.
  • the drain 301, the source 302, and the first gate 303a constitute a first MOSFET structure, and the first gate 303a controls the first current channel of the first MOSFET structure by the gate voltage.
  • the drain 301, the source 302, and the second gate 303b of the power MOSFET device constitute a second MOSFET structure, and the second gate 303b is connected to the source 302, so that the second gate 303b passes the source voltage To control the opening and closing of the second current channel of the second MOSFET structure.
  • the threshold voltage of the first MOSFET structure is greater than the threshold voltage of the second MOSFET structure.
  • the working mechanism of the power MOSFET device shown in FIG. 2 is: 1) when the gate-source voltage Vgs is smaller than the threshold voltage Vth1 of the first MOSFET structure, and the drain-source voltage Vds is greater than 0V, the power MOSFET device is in an off state; 2) When the gate-source voltage Vgs reaches the threshold voltage Vth1 of the first MOSFET structure, and the drain-source voltage Vds is greater than 0V, the power MOSFET device is turned on, and the first current channel of the first MOSFET structure is turned on, and the current flows from the drain. A current channel flows to the source while the second current channel of the second MOSFET structure is in an off state and no current flows.
  • the body contact diode 305 When the power MOSFET device is turned off: when the source voltage is greater than the drain voltage, the body contact diode 305 is in a negative bias state, so that the reverse current flowing through the body diode can be greatly reduced, thereby greatly reducing the body diode.
  • the minority carrier which in turn can significantly reduce the reverse recovery charge and reverse recovery time of the power MOSFET device, enabling the power MOSFET device to achieve fast reverse recovery; meanwhile, when the source-drain voltage Vsd reaches the second MOSFET structure At the threshold voltage Vth2, the second current channel of the second MOSFET structure is in an on state, such that the reverse current flows from the source 302 through the second current channel of the second MOSFET structure to the drain 301.
  • the power MOSFET device includes an n-type drain region 31 and an n-type drift region 30 over the n-type drain region 31.
  • a p-type columnar epitaxial doping region 32 is also formed in the type drift region 30 (only two p-type columnar epitaxial doping regions 32 are exemplarily shown in FIG. 3, the number of which is set according to actual product requirements), p
  • the doping impurities of the type columnar epitaxial doping region 32 and the doping impurities in the adjacent n-type drift region 30 form a charge balance, thereby forming a super junction structure.
  • a p-type body region 33 is formed on top of the p-type columnar epitaxial doping region 32, that is, the p-type columnar epitaxial doping region 32 is located below the p-type body region 33.
  • the power MOSFET device of the present embodiment When the power MOSFET device of the present embodiment is formed, the p-type pillar-shaped doping region 32 located under the p-type body region 33 may not be formed. At this time, the power MOSFET device of the embodiment is a power without a super junction structure. MOSFET device, a power MOSFET device of conventional structure.
  • a p-type body region contact region 38, a first n-type source region 34a and a second n-type source region 34b are formed in the p-type body region 33, and the p-type body region contact region 38 is formed. It is usually disposed between the first n-type source region 34a and the second n-type source region 34b.
  • a parasitic body diode structure in the power MOSFET device is formed between the p-type body region 33 and the n-type drift region 30, wherein the p-type body region 33 is the anode of the body diode and the n-type drift region is the cathode of the body diode.
  • the power MOSFET device provided in this embodiment further includes a first current channel located in the p-type body region 33 and interposed between the first n-type source region 34a and the n-type drift region 30, covering the first current channel.
  • the gate dielectric layer 35 and the first gate 36a, the first gate 36a is a control gate and controls the opening and closing of the first current channel by the gate voltage.
  • a second current channel located in the p-type body region 33 between the second n-type source region 34b and the n-type drift region 30, covering the gate dielectric layer 35 and the second gate 36b of the second current channel .
  • the turn-on voltage of the second current channel is lower than the turn-on voltage of the first current channel.
  • the current channel is an accumulation layer and an inversion layer formed on the surface of the semiconductor when a gate voltage is applied in the MOSFET structure.
  • the first current channel and the second current channel in the power MOSFET device are both Not shown.
  • the power MOSFET device provided in this embodiment further includes a conductive layer 37 on the p-type body region contact region 38.
  • the conductive layer 37 and the p-type body region contact region 38 form a body region contact diode structure, wherein the conductive layer 37 is the body.
  • the region contacts the cathode of the diode, and the p-type body contact region 38 is the anode of the body contact diode, such that the anode of the body contact diode is connected to the anode of the body diode.
  • the conductive layer 37 may be an n-type polysilicon layer or a metal layer
  • the body contact diode may be a silicon-based body contact diode or a Schottky barrier diode.
  • the second gate 36b, the first n-type source region 34a, the second n-type source region 34b and the conductive layer 37 are electrically connected and connected to the source voltage, so that the second gate 36b is controlled by the source voltage.
  • the second current channel is turned on and off.
  • the conductive layer 37 is directly in contact with the first n-type source region 34a and the second n-type source region 34b, so that only the conductive layer 37 and the second gate 36b need to be electrically connected. Just connect.
  • FIG. 4 is a top plan view of a power MOSFET device according to the present embodiment.
  • FIG. 4 is not a top view.
  • FIG. 4 only shows the positional relationship of a part of the structure of the power MOSFET device of the present embodiment from a top view.
  • 5 is a cross-sectional structural view of the power MOSFET device shown in FIG. 4 along the AA direction, and only two columnar epitaxial doping regions 32 are exemplarily shown in FIG. 4 and 5 correspond to a power MOSFET device provided by the present disclosure.
  • a source metal contact layer 47 is formed over the p-type body region 33.
  • the source metal contact layer 47 is a conductive layer located above the p-type body region contact region 38.
  • the doping concentration of the p-type body contact region 38 needs to be lower than the maximum peak of the doping concentration of the p-type body region 33, whereby the p-type body region contact region 38 and the source metal contact layer 47 form a Schottky barrier A diode structure in which the source metal contact layer 47 is the cathode of the body contact diode, and the p-type body contact region 38 is the anode of the body contact diode.
  • the position of the source metal contact layer in the source metal contact hole is only exemplarily shown in FIG.
  • the source metal contact layer 47 is directly connected to the second gate 36b, the first n-type source region 34a, and the second n-type source region 34b, and the source metal contact layer 47 is externally connected to the source voltage, whereby the second gate 36b passes The source voltage controls the opening and closing of the second current channel near the side of the second n-type source region 34b.
  • the first gate 36a externally connects the gate voltage through the gate metal contact layer 74, whereby the first gate 36a controls the opening and closing of the first current channel near the side of the first n-type source region 34a by the gate voltage.
  • the source metal contact layer 47 and the gate metal contact layer 74 are separated by an interlayer insulating layer 50.
  • the interlayer insulating layer 50 is usually a material such as silicon glass, borophosphosilicate glass or phosphosilicate glass.
  • FIG. 6 is a cross-sectional structural diagram of a power MOSFET device according to the embodiment.
  • FIG. 6 corresponds to a power MOSFET device provided by the present disclosure.
  • the power MOSFEET device shown in FIG. 3 is used, and the body contact diode is used.
  • an n-type polysilicon layer 57 is formed over the p-type body region 33, and the n-type polysilicon layer 57 is a conductive layer located above the p-type body region contact region 38, whereby the p-type body region contacts
  • the region 38 and the n-type polysilicon layer 57 form a silicon-based body contact diode structure in which the n-type polysilicon layer 57 is the cathode of the body contact diode and the p-body contact region 38 is the anode of the body contact diode.
  • the n-type polysilicon layer 57 can be directly in contact with the second gate 36b, the first n-type source region 34a, and the second n-type source region 34b, and then the n-type polysilicon layer 57 is externally connected to the source voltage through the source metal contact layer 47. As shown in Figure 6.
  • the n-type polysilicon layer 57 may also be in direct contact connection with the first n-type source region 34a and the second n-type source region 34b, and the second gate 36b and the n-type polysilicon layer 57 are connected by a source metal contact layer, and then the source.
  • the metal contact layer is externally connected to the source voltage.
  • the n-type polysilicon layer 57 is in direct contact connection with the second gate 36b, the first n-type source region 34a, and the second n-type source region 34b, and then the n-type polysilicon layer 57 passes through the source metal contact layer 47.
  • the source voltage is externally connected, whereby the second gate 36b controls the opening and closing of the second current channel near the side of the second n-type source region 34b by the source voltage.
  • the first gate electrode 36a externally connects the gate voltage through the gate metal contact layer (based on the positional relationship of the cross section, the gate metal contact layer is not shown in FIG. 6), whereby the first gate electrode 36a controls the approach by the gate voltage.
  • the first current channel on one side of the first n-type source region 34a is turned on and off.
  • the source metal contact layer 47 and the gate metal contact layer are separated by an interlayer insulating layer 50.
  • the interlayer insulating layer 50 is usually a material such as silicon glass, borophosphosilicate glass or phosphosilicate glass.
  • FIG. 7 is a cross-sectional structural diagram of a power MOSFET device according to the embodiment.
  • the power MOSFET device of the present embodiment includes an n-type drain region 31 and an n-type drift region 30 over the n-type drain region 31, and a p-type columnar epitaxial doping is also formed in the n-type drift region 30.
  • the impurity region 32 (only two columnar epitaxial doping regions 32 are exemplarily shown in FIG. 7 , the number of which can be set according to actual product requirements), the doping impurities and adjacent of the p-type columnar epitaxial doping region 32
  • the doping impurities in the n-type drift region 30 form a charge balance, thereby forming a super junction structure.
  • a parasitic body diode structure in the power MOSFET device is formed between the p-type body region 33 and the n-type drift region 30, wherein the p-type body region 33 is the anode of the body diode and the n-type drift region is the cathode of the body diode.
  • the power MOSFET device provided in this embodiment further includes a p-type body region contact region 38, an n-type doping region 39, a first n-type source region 34a and a second n-type source region 34b, which are located in the p-type body region 33, p
  • the body region contact region 38 and the n-type doping region 39 are both disposed between the first n-type source region 34a and the second n-type source region 34b, and the n-type doping region 39 is located above the p-type body region contact region 38.
  • the n-type doping region 39 is a conductive layer located above the p-type body region contact region 38, whereby the n-type doping region 39 and the p-type body region contact region 39 form a silicon-based body region contact diode structure.
  • the n-type doped region 39 is the cathode of the body contact diode
  • the p-type body contact region 38 is the anode of the body contact diode, so that the anode of the body contact diode is connected to the anode of the body diode.
  • the power MOSFET device provided in this embodiment further includes a first current channel located in the p-type body region 33 and interposed between the first n-type source region 34a and the n-type drift region 30, covering the first current channel.
  • the gate dielectric layer 35 and the first gate 36a, the first gate 36a is a control gate and controls the opening and closing of the first current channel by a gate voltage.
  • the power MOSFET device provided in this embodiment further includes a second current channel located in the p-type body region 33 and interposed between the second n-type source region 34b and the n-type drift region 30, covering the second current channel.
  • the turn-on voltage of the second current channel is lower than the turn-on voltage of the first current channel.
  • the second gate 36b, the first n-type source region 34a, the second n-type source region 34b and the n-type doping region 39 are electrically connected and connected to the source voltage.
  • the n-type doping region 39 is connected to the first n-type source region 34a, the second n-type source region 34b, and the second gate 36b through the source metal contact layer 47.
  • the source metal contact layer 47 is externally connected to the source voltage, whereby the second gate 36b controls the turn-on and turn-off of the second current channel by the source voltage.
  • the first gate electrode 36a externally connects the gate voltage through the gate metal contact layer (based on the positional relationship of the cross section, the gate metal contact layer is not shown in FIG.
  • the source metal contact layer 47 and the gate metal contact layer are separated by an interlayer insulating layer 50.
  • the interlayer insulating layer 50 is usually a material such as silicon glass, borophosphosilicate glass or phosphosilicate glass.
  • Vf represents the voltage applied to the body diode (i.e., the source-drain voltage Vsd of the power MOSFET device)
  • I(A) represents the reverse current flowing through the body diode.
  • the related art power MOSFET device without body contact diode is turned off, and the reverse current I(A) flowing through the body diode is rapidly increased after applying the source/drain voltage, and the power of this embodiment is increased.
  • the body contact diode since the body contact diode is in a negative bias state, substantially no reverse current flows through the body diode, and the reverse current flowing through the body diode is quickly generated only when the body contact diode is reversely broken down. Increase.
  • the source-drain voltage of the power MOSFET device of this embodiment does not cause reverse breakdown of the body contact diode when the power MOSFET device is turned off. Therefore, when the power MOSFET device of this embodiment is turned off, substantially no reverse current flows through the body diode. Therefore, the small subcarriers in the body diode of the power MOSFET device can be greatly reduced, thereby greatly reducing the reverse recovery charge and reverse recovery time of the power MOSFET device, enabling the power MOSFET device to achieve fast reverse recovery.
  • FIG. 9 is a test comparison diagram of a reverse recovery curve of a power MOSFET device of the present embodiment and a related art power MOSFET device having no body contact diode.
  • curve 3 represents a reverse recovery curve of a power MOSFET device having no body contact diode in the related art
  • curve 4 represents a reverse recovery curve of the power MOSFET device having a body contact diode of the present embodiment.
  • the power MOSFET device having the body contact diode of the present embodiment has a faster reverse recovery speed than the related art power MOSFET device having no body contact diode.

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Abstract

一种功率MOSFET器件，包括源极、漏极、第一栅极、第二栅极、体二极管和体区接触二极管，所述源极、漏极、第一栅极构成第一MOSFET结构，所述源极、漏极、第二栅极构成第二MOSFET结构，所述体二极管的阴极与所述漏极连接，所述体区接触二极管的阳极与所述体二极管的阳极连接，所述体区接触二极管的阴极与所述源极连接，所述第一栅极通过栅极电压来控制所述第一MOSFET结构的开启和关断，所述第二栅极与所述源极连接，所述第二栅极通过源极电压来控制所述第二MOSFET结构的开启和关断。

Description

功率MOSFET器件
本公开要求申请日为2017年11月1日、申请号为201711058204.0，以及申请日为2017年11月1日、申请号201711058065.1的中国专利申请的优先权，上述申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体功率器件技术领域，例如涉及一种功率MOSFET器件。
背景技术
相关技术的功率金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)器件的等效电路如图1所示，包括漏极101、源极102、栅极103、和体二极管104，其中，体二极管104是功率MOSFET器件中的本征寄生结构。功率MOSFET器件的栅极通过栅极电压来控制功率MOSFET器件的电流沟道的开启和关断，功率MOSFET器件工作机理是：1)当栅源电压Vgs小于功率MOSFET器件的阈值电压Vth，漏源电压Vds大于0V时，功率MOSFET器件处于关断状态；2)当栅源电压Vgs大于功率MOSFET器件的阈值电压Vth，漏源电压Vds大于0V时，功率MOSFET器件正向开启，此时电流从漏极经栅极处的电流沟道流到源极。功率MOSFET器件在关断时，当漏源电压Vds小于0V时，功率MOSFET器件的体二极管处于正偏压状态，反向电流从源极经体二极管流至漏极，此时体二极管的电流存在注入少子载流子现象，而这些少子载流子在功率MOSFET器件再一次开启时进行反向恢复，导致功率MOSFET器件有较大的反向恢复电流，反向恢复时间长。 在包含半桥式电路、全桥式电路、LLC谐振电路等的电源系统以及电机控制系统中，功率MOSFET器件中寄生的体二极管会经历少子载流子反向恢复的过程。少子载流子产生的反向恢复电流会导致功率MOSFET器件的损耗增加，降低了系统的效率，同时也容易引起上下晶体管直通烧坏器件，影响功率MOSFET器件的安全工作。
相关技术中，提高功率MOSFET器件的反向恢复速度的方法包括以下几种：(1)反向并联快恢复二极管，该方法的缺点是封装体积变大，制造成本大幅增加；(2)集成肖特基体二极管，该方法的缺点是耐压低、漏电流大，并且功耗增加；(3)采用寿命控制技术，如：电子辐照、粒子辐照(质子、α粒子)、深能级复合中心等，该方法的缺点是工艺难度提高、制造成本上升，同时器件漏电流和导通电阻变大，功耗增加。
发明内容
本公开提供一种具有快速反向恢复功能的功率MOSFET器件，以解决相关技术中的功率MOSFET器件因少子载流子注入问题造成的反向恢复时间较长的问题。
一种功率MOSFET器件，包括源极、漏极、第一栅极、第二栅极、体二极管和体区接触二极管，所述源极、漏极、第一栅极构成第一MOSFET结构，所述源极、漏极、第二栅极构成第二MOSFET结构，所述体二极管的阴极与所述漏极连接，所述体区接触二极管的阳极与所述体二极管的阳极连接，所述体区接触二极管的阴极与所述源极连接，所述第一栅极通过栅极电压来控制所述第一MOSFET结构的开启和关断，所述第二栅极与所述源极连接，所述第二栅极通过源极电压来控制所述第二MOSFET结构的开启和关断。
在一实施例中，所述第一MOSFET结构的阈值电压大于所述第二MOSFET结构的阈值电压。
在一实施例中所述功率MOSFET器件，包括：n型漏区以及位于所述n型漏区之上的n型漂移区，所述n型漂移区内设有p型体区，所述p型体区内设有p型体区接触区、第一n型源区和第二n型源区；位于所述p型体区接触区之上的导电层，所述导电层与所述p型体区接触区形成所述体区接触二极管，其中所述导电层为所述体区接触二极管的阴极，所述p型体区接触区为所述体区接触二极管的阳极；位于所述p型体区内且介于所述第一n型源区和所述n型漂移区之间的第一电流沟道，覆盖所述第一电流沟道的栅介质层和所述第一栅极，所述第一栅极通过栅极电压来控制所述第一电流沟道的开启和关断；位于所述p型体区内且介于所述第二n型源区和所述n型漂移区之间的第二电流沟道，覆盖所述第二电流沟道的栅介质层和所述第二栅极，所述第二栅极、所述第一n型源区、所述第二n型源区和所述导电层之间电性连接并均接源极电压，所述第二栅极通过源极电压来控制所述第二电流沟道的开启和关断。
在一实施例中，所述导电层为位于所述p型体区之上的源极金属接触层，所述p型体区接触区的掺杂浓度低于所述p型体区的掺杂浓度的最大峰值，所述p型体区接触区与所述源极金属接触层形成肖特基势垒二极管结构。
在一实施例中，所述第二栅极通过所述源极金属接触层与所述第一n型源区和所述第二n型源区连接，所述源极金属接触层外接源极电压。
在一实施例中，所述导电层为位于所述p型体区之上的n型多晶硅层，所述n型多晶硅层与所述p型体区接触区形成硅基的体区接触二极管结构。
在一实施例中，所述n型多晶硅层与所述第二栅极、所述第一n型源区和所述第二n型源区直接连接，所述n型多晶硅层通过源极金属接触层外接源极电压。
在一实施例中，所述第二栅极通过源极金属接触层与所述n型多晶硅层连接，所述源极金属接触层外接源极电压。
在一实施例中，所述导电层为位于所述p型体区接触区内的n型掺杂区，所述n型掺杂区设于所述第一n型源区和第二n型源区之间，所述n型掺杂区与所述p型体区接触区形成硅基的体区接触二极管结构。
在一实施例中，所述第二栅极通过源极金属接触层与所述第一n型源区、所述第二n型源区和所述n型掺杂区连接，所述源极金属接触层外接源极电压。
在一实施例中，所述第一电流沟道的开启电压大于所述第二电流沟道的开启电压。
在一实施例中，所述功率MOSFET器件还包括位于p型体区下方的p型柱状外延掺杂区，所述p型柱状外延掺杂区的掺杂杂质和相邻的所述n型漂移区内的掺杂杂质形成电荷平衡，以形成超结结构。
本公开提供的功率MOSFET器件在关断时，当源漏电压大于0V时，体区接触二极管处于负偏压状态，因此能够大幅降低流经体二极管的反向电流，从而能够大幅减少体二极管内的少子载流子，进而能够减少功率MOSFET器件的反向恢复电荷和反向恢复时间，使得功率MOSFET器件能够实现快速的反向恢复功能；同时当源漏电压达到第二MOSFET结构的阈值电压时，第二MOSFET结构的第二电流沟道开启，反向电流会由源极经第二MOSFET结构的第二电流沟道流至漏极。
附图说明
为了说明本实施例的技术方案，下面对描述实施例中所需要用到的附图进行介绍。
图1是相关技术的功率MOSFET器件的等效电路示意图；
图2是一实施例提供的一种功率MOSFET器件的等效电路示意图；
图3是一实施例提供的一种功率MOSFET器件的剖面结构示意图；
图4是一实施例提供的一种功率MOSFET器件的俯视结构示意图；
图5是图4所示的功率MOSFET器件沿AA方向的剖面结构示意图；
图6是一实施例提供的一种功率MOSFET器件的剖面结构示意图；
图7是一实施例提供的一种功率MOSFET器件的剖面结构示意图；
图8是一实施例提供的一种功率MOSFET器件与相关技术的功率MOSFET器件的Vf曲线的测试对比图；
图9是一实施例提供的一种功率MOSFET器件与相关技术的功率MOSFET器件的反向恢复曲线的测试对比图。
具体实施方式
以下将结合本实施例中的附图，通过具体实施方式描述本公开。
本实施例所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为说明本公开的具体实施方式，说明书附图中所列示意图，放大了本公开所述的层和区域的厚度，且所列图形大小并不代表实际尺寸；说明书附图是示意性的。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
功率MOSFET器件包括元胞区和终端区，其中，元胞区用于获得低导通电阻，终端区用于提高元胞区中最边缘的元胞的耐压。终端区是功率MOSFET器件中的通用结构，根据不同产品的要求有不同的设计结构，在本实施例中不再 展示和描述功率MOSFET器件的终端区的结构。本实施例中所述的MOSFET器件指的是功率MOSFET器件中元胞区的结构。
图2所示为本实施例提供的一种功率MOSFET器件的一个实施例的等效电路示意图。如图2所示，本实施例提供的功率MOSFET器件包括漏极301、源极302、第一栅极303a、第二栅极303b、体二极管304和体区接触二极管305，第二栅极303b与源极302连接，体区接触二极管305可以为硅基二极管或者为肖特基势垒二极管，且体二极管304的阴极与漏极301连接，体区接触二极管305的阳极与体二极管304的阳极连接，体区接触二极管305的阴极与源极302连接。本实施例提供的功率MOSFET器件中，漏极301、源极302、第一栅极303a构成第一MOSFET结构，第一栅极303a通过栅极电压来控制第一MOSFET结构的第一电流沟道的开启和关断；功率MOSFET器件的漏极301、源极302、第二栅极303b构成第二MOSFET结构，第二栅极303b与源极302连接，从而第二栅极303b通过源极电压来控制第二MOSFET结构的第二电流沟道的开启和关断。在一实施例中，第一MOSFET结构的阈值电压大于第二MOSFET结构的阈值电压。
图2所示的功率MOSFET器件的工作机理是：1)当栅源电压Vgs小于第一MOSFET结构的阈值电压Vth1，漏源电压Vds大于0V时，该功率MOSFET器件处于关断状态；2)当栅源电压Vgs达到第一MOSFET结构的阈值电压Vth1，漏源电压Vds大于0V时，该功率MOSFET器件正向开启，此时第一MOSFET结构的第一电流沟道开启，电流从漏极经第一电流沟道流到源极，而第二MOSFET结构的第二电流沟道处于关断状态而没有电流流过。功率MOSFET器件在关断时：当源极电压大于漏极电压时，体区接触二极管305处于负偏压状态，因此能够大幅度降低流经体二极管的反向电流，从而能够大幅降低体二极 管内的少子载流子，进而能够大幅降低功率MOSFET器件的反向恢复电荷和反向恢复时间，使得功率MOSFET器件能够实现快速的反向恢复功能；同时，当源漏电压Vsd达到第二MOSFET结构的阈值电压Vth2时，第二MOSFET结构的第二电流沟道处于开启状态，从而使反向电流由源极302经第二MOSFET结构的第二电流沟道流至漏极301。
图3是本实施例的一种功率MOSFET器件的剖面结构示意图，如图3所示，功率MOSFET器件包括n型漏区31和位于n型漏区31之上的n型漂移区30，在n型漂移区30内还形成有p型柱状外延掺杂区32(图3中仅示例性的示出了两个p型柱状外延掺杂区32结构，其数量依据实际产品要求设定)，p型柱状外延掺杂区32的掺杂杂质和相邻的n型漂移区30内的掺杂杂质形成电荷平衡，从而形成超结结构。在p型柱状外延掺杂区32的顶部形成有p型体区33，即p型柱状外延掺杂区32位于p型体区33的下方。
在形成本实施例的功率MOSFET器件时，也可以不形成位于p型体区33的下方的p型柱状掺杂区32，此时，本实施例的功率MOSFET器件是不采用超结结构的功率MOSFET器件，即传统结构的功率MOSFET器件。
本实施例提供的功率MOSFET器件中，在p型体区33内形成有p型体区接触区38、第一n型源区34a和第二n型源区34b，p型体区接触区38通常设置于第一n型源区34a和第二n型源区34b之间。
p型体区33与n型漂移区30之间形成功率MOSFET器件中寄生的体二极管结构，其中，p型体区33为该体二极管的阳极，n型漂移区为该体二极管的阴极。
本实施例提供的功率MOSFET器件还包括位于p型体区33内且介于第一n型源区34a和n型漂移区30之间的第一电流沟道，覆盖该第一电流沟道的栅介 质层35和第一栅极36a，第一栅极36a是控制栅极并通过栅极电压来控制第一电流沟道的开启和关断。位于p型体区33内且介于第二n型源区34b和n型漂移区30之间的第二电流沟道，覆盖该第二电流沟道的栅介质层35和第二栅极36b。
在一实施例中，第二电流沟道的开启电压低于第一电流沟道的开启电压。
电流沟道是MOSFET结构中当施加栅极电压时在半导体表面形成的积累层及反型层，在本实施例附图中，功率MOSFET器件中的第一电流沟道和第二电流沟道均未示出。
本实施例提供的功率MOSFET器件还包括位于p型体区接触区38之上的导电层37，导电层37与p型体区接触区38形成体区接触二极管结构，其中导电层37为该体区接触二极管的阴极，p型体区接触区38为该体区接触二极管的阳极，从而体区接触二极管的阳极与体二极管的阳极连接。在一实施例中，导电层37可以为n型多晶硅层，也可以为金属层，由此体区接触二极管可以是硅基的体区接触二极管，也可以是肖特基势垒二极管。
第二栅极36b、第一n型源区34a、第二n型源区34b与导电层37之间电性连接并均接源极电压，从而，第二栅极36b通过源极电压来控制第二电流沟道的开启和关断。
在图3所示的功率MOSFET器件中，导电层37与第一n型源区34a、第二n型源区34b直接接触连接，因此只需要再将导电层37与第二栅极36b电性连接即可。
图4是本实施例提供的一种功率MOSFET器件的俯视结构示意图，其中，图4并不是俯视图，图4只是从俯视的角度示出了本实施例的功率MOSFET器件中部分结构的位置关系。图5是图4所示的功率MOSFET器件沿AA方向的 剖面结构示意图，图5中仅示例性的示出了两个柱状外延掺杂区32结构。图4和图5对应的是本公开提供的一种功率MOSFET器件在图3所示的功率MOSFEET器件的基础上，体区接触二极管采用肖特基势垒二极管的一个实施例。如图4和图5所示，在p型体区33之上形成有源极金属接触层47，源极金属接触层47即为位于p型体区接触区38之上的导电层，此时，p型体区接触区38的掺杂浓度需要低于p型体区33的掺杂浓度的最大峰值，由此p型体区接触区38和源极金属接触层47形成肖特基势垒二极管结构，其中，源极金属接触层47为该体区接触二极管的阴极，p型体区接触区38为该体区接触二极管的阳极。图4中只示例性的示出了源极金属接触孔中的源极金属接触层的位置。源极金属接触层47与第二栅极36b、第一n型源区34a、第二n型源区34b直接连接，源极金属接触层47外接源极电压，由此第二栅极36b通过源极电压来控制靠近第二n型源区34b一侧的第二电流沟道的开启和关断。第一栅极36a通过栅极金属接触层74外接栅极电压，由此第一栅极36a通过栅极电压来控制靠近第一n型源区34a一侧的第一电流沟道的开启和关断。源极金属接触层47与栅极金属接触层74之间由层间绝缘层50隔离，层间绝缘层50通常为硅玻璃、硼磷硅玻璃或磷硅玻璃等材料。
图6是本实施例提供的一种功率MOSFET器件的剖面结构示意图，图6对应的是本公开提供的一种功率MOSFET器件在图3所示的功率MOSFEET器件的基础上，体区接触二极管采用硅基二极管的一个实施例。如图6所示，在p型体区33之上形成有n型多晶硅层57，n型多晶硅层57即为位于p型体区接触区38之上的导电层，由此p型体区接触区38和n型多晶硅层57形成硅基的体区接触二极管结构，其中，n型多晶硅层57为该体区接触二极管的阴极，p型体区接触区38为该体区接触二极管的阳极。n型多晶硅层57可以与第二栅极 36b、第一n型源区34a、第二n型源区34b直接接触连接，然后n型多晶硅层57通过源极金属接触层47外接源极电压，如图6所示。n型多晶硅层57也可以与第一n型源区34a、第二n型源区34b直接接触连接，第二栅极36b与n型多晶硅层57之间通过源极金属接触层连接，然后源极金属接触层外接源极电压。在该实施例中，n型多晶硅层57与第二栅极36b、第一n型源区34a、第二n型源区34b直接接触连接，然后n型多晶硅层57通过源极金属接触层47外接源极电压，由此第二栅极36b通过源极电压来控制靠近第二n型源区34b一侧的第二电流沟道的开启和关断。第一栅极36a通过栅极金属接触层(基于剖面的位置关系，栅极金属接触层在图6中未示出)外接栅极电压，由此第一栅极36a通过栅极电压来控制靠近第一n型源区34a一侧的第一电流沟道的开启和关断。源极金属接触层47与栅极金属接触层之间由层间绝缘层50隔离，层间绝缘层50通常为硅玻璃、硼磷硅玻璃或磷硅玻璃等材料。
图7是本实施例提供的一种功率MOSFET器件的剖面结构示意图。如图7所示，本实施例的功率MOSFET器件包括n型漏区31和位于n型漏区31之上的n型漂移区30，在n型漂移区30内还形成有p型柱状外延掺杂区32(图7中仅示例性的示出了两个柱状外延掺杂区32结构，其数量可根据实际产品要求设定)，p型柱状外延掺杂区32的掺杂杂质和相邻的n型漂移区30内的掺杂杂质形成电荷平衡，从而形成超结结构。
p型体区33与n型漂移区30之间形成功率MOSFET器件中寄生的体二极管结构，其中，p型体区33为该体二极管的阳极，n型漂移区为该体二极管的阴极。
本实施例提供的功率MOSFET器件还包括位于p型体区33内的p型体区接触区38、n型掺杂区39、第一n型源区34a和第二n型源区34b，p型体区接 触区38和n型掺杂区39均设于第一n型源区34a和第二n型源区34b之间，n型掺杂区39位于p型体区接触区38之上，n型掺杂区39即为位于p型体区接触区38之上的导电层，由此，n型掺杂区39与p型体区接触区39形成硅基的体区接触二极管结构，其中，n型掺杂区39为该体区接触二极管的阴极，p型体区接触区38为该体区接触二极管的阳极，从而体区接触二极管的阳极与体二极管的阳极连接。
本实施例提供的功率MOSFET器件还包括位于p型体区33内且介于第一n型源区34a和n型漂移区30之间的第一电流沟道，覆盖该第一电流沟道的栅介质层35和第一栅极36a，第一栅极36a是控制栅极并通过栅极电压来控制该第一电流沟道的开启和关断。
本实施例提供的功率MOSFET器件还包括位于p型体区33内且介于第二n型源区34b和n型漂移区30之间的第二电流沟道，覆盖该第二电流沟道的栅介质层35和第二栅极36b。
在一实施例中，第二电流沟道的开启电压低于第一电流沟道的开启电压。
第二栅极36b、第一n型源区34a、第二n型源区34b与n型掺杂区39之间电性连接并均接源极电压。在图7所示的功率MOSFET器件中，n型掺杂区39与第一n型源区34a、第二n型源区34b、第二栅极36b之间通过源极金属接触层47连接，源极金属接触层47外接源极电压，由此第二栅极36b通过源极电压来控制第二电流沟道的开启和关断。第一栅极36a通过栅极金属接触层(基于剖面的位置关系，栅极金属接触层在图7中未示出)外接栅极电压，由此第一栅极36a通过栅极电压来控制第一电流沟道的开启和关断。源极金属接触层47与栅极金属接触层之间由层间绝缘层50隔离，层间绝缘层50通常为硅玻璃、硼磷硅玻璃或磷硅玻璃等材料。
图8是本实施例的一种功率MOSFET器件与现有技术的没有体区接触二极管的功率MOSFET器件的Vf曲线的测试对比图。如图8所示，曲线1表示相关技术中没有体区接触二极管的功率MOSFET器件的正向电压Vf曲线测试图，曲线2表示本实施例的具有体区接触二极管的功率MOSFET器件的Vf曲线测试图，其中Vf表示施加在体二极管上的电压(即功率MOSFET器件的源漏电压Vsd)，I(A)表示流过体二极管的反向电流。由图8可知，相关技术的没有体区接触二极管的功率MOSFET器件在关断时，施加源漏电压后，流过体二极管的反向电流I(A)迅速增大，而本实施例的功率MOSFET器件，由于体区接触二极管处于负偏压状态，因此基本没有反向电流流过体二极管，只有当体区接触二极管被反向击穿后，才会使流过体二极管的反向电流迅速增大。本实施例的功率MOSFET器件在关断时的源漏电压不会造成体区接触二极管反向击穿，因此本实施例的功率MOSFET器件在关断时，基本没有反向电流流过体二极管，因此能够大幅度降低功率MOSFET器件的体二极管内的少子载流子，进而能够大幅度降低功率MOSFET器件的反向恢复电荷和反向恢复时间，使得功率MOSFET器件能够实现快速的反向恢复功能。
图9是本实施例的一种功率MOSFET器件与相关技术的没有体区接触二极管的功率MOSFET器件的反向恢复曲线的测试对比图。如图9所示，曲线3表示相关技术中没有体区接触二极管的功率MOSFET器件的反向恢复曲线图，曲线4表示本实施例的具有体区接触二极管的功率MOSFET器件的反向恢复曲线图。由图9可知，本实施例的具有体区接触二极管的功率MOSFET器件与相关技术的没有体区接触二极管的功率MOSFET器件相比具有更快的反向恢复速度。

Claims (11)

  1. 一种功率金属氧化物半导体场效应晶体管MOSFET器件，包括源极、漏极、第一栅极、第二栅极、体二极管和体区接触二极管，所述源极、漏极、第一栅极构成第一MOSFET结构，所述源极、漏极、第二栅极构成第二MOSFET结构，所述体二极管的阴极与所述漏极连接，所述体区接触二极管的阳极与所述体二极管的阳极连接，所述体区接触二极管的阴极与所述源极连接，所述第一栅极通过栅极电压来控制所述第一MOSFET结构的开启和关断，所述第二栅极与所述源极连接，所述第二栅极通过源极电压来控制所述第二MOSFET结构的开启和关断。
  2. 如权利要求1所述的功率MOSFET器件，其中，所述第一MOSFET结构的阈值电压大于所述第二MOSFET结构的阈值电压。
  3. 如权利要求1所述的功率MOSFET器件，包括：
    n型漏区以及位于所述n型漏区之上的n型漂移区，所述n型漂移区内设有p型体区，所述p型体区内设有p型体区接触区、第一n型源区和第二n型源区；
    位于所述p型体区接触区之上的导电层，所述导电层与所述p型体区接触区形成所述体区接触二极管，其中所述导电层为所述体区接触二极管的阴极，所述p型体区接触区为所述体区接触二极管的阳极；
    位于所述p型体区内且介于所述第一n型源区和所述n型漂移区之间的第一电流沟道，覆盖所述第一电流沟道的栅介质层和所述第一栅极，所述第一栅极通过栅极电压来控制所述第一电流沟道的开启和关断；
    位于所述p型体区内且介于所述第二n型源区和所述n型漂移区之间的第二电流沟道，覆盖所述第二电流沟道的栅介质层和所述第二栅极，所述第二栅极、所述第一n型源区、所述第二n型源区和所述导电层之间电性连接并均接源极电压，所述第二栅极通过源极电压来控制所述第二电流沟道的开启和关断。
  4. 如权利要求3所述的功率MOSFET器件，其中，所述导电层为位于所 述p型体区之上的源极金属接触层，所述p型体区接触区的掺杂浓度低于所述p型体区的掺杂浓度的最大峰值，所述p型体区接触区与所述源极金属接触层形成肖特基势垒二极管结构。
  5. 如权利要求4所述的功率MOSFET器件，其中，所述第二栅极通过所述源极金属接触层与所述第一n型源区和所述第二n型源区连接，所述源极金属接触层外接源极电压。
  6. 如权利要求3所述的功率MOSFET器件，其中，所述导电层为位于所述p型体区之上的n型多晶硅层，所述n型多晶硅层与所述p型体区接触区形成硅基的体区接触二极管结构。
  7. 如权利要求6所述的功率MOSFET器件，其中，所述n型多晶硅层与所述第二栅极、所述第一n型源区和所述第二n型源区直接连接，所述n型多晶硅层通过源极金属接触层外接源极电压。
  8. 如权利要求3所述的功率MOSFET器件，其中，所述导电层为位于所述p型体区内的n型掺杂区，所述n型掺杂区与所述p型体区接触区形成硅基的体区接触二极管结构。
  9. 如权利要求8所述的功率MOSFET器件，其中，所述第二栅极通过源极金属接触层与所述第一n型源区、所述第二n型源区和所述n型掺杂区连接，所述源极金属接触层外接源极电压。
  10. 如权利要求3所述的功率MOSFET器件，其中，所述第一电流沟道的开启电压大于所述第二电流沟道的开启电压。
  11. 如权利要求3所述的功率MOSFET器件，还包括位于p型体区下方的p型柱状外延掺杂区，所述p型柱状外延掺杂区的掺杂杂质和相邻的所述n型漂移区内的掺杂杂质形成电荷平衡，以形成超结结构。
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