WO2021103094A1 - 超结功率器件 - Google Patents

超结功率器件 Download PDF

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Publication number
WO2021103094A1
WO2021103094A1 PCT/CN2019/123318 CN2019123318W WO2021103094A1 WO 2021103094 A1 WO2021103094 A1 WO 2021103094A1 CN 2019123318 W CN2019123318 W CN 2019123318W WO 2021103094 A1 WO2021103094 A1 WO 2021103094A1
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type
gate
power device
region
super junction
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PCT/CN2019/123318
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English (en)
French (fr)
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龚轶
袁愿林
刘伟
刘磊
毛振东
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苏州东微半导体有限公司
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Priority to KR1020227000422A priority Critical patent/KR102717550B1/ko
Publication of WO2021103094A1 publication Critical patent/WO2021103094A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Definitions

  • This application belongs to the technical field of semiconductor super junction power devices, for example, relates to a semiconductor super junction power device with fast reverse recovery speed and small chip size.
  • the cross-sectional structure of a related art semiconductor super junction power device is shown in FIG. 1, including: n-type drain region 50, n-type drain region 50 is connected to the drain voltage through drain contact metal layer 58; located in n-type drain region 50
  • the upper n-type drift region 51, the p-type body region 52 on the top of the n-type drift region 51, the n-type source region 53 in the p-type body region 52, the n-type source region 53 and the p-type body region 52 pass through the source
  • the electrode contact metal layer 57 is connected to the source voltage; the p-type columnar doped region 59 located below the p-type body region; the current in the p-type body region 52 and between the n-type source region 53 and the n-type drift region 51 A channel, and a gate structure that controls the on and off of the current channel.
  • the gate structure includes a gate dielectric layer 54 and a gate 55.
  • the reverse current will flow through the parasitic body diode in the semiconductor super junction power device.
  • the body diode current has the phenomenon of injecting minority carrier carriers, and these minority carrier carriers Reverse recovery is performed when the semiconductor super junction power device is turned on again, resulting in a larger reverse recovery current and a long reverse recovery time.
  • life control technologies such as electron irradiation, deep-level recombination centers, etc. are usually used to improve the reverse recovery speed of semiconductor super-junction power devices.
  • the disadvantages of this method are that the process is difficult, the manufacturing cost is expensive, and the semiconductor superjunction cannot be accurately controlled. Reverse recovery speed of junction power device.
  • This application provides a super junction power device with a fast reverse recovery speed to solve the technical problem of long reverse recovery time caused by the minority carrier injection problem of the super junction power device in the related art.
  • An n-type drain region, an n-type drift region located above the n-type drain region, a plurality of p-type columnar doped regions located in the n-type drift region, located between each of the p-type columnar doped regions The upper p-type body region, and at least one first MOSFET unit and at least one second MOSFET unit;
  • the first MOSFET unit includes: a first n-type source region located in the p-type body region; a first gate structure located on the p-type body region, the first gate structure including a first A gate dielectric layer and a first gate and an n-type floating gate located on the first gate dielectric layer, and in the lateral direction, the n-type floating gate is located on a side close to the n-type drift region, the The first gate is located on a side close to the first n-type source region and extends above the n-type floating gate.
  • the first gate acts on the n-type floating gate through capacitive coupling; An opening in the first gate dielectric layer, the n-type floating gate contacts the p-type body region through the opening to form a pn junction diode;
  • the second MOSFET unit includes: a second n-type source region located in the p-type body region for controlling a current channel between the second n-type source region and the n-type drift region
  • the second gate structure is turned on and off, and the second gate structure includes a second gate dielectric layer and a second gate.
  • the second MOSFET unit further includes a gate trench recessed in the n-type drift region, and the second gate dielectric layer and the second gate are located Inside the gate trench.
  • the first n-type source region and the second n-type source region are located in the same p-type body region.
  • the first n-type source region and the second n-type source region are located in two different p-type body regions.
  • the first gate extends above the n-type floating gate and covers the sidewall of the n-type floating gate close to the n-type drift region .
  • the first MOSFET unit When a super-junction power device provided by an embodiment of the present invention is reverse-conducting, the first MOSFET unit has a low threshold voltage, so that the first MOSFET unit is turned on at a low gate voltage (or 0V voltage), thereby increasing current flow.
  • the second MOSFET unit By passing the reverse current of the first MOSFET unit, the current flowing through the parasitic body diode in the super junction power device can be reduced, and the reverse recovery speed of the super junction power device can be improved.
  • the second MOSFET unit has a shorter current channel than the first MOSFET unit, and is used to control the chip size of the super junction power device, so that the super junction power device has a fast reverse recovery speed and a small chip size.
  • Figure 1 is a schematic diagram of an equivalent circuit of a related art super junction power device
  • FIG. 2 is a schematic cross-sectional structure diagram of a first embodiment of a super junction power device provided by the present application
  • FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a super junction power device provided by the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a third embodiment of a super junction power device provided by the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a first embodiment of a super junction power device provided by the present application.
  • a super junction power device provided by an embodiment of the present invention includes an n-type drain region 20 located in The n-type drift region 21 above the n-type drain region 20, a plurality of p-type columnar doped regions 29 located in the n-type drift region, only two p-type columnar doped regions 29 are exemplarily shown in FIG.
  • a charge balance is formed between the first p-type columnar doped region 29 and the adjacent n-type drift region 21 to improve the withstand voltage of the super junction power device; the p-type doped region above each p-type columnar doped region 29
  • the type body region 22, and at least one first MOSFET cell 200 and at least one second MOSFET cell 300, only one first MOSFET cell 200 and one second MOSFET cell 300 are exemplarily shown in FIG. 2.
  • the first MOSFET unit 200 of the embodiment of the present invention includes: a first n-type source region 23 located in a p-type body region 22; a first gate structure located on the p-type body region 22, and the first gate structure includes The first gate dielectric layer 24, the n-type floating gate 25 and the first gate 26, the first gate 26 and the n-type floating gate 25 are located on the first gate dielectric layer 24, and in the lateral direction, the n-type floating gate 25 Located on the side close to the n-type drift region 21, the first gate 26 is located on the side close to the first n-type source region 23 and extends above the n-type floating gate 25, the first gate 26 and the n-type floating gate 25 Isolated by the insulating dielectric layer 27, the first gate 26 acts on the n-type floating gate 25 through capacitive coupling.
  • the insulating dielectric layer 27 is usually silicon dioxide.
  • An opening 28 is formed in the first gate dielectric layer 24 under the n-type floating gate 25, and the opening 28 of the n-type floating gate 25 contacts the p-type body region 22 to form a p-n junction diode.
  • the second MOSFET cell 300 of the embodiment of the present invention includes a second n-type source region 33 located in the p-type body region 22.
  • the first n-type source region 23 of the first MOSFET cell 200 and the second n-type source region 33 of the second MOSFET cell 300 are formed in two different p-type body regions 22;
  • the second gate dielectric layer 34 and the second gate 36 located on the second gate dielectric layer 34, the second gate 36 can control the current channel of the second MOSFET unit 300 through the gate voltage (that is, between the second n
  • the current channel between the n-type source region 33 and the n-type drift region 21) is turned on and off.
  • the n-type floating gate 25 in the forward blocking state, a high voltage is applied to the n-type drain region 20, the pn junction diode in the first MOSFET unit 200 is forward-biased, and the n-type floating gate 25 is The positive charge is charged, which lowers the threshold voltage Vht1 of the current channel under the n-type floating gate 25.
  • the drain-source voltage Vds is greater than 0V
  • the threshold voltage Vht1 of the current channel under the n-type floating gate 25 affects the entire first MOSFET unit 200
  • the influence of the threshold voltage Vth is very low, and the first MOSFET cell 200 still has a high threshold voltage.
  • the threshold voltage Vht1 of the current channel under the n-type floating gate 25 affects the threshold voltage Vth of the entire first MOSFET unit 200 So that the first MOSFET unit 200 has a low threshold voltage Vth, so that the current channel of the first MOSFET unit 200 is turned on at a low gate voltage (or 0V voltage), so that the flow through the first MOSFET unit 200 can be increased.
  • the reverse current of the super junction power device reduces the current flowing through the parasitic body diode in the super junction power device and improves the reverse recovery speed of the super junction power device.
  • the first MOSFET unit 200 in the super-junction power device of the embodiment of the present invention is used to adjust the reverse recovery speed of the super-junction power device.
  • the first gate 26 and the n-type floating gate 25 are arranged laterally, they are affected by the first gate. Due to the limitation of the size of the opening 28 in the dielectric layer 24, the first MOSFET unit 200 has a long current channel, which will increase the size of the super junction power device chip, which is not conducive to the smaller size of the super junction power device.
  • the second MOSFET unit 300 is provided, and the second MOSFET unit 300 is not provided with an n-type floating gate structure, which can make the second MOSFET unit 300 have a shorter current channel compared with the first MOSFET unit 200. Therefore, By setting the ratio of the first MOSFET unit 200 and the second MOSFET unit 300, the chip size of the super junction power device can be effectively controlled under the premise of ensuring that the super junction power device has a fast reverse recovery speed, so that the super junction power device can be effectively controlled. Power device chips can be packaged in a smaller size.
  • the first MOSFET unit 200 and the second MOSFET unit 300 have different gate structures, in order to prevent the first MOSFET unit 200 and the second MOSFET unit 300 from having different threshold voltages, it is possible to make
  • the first gate 26 of the first MOSFET unit 200 is electrically connected to the first n-type source region 23, that is, the first gate 26 is connected to the source voltage.
  • the first MOSFET unit 200 is only used to flow reverse current.
  • the turn-on current of the super-junction power device is not provided, which can ensure the uniformity of the turn-on of the current channel of the super-junction power device.
  • FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a super junction power device provided by the present application.
  • the difference from the structure of the super junction power device described in the first embodiment of the present application shown in FIG. 2 is that the present application
  • the first n-type source region 23 and the second n-type source region 33 are formed in the same p-type body region 22.
  • the second MOSFET cell 300 also includes a gate recessed in the n-type drift region 21.
  • the trench, the second gate dielectric layer 34 and the second gate 36 are all formed in the gate trench.
  • the second MOSFET unit 300 adopting the vertical current channel structure can reduce the chip size of the super junction power device.
  • the first gate 26 of the first MOSFET unit 200 extends above the n-type floating gate 25 and covers the sidewall of the n-type floating gate 25 close to the n-type drift region 21, which can increase the first gate.
  • the pole 26 covers the area of the n-type floating gate 25, which can increase the capacitive coupling ratio of the first gate 26 to the n-type floating gate 26.

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  • Chemical & Material Sciences (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

一种超结功率器件，包括至少一个第一MOSFET单元（200）和至少一个第二MOSFET单元（300），第一MOSFET单元（200）在超结功率器件开启和关断时具有不同的阈值电压，超结功率器件在反向导通时，反向电流可以流过第一MOSFET单元（200），这提高了超结功率器件的反向恢复速度；第二MOSFET单元（300）相较于第一MOSFET（200）单元具有更短的电流沟道，可以有效控制超结功率器件的芯片尺寸。该超结功率器件在具有快的反向恢复速度的同时还具有小的芯片尺寸。

Description

超结功率器件
本公开要求在2019年11月27日提交中国专利局、申请号为201911184109.4的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请属于半导体超结功率器件技术领域，例如涉及一种反向恢复速度快且芯片尺寸小的半导体超结功率器件。
背景技术
相关技术的一种半导体超结功率器件的剖面结构如图1所示，包括：n型漏区50，n型漏区50通过漏极接触金属层58接漏极电压；位于n型漏区50之上的n型漂移区51，位于n型漂移区51顶部的p型体区52，位于p型体区52内的n型源区53，n型源区53和p型体区52通过源极接触金属层57接源极电压；位于p型体区下方的p型柱状掺杂区59；位于p型体区52内且介于n型源区53和n型漂移区51之间的电流沟道，以及控制该电流沟道开启和关断的栅极结构，该栅极结构包括栅介质层54和栅极55。
相关技术的半导体超结功率器件在关断时，反向电流会流过半导体超结功率器件内寄生的体二极管，此时体二极管的电流存在注入少子载流子现象，而这些少子载流子在半导体超结功率器件再一次开启时进行反向恢复，导致较大的反向恢复电流，反向恢复时间长。目前通常采用寿命控制技术如：电子辐照、深能级复合中心等来提高半导体超结功率器件的反向恢复速度，该方法的缺点是工艺难度高、制造成本昂贵，而且不能准确控制半导体超结功率器件的反向恢复速度。
发明内容
本申请提供一种反向恢复速度快的超结功率器件，以解决相关技术中的超结功率器件因少子载流子注入问题造成的反向恢复时间长的技术问题。
本发明实施例提供的一种超结功率器件，包括：
n型漏区，位于所述n型漏区之上的n型漂移区，位于所述n型漂移区内的多个p型柱状掺杂区，位于每个所述p型柱状掺杂区之上的p型体区，以及至少一个第一MOSFET单元和至少一个第二MOSFET单元；
所述第一MOSFET单元包括：位于所述p型体区内的第一n型源区；位于所述p型体区之上的第一栅极结构，所述第一栅极结构包括第一栅介质层以及位于所述第一栅介质层之上的第一栅极和n型浮栅，且在横向上，所述n型浮栅位于靠近所述n型漂移区的一侧，所述第一栅极位于靠近所述第一n型源区的一侧并延伸至所述n型浮栅之上，所述第一栅极通过电容耦合作用于所述n型浮栅；位于所述第一栅介质层中的一个开口，所述n型浮栅通过所述开口与所述p型体区接触形成p-n结二极管；
所述第二MOSFET单元包括：位于所述p型体区内的第二n型源区，用于控制介于所述第二n型源区和所述n型漂移区之间的电流沟道的开启和关断的第二栅极结构，所述第二栅极结构包括第二栅介质层和第二栅极。
可选的，本申请所述的超结功率器件，所述第二MOSFET单元还包括凹陷在所n型漂移区内的栅沟槽，所述第二栅介质层和所述第二栅极位于所述栅沟槽内。
可选的，本申请所述的超结功率器件，所述第一n型源区和所述第二n型源区位于同一个所述p型体区内。
可选的，本申请所述的超结功率器件，所述第一n型源区和所述第二n型源区位于两个不同的所述p型体区内。
可选的，本申请所述的超结功率器件，所述第一栅极延伸至所述n型浮栅之上且覆盖所述n型浮栅靠近所述n型漂移区一侧的侧壁。
可选的，本申请所述的超结功率器件，所述第一MOSFET单元的第一栅极与所述第一n型源区电性连接。
本发明实施例提供的一种超结功率器件在反向导通时，第一MOSFET单元具有低阈值电压，使得第一MOSFET单元在低栅极电压(或0V电压)下导通，从而能够增加流过第一MOSFET单元的反向电流，进而能够减少流过超结功率器件中寄生的体二极管的电流，提高超结功率器件的反向恢复速度。第二MOSFET单元具有比第一MOSFET单元更短的电流沟道，用于控制超结功率器件的芯片尺寸，使得超结功率器件在具有快的反向恢复速度的同时还具有小的芯片尺寸。
附图说明
下面对描述实施例中所需要用到的附图做一简单介绍。
图1是相关技术的超结功率器件的等效电路示意图；
图2是本申请提供的一种超结功率器件的第一个实施例的剖面结构示意图；
图3是本申请提供的一种超结功率器件的第二个实施例的剖面结构示意图；
图4是本申请提供的一种超结功率器件的第三个实施例的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体实施方式，完整地描述本申请的技术方案。同时，说明书附图中所列示意图，放大了本申请所述的层和区域的尺寸，且所列图形大小并不代表实际尺寸。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状如制备引起的偏差等。
图2是本申请提供的一种超结功率器件的第一个实施例的剖面结构示意图，如图2所示，本发明实施例提供的一种超结功率器件包括n型漏区20，位于n型漏区20之上的n型漂移区21，位于n型漂移区中的多个p型柱状掺杂区29，图2中仅示例性的示出了两个p型柱状掺杂区29，第一p型柱状掺杂区29与相邻的n型漂移区21之间形成电荷平衡，用以提高超结功率器件的耐压；位于每个p型柱状掺杂区29之上的p型体区22，以及至少一个第一MOSFET单元200和至少一个第二MOSFET单元300，在图2中仅示例性的示出了一个第一MOSFET单元200和一个第二MOSFET单元300。
本发明实施例的第一MOSFET单元200包括：位于p型体区22内的第一n型源区23；位于p型体区22之上的第一栅极结构，该第一栅极结构包括第一栅介质层24、n型浮栅25和第一栅极26，第一栅极26和n型浮栅25位于第一栅介质层24之上，且在横向上，n型浮栅25位于靠近n型漂移区21的一侧，第一栅极26位于靠近第一n型源区23的一侧且延伸至n型浮栅25之上，第一栅极26和n型浮栅25由绝缘介质层27隔离，第一栅极26通过电容耦合作用于n型浮栅25。绝缘介质层27通常为二氧化硅。在n型浮栅25下方的第一栅介质层24中形成有一个开口28，n型浮栅25开口28与p型体区22接触形成p-n结二极管。
如图2所示，本发明实施例的第二MOSFET单元300包括位于p型体区22内的第二n型源区33，在图2所示的本发明实施例的超结功率器件中，第一MOSFET单元200的第一n型源区23和第二MOSFET单元300的第二n型源 区33形成在两个不同的p型体区22中；位于p型体区22之上的第二栅介质层34以及位于第二栅介质层34之上的第二栅极36，第二栅极36可以通过栅极电压来控制第二MOSFET单元300的电流沟道(即介于第二n型源区33与n型漂移区21之间的电流沟道)的开启和关断。
本发明实施例的超结功率器件，在正向阻断状态时，n型漏区20被施加高电压，第一MOSFET单元200中的p-n结二极管被正向偏置，n型浮栅25被充入正电荷，这使得n型浮栅25下面的电流沟道的阈值电压Vht1降低。
本发明实施例的超结功率器件在正向阻断状态和正向开启状态时，漏源电压Vds大于0V，n型浮栅25下面的电流沟道的阈值电压Vht1对整个第一MOSFET单元200的阈值电压Vth的影响很低，第一MOSFET单元200仍具有高阈值电压。本发明实施例的超结功率器件在关断时，当源漏电压Vsd大于0V时，n型浮栅25下面的电流沟道的阈值电压Vht1对整个第一MOSFET单元200的阈值电压Vth的影响很大，使得第一MOSFET单元200具有低阈值电压Vth，从而使第一MOSFET单元200的电流沟道在低栅极电压(或0V电压)下导通，从而能够增加流过第一MOSFET单元200的反向电流，减少流过超结功率器件中寄生的体二极管的电流，提高超结功率器件的反向恢复速度。
本发明实施例的超结功率器件中的第一MOSFET单元200用于调节超结功率器件的反向恢复速度，但是由于第一栅极26和n型浮栅25横向设置，同时受第一栅介质层24中的开口28的尺寸的限制，第一MOSFET单元200具有很长的电流沟道，这会增加超结功率器件芯片的尺寸，不利于超结功率器件进行更小尺寸的封装。本发明实施例通过设置第二MOSFET单元300，第二MOSFET单元300不设置n型浮栅结构，这可以使得第二MOSFET单元300相较于第一MOSFET单元200具有短的电流沟道，因此，通过设置第一MOSFET单元200和第二MOSFET单元300的比例，可以在保证超结功率器件具有快的反向恢复速度的前提下，还可以有效控制超结功率器件的芯片尺寸，从而使超结功率器件芯片可以进行更小尺寸的封装。
本发明实施例的超结功率器件，由于第一MOSFET单元200和第二MOSFET单元300具有不同的栅极结构，为避免第一MOSFET单元200和第二MOSFET单元300具有不同的阈值电压，可以使得第一MOSFET单元200的第一栅极26与第一n型源区23电性连接，即第一栅极26接源极电压，此时第一MOSFET单元200仅用于流过反向电流，而不提供超结功率器件的开启电流， 这可以保证超结功率器件的电流沟道开启的一致性。
图3是本申请提供的一种超结功率器件的第二个实施例的剖面结构示意图，与图2所示的本申请的第一个实施例所述超结功率器件结构不同的是，本实施例中的第一n型源区23和第二n型源区33形成在同一个p型体区22内，同时，第二MOSFET单元300还包括一个凹陷在n型漂移区21内的栅沟槽，第二栅介质层34和第二栅极36均形成在该栅沟槽内。采用垂直电流沟道结构的第二MOSFET单元300可以减小超结功率器件的芯片尺寸。
图4是本申请提供的一种超结功率器件的第三个实施例的剖面结构示意图，与图3所示的本申请的第二个实施例所述超结功率器件结构不同的是，本实施例中的第一MOSFET单元200的第一栅极26延伸至n型浮栅25之上且覆盖n型浮栅25靠近n型漂移区21一侧的侧壁，这可以增大第一栅极26覆盖n型浮栅25的面积，进而能够增大第一栅极26对n型浮栅26的电容耦合率。

Claims (6)

  1. 一种超结功率器件，包括：
    n型漏区，位于所述n型漏区之上的n型漂移区，位于所述n型漂移区内的多个p型柱状掺杂区，位于每个所述p型柱状掺杂区之上的p型体区，以及至少一个第一MOSFET单元和至少一个第二MOSFET单元；
    所述第一MOSFET单元包括：位于所述p型体区内的第一n型源区；位于所述p型体区之上的第一栅极结构，所述第一栅极结构包括第一栅介质层以及位于所述第一栅介质层之上的第一栅极和n型浮栅，且在横向上，所述n型浮栅位于靠近所述n型漂移区的一侧，所述第一栅极位于靠近所述第一n型源区的一侧并延伸至所述n型浮栅之上，所述第一栅极通过电容耦合作用于所述n型浮栅；位于所述第一栅介质层中的一个开口，所述n型浮栅通过所述开口与所述p型体区接触形成p-n结二极管；
    所述第二MOSFET单元包括：位于所述p型体区内的第二n型源区，用于控制介于所述第二n型源区和所述n型漂移区之间的电流沟道的开启和关断的第二栅极结构，所述第二栅极结构包括第二栅介质层和第二栅极。
  2. 如权利要求1所述的超结功率器件，其中，所述第二MOSFET单元还包括凹陷在所n型漂移区内的栅沟槽，所述第二栅介质层和所述第二栅极位于所述栅沟槽内。
  3. 如权利要求1所述的超结功率器件，其中，所述第一n型源区和所述第二n型源区位于同一个所述p型体区内。
  4. 如权利要求1所述的超结功率器件，其中，所述第一n型源区和所述第二n型源区位于两个不同的所述p型体区内。
  5. 如权利要求1所述的超结功率器件，其中，所述第一栅极覆盖所述n型浮栅靠近所述n型漂移区一侧的侧壁。
  6. 如权利要求1所述的超结功率器件，其中，所述第一MOSFET单元的第一栅极与所述第一n型源区电性连接。
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