WO2020151088A1 - 一种极低反向恢复电荷超结功率vdmos - Google Patents

一种极低反向恢复电荷超结功率vdmos Download PDF

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WO2020151088A1
WO2020151088A1 PCT/CN2019/081816 CN2019081816W WO2020151088A1 WO 2020151088 A1 WO2020151088 A1 WO 2020151088A1 CN 2019081816 W CN2019081816 W CN 2019081816W WO 2020151088 A1 WO2020151088 A1 WO 2020151088A1
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vdmos
region
super junction
drain
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French (fr)
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祝靖
田甜
李少红
孙伟锋
陆生礼
时龙兴
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东南大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the invention relates to the field of power semiconductor devices, in particular to a method for preparing a super junction power VDMOS device with extremely low reverse recovery charge
  • SJ-VDMOS Super Junction Vertical Double-diffusion Metal-oxide-semiconductor
  • SJ-VDMOS introduces highly doped P pillars to mutually deplete the high-concentration N-type voltage withstand layer laterally to reduce the vertical electric field of the device, and achieve high voltage withstand capability and low on-resistance of the device.
  • the highly doped p-pillar greatly improves the anode emission area and hole injection efficiency of the SJ-VDMOS body diode, resulting in extremely poor reverse recovery characteristics of the SJ-VDMOS body diode, such as excessive reverse recovery current.
  • Carrier lifetime control technology such as electron irradiation technology and heavy metal doping technology, by introducing deep-level recombination centers, effectively reducing the lifetime of minority carriers in the N-type withstand voltage layer to reduce the reverse recovery charge , But it will cause a substantial increase in device leakage current, especially at high temperatures, and the cost of electron irradiation technology is high, and heavy metal doping technology is complicated.
  • the improvement of the reverse recovery characteristics of the body diode of SJ-VDMOS and the level of leakage current have a trade-off relationship with the area of the Schottky diode.
  • the larger the area the more obvious the improvement effect of reverse recovery characteristics, but the leakage current Also significantly increased;
  • the current capability of Schottky diodes is lower than that of SJ-VDMOS body diodes, so that when high freewheeling current flows, the body diode still plays a leading role in freewheeling, which greatly reduces the reverse recovery characteristics of the scheme The improvement effect.
  • the present invention proposes an SJ-VDMOS device with extremely low reverse recovery charge.
  • This structure maintains high withstand voltage, low leakage and low production cost, while significantly reducing the reverse of the SJ-VDMOS body diode.
  • the recovery charge Qrr increases the reverse recovery softness factor S, and can still achieve excellent reverse recovery characteristics under large freewheeling current conditions, thereby reducing the power consumption and electromagnetic interference of the device during reverse recovery Noise further improves the reliability of the device.
  • a very low reverse recovery charge super junction power VDMOS including a super junction VDMOS
  • the super junction VDMOS includes an N-type substrate that doubles as a drain and an N-type drift region provided on the N-type substrate. Its characteristics are In that, a first P pillar is provided in the N-type drift region of the super junction VDMOS, a first P-type body region is provided on the top of the first P-pillar, and the top surface of the first P-type body region and the N-type drift region The top surface is flush, an NMOS tube is provided on the first P-type body region, and a SiO2 isolation layer is provided between the NMOS tube and the first P-type body region.
  • the source metal of the super junction VDMOS serves as the The drain of the super junction power VDMOS
  • the gate of the super junction VDMOS is connected to the gate of the NMOS transistor and serves as the gate of the super junction power VDMOS
  • the drain of the NMOS transistor serves as the The source of the super-junction power VDMOS
  • a Schottky contact is also provided on the N-type drift region of the super-junction VDMOS, and the Schottky contact is connected to the drain of the N MOS transistor, and thus forms a cathode connected to the The drain and anode of the super junction power VDMOS are connected to the Schottky diode of the source of the super junction power VDMOS.
  • the present invention Compared with the traditional SJ-VDMOS, the present invention has the following advantages:
  • the present invention uses the integrated cell distributed Schottky contact 9 to conduct the freewheeling current, which greatly reduces the total amount of hole charges stored in the N-type withstand voltage layer during the freewheeling period. Since the body diode of a traditional SJ-VDMOS device is composed of a high-concentration first P-type body region, a P column and an N-type withstand voltage layer, when the body diode is forward conductive, a large amount of hole current will flow through the N The N-type withstand voltage layer causes a large amount of holes to be stored in the N-type withstand voltage layer, resulting in extremely poor body diode reverse recovery characteristics and a large amount of reverse recovery charge (Qrr).
  • Schottky diode is a majority carrier (electron) conductive device, so that during the forward conduction period, there is almost no storage of hole carriers in the N-type withstand voltage layer, thereby significantly improving the reverse recovery of SJ-VDMOS Features, greatly reducing Qrr.
  • the present invention uses an isolated NMOS tube composed of a P-type substrate region 11, an N-type heavily doped drain region 13, an N-type heavily doped source region 51, a P-type heavily doped region 10B and an SiO2 isolation layer 12
  • the reverse biased PN junction composed of the P-type substrate region and the N-type heavily doped drain region in 101 can block the freewheeling current, forcing the current to flow through the Schottky diode, effectively suppressing SJ-
  • the turn-on of the VDMOS body diode realizes the excellent reverse recovery characteristics of the device under the condition of large freewheeling current.
  • the freewheeling current completely flows out of the drain through the Schottky diode during the freewheeling period, thereby significantly improving the performance of the traditional parallel Schottky diode SJ-VDMOS device. Poor reverse recovery characteristics under current flow.
  • the NMOS device is connected in series under the SJ-VDMOS device, the sources of the two MOS devices are short-circuited, the gate voltage is the same, and the body diode PN junction directions of the two MOS devices are opposite.
  • the channel of the NMOS tube is not turned on and the body diode is reverse biased, and the current cannot flow through the NMOS tube, forcing the current to flow only to the multi-conducting Schottky diode instead of the SJ-VDMOS
  • the body diode realizes the excellent reverse recovery characteristics of the device in the case of large freewheeling current, as shown in the reverse recovery comparison diagram of the two structures in Figure 6.
  • the present invention uses the integrated NMOS and SJ-VDMOS to have the same gate and source, so that the structure of the present invention can be driven like a traditional SJ-VDMOS.
  • the gate is connected to high potential
  • the source (the drain of NMOS) is connected to 0 potential
  • the drain of SJ-VDMOS is connected to high potential.
  • the channels of NMOS and SJ-VDMOS At the same time, the drain current flows from the drain to the source; in the case of reverse withstand voltage, the gate and source are shorted to ground, and the drain is connected to high potential.
  • It is composed of N-type withstand voltage layer, P-pillar and p-body Reverse bias PN junction for voltage resistance.
  • the present invention utilizes the feature of greatly improving the reverse recovery characteristics under a very small Schottky contact area, and realizes excellent leakage characteristics.
  • Traditional SJ-VDMOS devices with Schottky diodes in parallel need a larger Schottky contact area to achieve a good reverse recovery effect, and a larger Schottky area will cause the reverse bias leakage current of SJ-VDMOS to increase significantly .
  • the structure of the present invention utilizes the characteristic that the freewheeling current can only flow through the Schottky diode, and the freewheeling can be realized with only a very small Schottky area, thereby achieving excellent leakage characteristics, as shown in the traditional SJ-
  • the comparison of the reverse bias characteristics of the proposed new structure in which the area of VMOS and Schottky occupy 9.9% of the entire cell is shown in the figure.
  • Figure 1 shows the structure of the traditional SJ-MOSFET.
  • Figure 2 shows the structure of the proposed SJ-MOSFET, in which Figure 2-1 is the overall structure of the proposed SJ-MOSFET, and Figure 2-2 is the partial enlarged structure of the NMOS tube in the proposed SJ-MOSFET.
  • Figure 3 shows the circuit structure diagram of the proposed SJ-MOSFET.
  • Figure 4 shows the working principle diagram of the proposed structure, among which, Figure 4-1 is the equivalent circuit diagram of the proposed SJ-VDMOS device in the freewheeling phase, and Figure 4-2 shows the reverse recovery process of the proposed SJ-VDMOS device. Effect circuit diagram
  • Figure 5-1 shows the comparison of the hole concentration distribution when the two structures are forward conducting.
  • Figure 5-2 shows the comparison of the electron concentration distribution of the two structures when the forward conduction is conducted.
  • Figure 6 shows the comparison of the body diode current reverse recovery waveforms of the two structures.
  • Figure 7 shows the comparison of the reverse bias characteristics of the two structures.
  • Figure 8 shows the comparison diagram of the compromise relationship between Qrr and Ron,sp of the proposed structure.
  • Figure 9 shows the quality factor comparison chart of the two structures.
  • a very low reverse recovery charge super junction power VDMOS including a super junction VDMOS
  • the super junction VDMOS includes an N-type substrate 1 that also serves as a drain, and an N-type drift region 2 provided on the N-type substrate 1 , Characterized in that, a first P pillar 31 is provided in the N-type drift region 2 of the super junction VDMOS, a first P-type body region 41 is provided on the top of the first P-pillar 31, and the first P-type body region 41 The top surface is flush with the top surface of the N-type drift region 2, an NMOS tube 101 is provided on the first P-type body region 41, and an NMOS tube 101 is provided between the NMOS tube 101 and the first P-type body region 41.
  • a first P-type heavily doped region 10A is also provided on the first P-type body region 41, the source metal of the super junction VDMOS, the source metal of the NMOS transistor 101, and the second A P-type heavily doped region 10A is connected; the drain of the super junction VDMOS is used as the drain of the super junction power VDMOS, and the gate of the super junction VDMOS is connected to the gate of the N MOS transistor 101 and As the gate of the super junction power VDMOS, the drain of the NMOS transistor 101 serves as the source of the super junction power VDMOS; a Schottky contact 9 is also provided on the N-type drift region 2 of the super junction VDMOS.
  • the Schottky contact 9 is connected to the drain of the NMOS transistor 101, thereby forming a Schottky diode whose cathode is connected to the drain of the super junction power VDMOS and the anode is connected to the source of the super junction power VDMOS.
  • a Schottky diode whose cathode is connected to the drain of the super junction power VDMOS and the anode is connected to the source of the super junction power VDMOS.
  • the super junction VDMOS also has a second P pillar 32 in the N-type drift region 2, a second P-type body region 42 is provided on the top of the second P-pillar 32, and the top surface of the second P-type body region 42 and N The top surface of the type drift region 2 is flush, the N-type heavily doped source region 5 of super junction VDMOS is provided in the second P-type body region 42, and the N-type heavily doped source region 5 of the super junction VDMOS is connected with
  • the source metal 8, above the N-type heavily doped source region 5 of the super junction VDMOS is provided with a gate oxide layer 6 encapsulating the first gate conductive polysilicon 7 and the first gate conductive polysilicon 7 is the super junction VDMOS
  • the gate oxide layer 6 and the gate conductive polysilicon 7 extend through the second P-type body region 42 and enter above the N-type drift region 2.
  • the NMOS tube 101 includes a P-type substrate region 11, and an N-type heavily doped drain region 13 of the NMOS tube 101 is provided on the top of the P-type substrate region 11.
  • the N-type heavily doped source region 51 and the N-type heavily doped The second P-type heavily doped region 10B in contact with the hetero-source region 51, the drain metal 14 is connected to the N-type heavily doped drain region 13, and the N-type heavily doped source region 51 and the second
  • the P-type heavily doped region 10B is provided with a connection source metal 8
  • the N-type heavily doped drain region 13 is provided with a second gate oxide layer 62 containing a second gate conductive polysilicon 72 and the second gate is conductive
  • the polysilicon 72 is the gate of the NMOS tube 101, and the second gate oxide layer 62 and the second gate conductive polysilicon 72 extend through the P-type substrate region 11 and enter above the N-type heavily doped source region 51.
  • the Schottky contacts 9 are respectively located between the first P-type body region 41 and the second P-type body region 42 and outside the first P-type body region 41 and the second P-type body region 42, and have a length of 2 to 3 ⁇ m, and Use arsenic metal.
  • the SiO2 isolation layer 12 has a depth of 4.8 ⁇ m ⁇ 5.2 ⁇ m, a width of 1.9 ⁇ m ⁇ 2.1 ⁇ m, and a thickness of
  • the concentration of the P-type substrate region 11 of the NMOS tube is 1e16 eV, and the length of the gate oxide layer is 1.2 ⁇ m to 1.6 ⁇ m.
  • FIG. 3 The structure of the SJ-VDMOS device proposed by the present invention is shown in FIG. 3.
  • Reverse turn-off when the gate and source of the proposed structure are shorted together and connected to a low potential, and the drain is connected to a high potential, a reverse biased PN composed of an N-type withstand voltage layer, P-pillar and p-body Knot, bear the reverse bias withstand voltage.
  • Freewheeling process In the schematic diagram of the circuit shown in Figure 4-1, the gate and source are shorted to a high potential, and the drain is connected to a low potential. At this time, the channel is turned off and the reverse bias PN junction existing in the NMOS is blocked The freewheeling current flows through the body diode of the traditional SJ-VDMOS, and the freewheeling current flows into the N-type withstand voltage layer only through the Schottky electrode, and then flows out through the drain.
  • the body diode of the SJ-VDMOS does not turn on, so during the freewheeling period, the freewheeling current flowing through the device is almost entirely composed of electron currents, making the total amount of holes stored in the N-type withstand voltage layer almost zero , As shown in Figure 5, the electron current density in the voltage withstand layer is very high and the hole current density is extremely low.
  • Reverse recovery process As shown in Figure 4-2, when the external voltage condition gradually changes from the state during the freewheeling process to the gate and source short-circuited to a common low potential, when the drain is connected to a high potential, reverse recovery The process happens. During the freewheeling period, the total amount of holes stored in the N-type withstand voltage layer is almost no, resulting in that the space charge region in the N-type withstand voltage layer can be quickly depleted to withstand the voltage and achieve excellent reverse recovery characteristics.
  • Such as extremely fast reverse recovery time trr, extremely low reverse recovery storage charge Qrr, and higher softness factor S as shown in Figure 6 for the proposed structure with traditional SJ-VDMOS and Schottky ratio K of 9.9% The reverse recovery waveform comparison is shown.

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Abstract

本发明涉及一种极低反向恢复电荷超结功率VDMOS，包括兼做漏极的N型衬底及N型漂移区，N型漂移区内设有第一P柱，第一P柱的顶部设有第一P型体区，在第一P型体区上设有NMOS管，所述NMOS管与所述第一P型体区之间设有SiO2隔离层，所述第一P型体区上设有第一P型重掺杂区，所述超结VDMOS的源极金属、NMOS管的源极金属及第一P型重掺杂区相连接；所述超结VDMOS的漏极作为所述超结功率VDMOS的漏极，所述超结VDMOS的栅极与所述NMOS管的栅极连接并作为所述超结功率VDMOS的栅极，所述NMOS管的漏极作为所述超结功率VDMOS的源极；在超结VDMOS的N型漂移区上设有肖特基接触且肖特基接触与所述NMOS管的漏极连接，以形成阴极和阳极分别连接于本发明所提结构漏极与源极的肖特基二极管。

Description

一种极低反向恢复电荷超结功率VDMOS 技术领域
本发明涉及功率半导体器件领域，特别是涉及一种具有极低反向恢复电荷的超结功率VDMOS器件的制备方法
背景技术
超结纵向金属氧化物半导体场效应管(Super Junction Vertical Double-diffusion Metal-oxide-semiconductor简称SJ-VDMOS)因其打破硅极限，在实现极低导通电阻的同时，又维持了器件高的耐压性能，使其在脉冲宽度调制和电机控制电路中具有广泛地应用。
传统SJ-VDMOS引入高掺杂的P柱来和高浓度N型耐压层相互横向耗尽，以降低器件的纵向电场，实现器件高的耐压能力和低的导通电阻。但高掺杂的p柱，大幅地提升了SJ-VDMOS体二极管的阳极发射面积和空穴注入效率，造就了SJ-VDMOS体二极管极其恶劣的反向恢复特性，如过高的反向恢复电流(Irrm)，过大的反向恢复电荷(Qrr)和极低的软度因子(S)，进而降低器件工作的可靠性、增加系统的工作损耗和引起严重的电磁干扰(EMI)噪声，严重制约了SJ-VDMOS在硬开关拓扑结构和高频开关运用领域中的应用。为克服传统SJ-VDMOS体二极管反向恢复特性差的问题，人们通常采用两种主要的技术手段：载流子寿命控制技术以及并联肖特基二极管技术。(一)载流子寿命控制技术，例如电子辐照技术和重金属掺杂技术，通过引入深能级复合中心，有效地降低N型耐压层中少数载流子的寿命来降低反向恢复电荷，但会导致器件漏电流的大幅增加，尤其在高温下，且电子辐照技术成本高、重金属掺杂技术工艺复杂。(二)并联肖特基二极管技术，使得续流电流大部分由肖特基二极管来导通，减少流经SJ-VDMOS体二极管的电流，从而显著地其改善反向恢复特性。但该方案不可避免地导致两方面尖锐的问题。一是，SJ-VDMOS的体二极管反向恢复特性改善和泄露电流水平高低，与肖特基二极管的面积大小存在折中关系，如面积越大，反向恢复特性改善效果越明显，但泄露电流也显著增加；二是，肖特基二极管的电流能力不及SJ-VDMOS体二极管，使得在流过高续流电流时，体二极管依然起续流的主导作用，大幅降低该方案对反向恢复特性的改善作用。上述可见，现有的并联肖特基方案无法在维持较低泄露电流水平的基础上，大幅地改善SJ-VDMOS体二极管反向恢复特性，且该技术方案受限于续流电流水平高低，仅在较低的续流电流下，能够起到很好的反向恢复改善。因此，我们提出了一种新型SJ-VDMOS新结构，在实现了良好的反向恢复特性的同时确保器件低的漏电特性，且在高续流电流下，该结构依然能够实现卓越的反向恢复特性。
发明内容
本发明针对上述问题，提出了一种极低反向恢复电荷的SJ-VDMOS器件，该结构在保持高耐压、低漏电和低生产成本的同时，显著减小了SJ-VDMOS体二极管反向恢复电荷Qrr，增加了反向恢复的软度因子S，且在大续流电流状况下，依然能够实现卓越的反向恢复特性，从而减小了器件在反向恢复期间的功耗以及电磁干扰噪声，进一步 提高了器件的可靠性。
本发明的技术方案如下：
一种极低反向恢复电荷超结功率VDMOS，包括一超结VDMOS，所述超结VDMOS包括兼做漏极的N型衬底和设在N型衬底上的N型漂移区，其特征在于，在超结VDMOS的N型漂移区内设有第一P柱，在第一P柱的顶部设有第一P型体区且第一P型体区的顶面与N型漂移区的顶面平齐，在第一P型体区上设有NMOS管，在所述NMOS管与所述第一P型体区之间设有SiO2隔离层，在所述第一P型体区上还设有第一P型重掺杂区，所述超结VDMOS的源极金属、NMOS管的源极金属及第一P型重掺杂区相连接；所述超结VDMOS的漏极作为所述超结功率VDMOS的漏极，所述超结VDMOS的栅极与所述N MOS管的栅极连接并作为所述超结功率VDMOS的栅极，所述N MOS管的漏极作为所述超结功率VDMOS的源极；在超结VDMOS的N型漂移区上还设有肖特基接触且肖特基接触与所述N MOS管的漏极连接，并由此形成阴极连接于所述超结功率VDMOS漏极、阳极连接于所述超结功率VDMOS源极的肖特基二极管。
与传统SJ-VDMOS相比，本发明具有如下优点：
1、本发明利用集成的元胞分布式肖特基接触9来导通续流电流，大幅降低了续流期间N型耐压层中存储的空穴电荷总量。由于传统SJ-VDMOS器件的体二极管由高浓度的第一P型体区、P柱和N型耐压层所构成，当该体二极管正向导通时，会产生大量的空穴电流流经N型耐压层，致使大量的空穴存储在N型耐压层中，导致体二极管反向恢复特性极差，反向恢复电荷数目(Qrr)总量大。肖特基二极管是一种多数载流子(电子)导电器件，使得正向导通期间，N型耐压层中几乎没有空穴载流子的存储，从而显著地提升SJ-VDMOS的反向恢复特性，大幅地降低Qrr。
2、本发明利用由P型衬底区11、N型重掺杂漏区13、N型重掺杂源区51、P型重掺杂区10B和SiO2隔离层12所构成的隔离型NMOS管101中P型衬底区和N型重掺杂漏区组成的反偏PN结，对续流电流起阻断作用，迫使该电流只能通过肖特基二极管进行续流，有效地抑制SJ-VDMOS体二极管的开启，从而实现了在大续流电流情况下，器件卓越的反向恢复特性。传统并联肖特基二极管的SJ-VDMOS器件，利用肖特基二极管开启电压低和多子导电的特点，可以在较小的续流电流下，实现理想的反向恢复特性。然而当续流电流(IF)较高时，SJ-VDMOS的体二极管对续流电流起主导作用，绝大部分续流电流流经该二极管，使得该方法对反向恢复的改善效果大幅降低。而本发明中，由于NMOS的反偏PN结存在，在续流期间，使续流电流完全经由肖特基二极管流出漏极，从而显著改善传统并联肖特基二极管的SJ-VDMOS器件在大续流电流下较差的反向恢复特性。如电路图3所示，NMOS器件串联在SJ-VDMOS器件下方，两个MOS器件的源极短接、栅极电压相同，且两个MOS器件的体二极管PN结方向相反。故而当环路续流时，NMOS管沟道没有导通且体二极管反偏，电流无法从NMOS管流过，迫使电流只流向多子导电的肖特基二极管而并不流经SJ-VDMOS的体二极管，从而实现了器件在大续流电流情况下卓越的反向恢复特性，如图6两种结构反向恢复对比图所示。此外，肖特基接触的引入不仅导致极低的反向恢复存储电荷Qrr，还导致正向导通时特征导通电阻Ron,sp的增大，这意味着对于SJ-VDMOS其反向恢复存储电荷和特征导通电阻之间存在折中关系，如图8所示。品质因数是个权衡反向恢复存储电荷和特征导通电阻之间关系优劣的重要参数，如图9所示，所提结构的品质因数比传统结构的品质因数下降了94.9％,体现所提结构在正向导通和反向恢复中总体的优越性。
3、本发明利用集成的NMOS和SJ-VDMOS具有相同的栅极和源极，使得在本发明结构，可以像使用传统SJ-VDMOS一样进行驱动。正向导通时，在图3电路示意图中，栅极接高电位，源极(NMOS的漏极)接0电位，SJ-VDMOS的漏极接高电位，此时NMOS和SJ-VDMOS的沟道同时开启，漏极电流从漏极流向源极；反向耐压时，栅极和源极短接接地，漏极接高电位，由N型耐压层、P-pillar和p-body构成的反偏PN结，进行耐压。
4、本发明利用在极小的肖特基接触面积下就可以大幅地改善反向恢复特性的特点，实现了优异的漏电特性。传统并联肖特基二极管的SJ-VDMOS器件需要较大的肖特基接触面积才能取得良好的反向恢复效果，而较大的肖特基面积，会导致SJ-VDMOS的反偏泄露电流显著增加。而本发明结构，利用续流电流只能流过肖特基二极管的特点，只需极小的肖特基面积，就可以实现续流，从而实现了优异的漏电特性，如图7传统SJ-VMOS与肖特基面积在整个元胞中的占比K为9.9％的所提新结构的反偏特性对比图中所示。
附图说明
图1所示为传统SJ-MOSFET结构图。
图2所示为所提SJ-MOSFET结构图，其中，图2-1为所提SJ-MOSFET的整体结构图，图2-2为所提SJ-MOSFET中NMOS管的局部放大结构图。
图3所示为所提SJ-MOSFET电路结构图。
图4所示为所提结构工作原理图，其中，图4-1为所提SJ-VDMOS器件续流阶段的等效电路图，图4-2为所提SJ-VDMOS器件反向恢复过程的等效电路图
图5-1所示为两种结构正向导通时空穴浓度分布对比图。
图5-2所示为两种结构正向导通时电子浓度分布对比图。
图6所示为两种结构的体二极管电流反向恢复波形对比图。
图7所示为两种结构反偏特性对比图。
图8所示为所提结构的Qrr与Ron,sp的折中关系对比图。
图9所示为两种结构的品质因数对比图。
具体实施方式
一种极低反向恢复电荷超结功率VDMOS，包括一超结VDMOS，所述超结VDMOS包括兼做漏极的N型衬底1和设在N型衬底1上的N型漂移区2，其特征在于，在超结VDMOS的N型漂移区2内设有第一P柱31，在第一P柱31的顶部设有第一P型体区41且第一P型体区41的顶面与N型漂移区2的顶面平齐，在第一P型体区41上设有N MOS管101，在所述N MOS管101与所述第一P型体区41之间设有SiO2隔离层12，在所述第一P型体区41上还设有第一P型重掺杂区10A，所述超结VDMOS的源极金属、N MOS管101的源极金属及第一P型重掺杂区10A相连接；所述超结VDMOS的漏极作为所述超结功率VDMOS的漏极，所述超结VDMOS的栅极与所述N MOS管101的栅极连接并作为所述超结功率VDMOS的栅极，所述NMOS管101的漏极作为所 述超结功率VDMOS的源极；在超结VDMOS的N型漂移区2上还设有肖特基接触9且肖特基接触9与所述N MOS管101的漏极连接，并由此形成阴极连接于所述超结功率VDMOS漏极、阳极连接于所述超结功率VDMOS源极的肖特基二极管。在本实施例中，
所述超结VDMOS还N型漂移区2内设有第二P柱32，在第二P柱32的顶部设有第二P型体区42且第二P型体区42的顶面与N型漂移区2的顶面平齐，在第二P型体区42内设有超结VDMOS的N型重掺杂源区5，在超结VDMOS的N型重掺杂源区5上连接有源极金属8，在超结VDMOS的N型重掺杂源区5的上方设有内包第一栅极导电多晶硅7的栅氧化层6且第一栅极导电多晶硅7为所述超结VDMOS的栅极，所述栅氧化层6和栅极导电多晶硅7延伸经过第二P型体区42并进入N型漂移区2的上方。
所述N MOS管101包括P型衬底区11，在P型衬底区11顶部设有N MOS管101的N型重掺杂漏区13N型重掺杂源区51以及与N型重掺杂源区51相接触的第二P型重掺杂区10B，在所述N型重掺杂漏区13上连接有漏极金属14，在所述N型重掺杂源区51和第二P型重掺杂区10B上设有连接有源极金属8，在N型重掺杂漏区13上设有内包第二栅极导电多晶硅72的第二栅氧化层62且第二栅极导电多晶硅72为所述NMOS管101的栅极，所述第二栅氧化层62和第二栅极导电多晶硅72延伸经过P型衬底区11并进入N型重掺杂源区51的上方。
肖特基接触9分别位于第一P型体区41与第二P型体区42之间以及第一P型体区41和第二P型体区42的外侧，长度为2～3μm，并采用砷金属。
SiO2隔离层12的深度为4.8μm～5.2μm，宽度为1.9μm～2.1μm，厚度为
Figure PCTCN2019081816-appb-000001
NMOS管的P型衬底区11的浓度为1e16eV，栅氧化层的长度为1.2μm～1.6μm。
下面结合附图对本发明做进一步说明。
本发明工作原理：
本发明所提出的SJ-VDMOS器件结构如图3所示。
正向导通：当所提结构栅极和漏极接高电位、源极接低电位时，其内部NMOS和SJ-VDMOS中电子沟道同时开启，在漏极高电位的作用下，形成从漏极流向源极的电子电流。
反向关断：当所提结构栅极和源极短接在一起共接低电位、漏极接高电位时，由N型耐压层、P-pillar和p-body所构成的反偏PN结，承受该反偏耐压。
续流过程：图4-1所示电路示意图中，栅极、源极短接共接高电位，漏极接低电位，此时沟道关断，且NMOS中存在的反偏PN结阻断续流电流流过传统SJ-VDMOS的体二极管，续流电流只经由肖特基电极流入N型耐压层，再经漏极流出。由于续流期间，SJ-VDMOS的体二极管不开启，所以续流期间，流经器件的续流电流几乎全由电子电流所组成，使得N型耐压层中存储的空穴总量几乎为0,如图5所示，耐压层中电子电流密 度很高而空穴电流密度极低。
反向恢复过程：如图4-2所示，当外部电压条件，由续流过程中的状态逐渐转为栅极和源极短接共接低电位，漏极接高电位时，反向恢复过程发生。由于续流期间，存储在N型耐压层中的空穴总量几乎没有，导致N型耐压层中的空间电荷区可以快速地耗尽以进行耐压，实现卓越的反向恢复特性，如极快的反向恢复时间trr，极低的反向恢复存储电荷Qrr，较高的软度因子S，如图6传统SJ-VDMOS与肖特基占比K为9.9％的所提结构的反向恢复波形对比所示。

Claims (6)

  1. 一种极低反向恢复电荷超结功率VDMOS，包括一超结VDMOS，所述超结VDMOS包括兼做漏极的N型衬底(1)和设在N型衬底(1)上的N型漂移区(2)，其特征在于，在超结VDMOS的N型漂移区(2)内设有第一P柱(31)，在第一P柱(31)的顶部设有第一P型体区(41)且第一P型体区(41)的顶面与N型漂移区(2)的顶面平齐，在第一P型体区(41)上设有NMOS管(101)，在所述NMOS管(101)与所述第一P型体区(41)之间设有SiO2隔离层(12)，在所述第一P型体区(41)上还设有第一P型重掺杂区(10A)，所述超结VDMOS的源极金属、NMOS管(101)的源极金属及第一P型重掺杂区(10A)相连接；所述超结VDMOS的漏极作为所述超结功率VDMOS的漏极，所述超结VDMOS的栅极与所述NMOS管(101)的栅极连接并作为所述超结功率VDMOS的栅极，所述NMOS管(101)的漏极作为所述超结功率VDMOS的源极；在超结VDMOS的N型漂移区(2)上还设有肖特基接触(9)且肖特基接触(9)与所述NMOS管(101)的漏极连接，并由此形成阴极连接于所述超结功率VDMOS漏极、阳极连接于所述超结功率VDMOS源极的肖特基二极管。
  2. 根据权利要求1所述的极低反向恢复电荷超结功率VDMOS，其特征在于，所述超结VDMOS在N型漂移区(2)内设有第二P柱(32)，在第二P柱(32)的顶部设有第二P型体区(42)且第二P型体区(42)的顶面与N型漂移区(2)的顶面平齐，在第二P型体区(42)内设有超结VDMOS的N型重掺杂源区(5)，在超结VDMOS的N型重掺杂源区(5)上连接有源极金属(8)，在超结VDMOS的N型重掺杂源区(5)的上方设有内包第一栅极导电多晶硅(7)的栅氧化层(6)且第一栅极导电多晶硅(7)为所述超结VDMOS的栅极，所述栅氧化层(6)和栅极导电多晶硅(7)延伸经过第二P型体区(42)并进入N型漂移区(2)的上方。
  3. 根据权利要求1所述的极低反向恢复电荷超结功率VDMOS，其特征在于，所述NMOS管(101)包括P型衬底区(11)，在P型衬底区(11)顶部设有NMOS管(101)的N型重掺杂漏区(13)N型重掺杂源区(51)以及与N型重掺杂源区(51)相接触的第二P型重掺杂区(10B)，在所述N型重掺杂漏区(13)上连接有漏极金属(14)，在所述N型重掺杂源区(51)和第二P型重掺杂区(10B)上设有连接有源极金属(8)，在N型重掺杂漏区(13)上设有内包第二栅极导电多晶硅(72)的第二栅氧化层(62)且第二栅极导电多晶硅(72)为所述NMOS管(101)的栅极，所述第二栅氧化层(62)和第二栅极导电多晶硅(72)延伸经过P型衬底区(11)并进入N型重掺杂源区(51)的上方。
  4. 根据权利要求1所述的极低反向恢复电荷超结功率VDMOS，其特征在于，肖特基接触(9)分别位于第一P型体区(41)与第二P型体区(42)之间以及第一P型体区(41)和第二P型体区(42)的外侧，长度为2～3μm，并采用砷金属。
  5. 根据权利要求1所述的极低反向恢复电荷超结功率VDMOS，其特征在于，SiO2隔离层(12)的深度为4.8μm～5.2μm，宽度为1.9μm～2.1μm，厚度为
    Figure PCTCN2019081816-appb-100001
  6. 根据权利要求3所述的极低反向恢复电荷超结功率VDMOS，其特征在于，NMOS管的P型衬底区(11)的浓度为1e16eV，栅氧化层的长度为1.2μm～1.6μm。
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