CN113130627B - 一种集成沟道二极管的碳化硅鳍状栅mosfet - Google Patents

一种集成沟道二极管的碳化硅鳍状栅mosfet Download PDF

Info

Publication number
CN113130627B
CN113130627B CN202110393954.3A CN202110393954A CN113130627B CN 113130627 B CN113130627 B CN 113130627B CN 202110393954 A CN202110393954 A CN 202110393954A CN 113130627 B CN113130627 B CN 113130627B
Authority
CN
China
Prior art keywords
region
layer
conductive material
source contact
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110393954.3A
Other languages
English (en)
Other versions
CN113130627A (zh
Inventor
罗小蓉
姜钦峰
黄俊岳
宋旭
苏伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN202110393954.3A priority Critical patent/CN113130627B/zh
Publication of CN113130627A publication Critical patent/CN113130627A/zh
Application granted granted Critical
Publication of CN113130627B publication Critical patent/CN113130627B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明属于功率半导体技术领域，具体涉及一种集成沟道二极管的碳化硅鳍状栅MOSFET。本发明的主要特征在于：具有沟槽结构，且在沟槽区底部集成了沟道二极管，当器件处于反向续流工作模式时，沟道二极管导通实现续流功能，降低了反向导通压降并有效抑制体二极管的导通，消除双极退化带来的影响；采用鳍状栅结构，保证沟槽下方P区域良好接地，使沟槽底部氧化层的峰值电场低于临界击穿值，提高器件在阻断工作模式下的可靠性；位于沟槽内的两个对称鳍状栅，以及位于鳍状栅下方的沟槽底部第三导电材料，构成复合分离栅结构，降低栅漏电容，减少开关损耗，使器件在高频应用中更具优势。

Description

一种集成沟道二极管的碳化硅鳍状栅MOSFET
技术领域
本发明属于功率半导体技术领域，具体涉及一种集成沟道二极管的碳化硅鳍状栅MOSFET。
背景技术
相较于硅(Si)材料，碳化硅(SiC)由于其独特的材料特性，如更大的禁带宽度、更高的饱和漂移速度以及更高的热导率等物理性质，具有更加优越的静态特性、高频特性以及耐高温特性，在功率器件的应用中越来越受到欢迎。相较于传统的SiC平面型MOS器件，SiC槽栅MOS器件因其更大的沟道密度而具有更低的导通电阻。然而SiC槽栅MOS器件存在栅氧化层峰值电场过大的问题，为解决这一问题，已有研究者提出一种SiC鳍状栅MOSFET，能够保证栅槽下方P区域良好接地，使得栅槽底部氧化层的峰值电场低于临界击穿值，并实现了更低的损耗。
在转换器和逆变器系统中，通常需要一个续流二极管与开关设备反向并联。尽管使用SiC MOSFET中的体二极管作为续流二极管能够节省成本和面积，然而宽禁带SiC材料的体二极管的开启电压较大，会导致高的导通损耗；同时SiC材料中因载流子复合而产生的双极退化效应，会引起导通电阻与反向漏电流增大等不利影响。针对上述问题，目前一种可行的解决方案是在器件中集成沟道二极管来实现反向续流功能，降低反向导通压降，同时抑制体二极管的导通进而避免双极退化效应。
发明内容
本发明的目的，就是针对上述问题，提出一种集成沟道二极管的碳化硅鳍状栅MOSFET，可以在保证MOSFET整体性能不下降的同时，避免续流二极管压降太大和双极退化效应两个问题，并且在高频应用中更具优势。
本发明的技术方案是：
一种集成沟道二极管的碳化硅鳍状栅MOSFET，包括自下而上依次层叠设置的第一导电材料1、N+衬底层2、N漂移区3、外延层4和P-body区9，所述第一导电材料1底部引出为漏极；
其特征在于，还包括沟槽结构和源区结构，所述沟槽结构沿垂直方向依次贯穿P-body区9和外延层4后与N漂移区3接触，所述源区结构为位于沟槽结构两侧的P-body区9上表面并列设置的第一P+源接触区10和第一N+源接触区11，其中第一N+源接触区11与沟槽结构接触；沟槽结构底部为P埋层5，P埋层5与N漂移区3接触，P埋层5的上表面中部具有第二P+源接触区6，第二P+源接触区6两侧为第二N+源接触区7，第二N+源接触区7外侧为P沟道区8；所述沟槽结构中具有沿沟槽结构中线呈对称设置的栅极结构，栅极结构包括第一绝缘介质层13、第二绝缘介质层14、第三绝缘介质17以及被第一绝缘介质层13、第二绝缘介质层14、第三绝缘介质层17包围的鳍状N+多晶硅栅12，所述第一绝缘介质层13覆盖沟槽区侧壁且横向延伸覆盖P沟道区8上表面，所述鳍状N+多晶硅栅12通过第一绝缘介质层13与第一N+源接触区11、P-body区9和外延层4隔离；第三导电材料15覆盖于第二P+源接触区6和第二N+源接触区7以及第一绝缘介质层13横向延伸的部分；第二绝缘介质层14位于第三导电材料15上表面且与鳍状N+多晶硅栅12底部接触，沟槽结构中两对称的栅极结构之间填充有第二导电材料16，第二导电材料16分别与第三导电材料15、第二绝缘介质层14、第三绝缘介质17接触，且第二导电材料16还覆盖第一P+源接触区10和第一N+源接触区11的上表面；第二导电材料16的引出为源极；
所述外延层4、P沟道区8、第二N+源接触区7、第一绝缘介质13与第三导电材料15构成沟道二极管。
本发明采用集成沟道二极管，在器件处于反向续流工作模式时，沟道二极管导通实现续流功能，降低了反向导通压降并有效抑制体二极管的导通，消除双极退化带来的影响；采用鳍状栅结构，在保证沟槽下方P区域良好接地的基础上降低沟槽底部氧化层的峰值电场，提高器件在阻断工作模式下的可靠性；位于沟槽内的两个对称鳍状栅，以及位于鳍状栅下方的沟槽底部接源电位的第三导电材料，构成复合分离栅结构，降低栅漏电容，减少开关损耗，使器件在高频应用中更具优势。
进一步的，所述P埋层5向下延伸至N漂移区3内，所述P埋层5与所述N漂移区3形成半超结结构。
本发明的有益效果为：相比于传统的碳化硅槽栅MOSFET，本发明槽栅MOSFET，利用集成的沟道二极管进行续流，降低反向导通压降且避免双极退化效应，提高器件反向导通能力；能够降低氧化层中的峰值电场，提高耐压和可靠性；且具有复合分离栅结构，能实现更低的栅漏电容，减少开关损耗。此外，如形成半超结结构，还能进一步提高耐压和降低导通电阻。相较于采用集成SBD(Schottky Barrier Diode)来消除双极退化效应的方法，反向漏电流更小并且具有更好的耐高温特性，且节省面积。
附图说明
图1为实施例1的结构示意图；
图2为实施例2的结构示意图；
具体实施方式
下面结合附图和实施例，对本发明技术方案进行详细描述：
实施例1
如图1所示，本实例为一种集成沟道二极管的碳化硅鳍状栅MOSFET，包括自下而上依次层叠设置的第一导电材料1、N+衬底层2、N漂移区3、外延层4和P-body区9，所述第一导电材料1底部引出为漏极；
其特征在于，还包括沟槽结构和源区结构，所述沟槽结构沿垂直方向依次贯穿P-body区9和外延层4后与N漂移区3接触，所述源区结构为位于沟槽结构两侧的P-body区9上表面并列设置的第一P+源接触区10和第一N+源接触区11，其中第一N+源接触区11与沟槽结构接触；沟槽结构底部为P埋层5，P埋层5与N漂移区3接触，P埋层5的上表面中部具有第二P+源接触区6，第二P+源接触区6两侧为第二N+源接触区7，第二N+源接触区7外侧为P沟道区8；所述沟槽结构中具有沿沟槽结构中线呈对称设置的栅极结构，栅极结构包括第一绝缘介质层13、第二绝缘介质层14、第三绝缘介质17以及被第一绝缘介质层13、第二绝缘介质层14、第三绝缘介质层17包围的鳍状N+多晶硅栅12，所述第一绝缘介质层13覆盖沟槽区侧壁且横向延伸覆盖P沟道区8上表面，所述鳍状N+多晶硅栅12通过第一绝缘介质层13与第一N+源接触区11、P-body区9和外延层4隔离；第三导电材料15覆盖于第二P+源接触区6和第二N+源接触区7以及第一绝缘介质层13横向延伸的部分；第二绝缘介质层14位于第三导电材料15上表面且与鳍状N+多晶硅栅12底部接触，沟槽结构中两对称的栅极结构之间填充有第二导电材料16，第二导电材料16分别与第三导电材料15、第二绝缘介质层14、第三绝缘介质17接触，且第二导电材料16还覆盖第一P+源接触区10和第一N+源接触区11的上表面；第二导电材料16的引出为源极；
所述外延层4、P沟道区8、第二N+源接触区7、第一绝缘介质13与第三导电材料15构成沟道二极管。
本例的工作原理是：
在槽下埋层中添加N+区，P沟道区8在反向续流工作时感应出负电势，在源电极零电位的作用下形成反型电子沟道，起到反向续流的功能，降低反向导通压降，同时抑制体二极管导通并避免双极退化效应；采用鳍状栅结构，保证沟槽下方P区域良好接地，在沟槽下埋层区不包住沟槽拐角的情况下，也能使氧化层中的峰值电场低于临界击穿值，提高器件在阻断工作模式下的可靠性；位于沟槽内的两个对称鳍状栅，以及位于鳍状栅下方的沟槽底部第三导电材料，构成复合分离栅结构，降低栅漏电容，减小开关损耗，在高频应用中更具优势。
实施例2
如图2所示，本实例与实例1相比区别在于，所述P埋层5向下延伸至N漂移区3中，所述P埋层5与所述N漂移区3形成半超结结构，在阻断状态下半超结区域形成梯形电场分布提高耐压，正向导通时更高的N漂移区3掺杂浓度可以降低导通电阻，提高了器件整体的静态特性。由于沟槽底部接源电位的P埋层的存在，原本槽栅底部与N漂移区3耗尽形成的栅漏电容会转换为栅源电容，而半超结结构会增强这一效果，使器件的栅漏电容进一步降低。

Claims (2)

1.一种集成沟道二极管的碳化硅鳍状栅MOSFET，包括自下而上依次层叠设置的第一导电材料(1)、N+衬底层(2)、N漂移区(3)、外延层(4)和P-body区(9)，所述第一导电材料(1)底部引出为漏极；
其特征在于，还包括沟槽结构和源区结构，所述沟槽结构沿垂直方向依次贯穿P-body区(9)和外延层(4)后与N漂移区(3)接触，所述源区结构为位于沟槽结构两侧的P-body区(9)上表面并列设置的第一P+源接触区(10)和第一N+源接触区(11)，其中第一N+源接触区(11)与沟槽结构接触；沟槽结构底部为P埋层(5)，P埋层(5)与N漂移区(3)接触，P埋层(5)的上表面中部具有第二P+源接触区(6)，第二P+源接触区(6)两侧为第二N+源接触区(7)，第二N+源接触区(7)外侧为P沟道区(8)；所述沟槽结构中具有沿沟槽结构中线呈对称设置的栅极结构，栅极结构包括第一绝缘介质层(13)、第二绝缘介质层(14)、第三绝缘介质层(17)以及被第一绝缘介质层(13)、第二绝缘介质层(14)、第三绝缘介质层(17)包围的鳍状N+多晶硅栅(12)，所述第一绝缘介质层(13)覆盖沟槽区侧壁且横向延伸覆盖P沟道区(8)上表面，所述鳍状N+多晶硅栅(12)通过第一绝缘介质层(13)与第一N+源接触区(11)、P-body区(9)和外延层(4)隔离；第三导电材料(15)覆盖于第二P+源接触区(6)和第二N+源接触区(7)以及第一绝缘介质层(13)横向延伸的部分；第二绝缘介质层(14)位于第三导电材料(15)上表面且与鳍状N+多晶硅栅(12)底部接触，沟槽结构中两对称的栅极结构之间填充有第二导电材料(16)，第二导电材料(16)分别与第三导电材料(15)、第二绝缘介质层(14)、第三绝缘介质层(17)接触，且第二导电材料(16)还覆盖第一P+源接触区(10)和第一N+源接触区(11)的上表面；第二导电材料(16)的引出为源极；
所述外延层(4)、P沟道区(8)、第二N+源接触区(7)、第一绝缘介质层(13)与第三导电材料(15)构成沟道二极管。
2.根据权利要求1所述的一种集成沟道二极管的碳化硅鳍状栅MOSFET，其特征在于，所述P埋层(5)向下延伸至N漂移区(3)内，所述P埋层(5)与所述N漂移区(3)形成半超结结构。
CN202110393954.3A 2021-04-13 2021-04-13 一种集成沟道二极管的碳化硅鳍状栅mosfet Active CN113130627B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110393954.3A CN113130627B (zh) 2021-04-13 2021-04-13 一种集成沟道二极管的碳化硅鳍状栅mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110393954.3A CN113130627B (zh) 2021-04-13 2021-04-13 一种集成沟道二极管的碳化硅鳍状栅mosfet

Publications (2)

Publication Number Publication Date
CN113130627A CN113130627A (zh) 2021-07-16
CN113130627B true CN113130627B (zh) 2022-08-23

Family

ID=76776002

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110393954.3A Active CN113130627B (zh) 2021-04-13 2021-04-13 一种集成沟道二极管的碳化硅鳍状栅mosfet

Country Status (1)

Country Link
CN (1) CN113130627B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11723207B2 (en) 2021-08-27 2023-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated chip with a gate structure disposed within a trench
CN113990923B (zh) * 2021-10-20 2023-04-04 电子科技大学 一种集成沟道二极管的碳化硅双槽mosfet
CN114122139B (zh) * 2021-11-30 2024-01-26 电子科技大学 具有集成二极管的碳化硅mosfet器件及制造方法
CN114497184B (zh) * 2021-12-23 2024-03-29 杭州士兰微电子股份有限公司 功率半导体器件元胞结构、功率半导体器件及其制造方法
CN114122123B (zh) * 2022-01-26 2022-04-22 成都蓉矽半导体有限公司 集成高速续流二极管的碳化硅分离栅mosfet及制备方法
CN116525681B (zh) * 2023-05-18 2023-11-24 南京第三代半导体技术创新中心有限公司 集成沟道二极管的碳化硅槽栅mosfet器件及制造方法
CN117317023B (zh) * 2023-11-23 2024-03-29 北京智芯微电子科技有限公司 抗辐射半导体器件、工艺、电路、芯片及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148591A (zh) * 2018-08-29 2019-01-04 电子科技大学 一种集成肖特基二极管的碳化硅槽栅mos器件
CN109256427A (zh) * 2018-09-19 2019-01-22 电子科技大学 一种集成肖特基二极管的SiC MOSFET器件
CN111697077A (zh) * 2020-06-18 2020-09-22 电子科技大学 一种SiC沟槽栅功率MOSFET器件及其制备方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6998907B1 (en) * 2004-05-17 2006-02-14 National Semiconductor Corporation Apparatus and method for receiving high-common mode voltage range signals with low-voltage devices
JP5303839B2 (ja) * 2007-01-29 2013-10-02 富士電機株式会社 絶縁ゲート炭化珪素半導体装置とその製造方法
JP2011134910A (ja) * 2009-12-24 2011-07-07 Rohm Co Ltd ＳｉＣ電界効果トランジスタ
DE102011079747A1 (de) * 2010-07-27 2012-02-02 Denso Corporation Halbleitervorrichtung mit Schaltelement und Freilaufdiode, sowie Steuerverfahren hierfür
CN102683403B (zh) * 2012-04-24 2015-05-27 电子科技大学 一种沟槽栅电荷存储型igbt
JP6286823B2 (ja) * 2012-12-26 2018-03-07 日産自動車株式会社 半導体装置の製造方法
DE102015121566B4 (de) * 2015-12-10 2021-12-09 Infineon Technologies Ag Halbleiterbauelemente und eine Schaltung zum Steuern eines Feldeffekttransistors eines Halbleiterbauelements
CN107994071A (zh) * 2017-12-11 2018-05-04 电子科技大学 一种异质结沟槽绝缘栅型场效应管
CN109119463B (zh) * 2018-08-29 2020-07-31 电子科技大学 一种横向沟槽型mosfet器件及其制备方法
CN109244136B (zh) * 2018-09-19 2021-07-27 电子科技大学 槽底肖特基接触SiC MOSFET器件
CN109860171B (zh) * 2019-01-31 2021-03-30 电子科技大学 集成高速反向续流二极管的双极型碳化硅半导体功率器件
CN109904155B (zh) * 2019-01-31 2021-02-02 电子科技大学 一种集成高速反向续流二极管的碳化硅mosfet器件
CN109904220A (zh) * 2019-03-18 2019-06-18 电子科技大学 槽栅型碳化硅mosfet器件及制备方法
CN109817712A (zh) * 2019-03-26 2019-05-28 电子科技大学 一种具有多导电沟道及鳍式栅的增强型hemt器件
CN110534575B (zh) * 2019-09-04 2020-09-29 电子科技大学 一种vdmos器件
CN111048590B (zh) * 2019-12-26 2023-03-21 北京工业大学 一种具有内嵌沟道二极管的双沟槽SiC MOSFET结构及其制备方法
CN111312802B (zh) * 2020-02-27 2022-01-28 电子科技大学 低开启电压和低导通电阻的碳化硅二极管及制备方法
CN112420694B (zh) * 2020-11-06 2023-06-23 电子科技大学 集成反向肖特基续流二极管的可逆导碳化硅jfet功率器件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148591A (zh) * 2018-08-29 2019-01-04 电子科技大学 一种集成肖特基二极管的碳化硅槽栅mos器件
CN109256427A (zh) * 2018-09-19 2019-01-22 电子科技大学 一种集成肖特基二极管的SiC MOSFET器件
CN111697077A (zh) * 2020-06-18 2020-09-22 电子科技大学 一种SiC沟槽栅功率MOSFET器件及其制备方法

Also Published As

Publication number Publication date
CN113130627A (zh) 2021-07-16

Similar Documents

Publication Publication Date Title
CN113130627B (zh) 一种集成沟道二极管的碳化硅鳍状栅mosfet
CN109244136B (zh) 槽底肖特基接触SiC MOSFET器件
CN109904155B (zh) 一种集成高速反向续流二极管的碳化硅mosfet器件
CN113990923B (zh) 一种集成沟道二极管的碳化硅双槽mosfet
CN112420694B (zh) 集成反向肖特基续流二极管的可逆导碳化硅jfet功率器件
CN102412297A (zh) 基于衬底偏压技术的硅基功率器件结构
CN110518065A (zh) 低功耗高可靠性的沟槽型碳化硅mosfet器件
CN108198857A (zh) 一种集成凸块状肖特基二极管的碳化硅mosfet器件元胞结构
CN112687744B (zh) 平面型碳化硅逆阻mosfet器件及其制备方法
CN109103257A (zh) 高可靠性深沟槽功率mos器件
CN116110796B (zh) 集成sbd的碳化硅sgt-mosfet及其制备方法
CN113629135A (zh) 一种集成沟槽和体平面栅的SiC MOSFET器件
CN105993076A (zh) 一种双向mos型器件及其制造方法
CN210805778U (zh) 一种SiC-MOS器件结构
CN112201687A (zh) 一种npn三明治栅结构的沟槽mosfet器件
CN111403474A (zh) 一种集成肖特基二极管的双沟道碳化硅mosfet器件
CN111933711B (zh) 一种集成sbd的超结mosfet
CN117497600B (zh) 超结碳化硅晶体管的结构、制造方法及电子设备
CN109166923B (zh) 一种屏蔽栅mosfet
CN109860303A (zh) 一种积累型沟道的绝缘栅功率器件
CN117497601A (zh) 平面型碳化硅晶体管的结构、制造方法及电子设备
CN208835068U (zh) 高可靠性深沟槽功率mos器件
CN212967713U (zh) 一种具有均匀掺杂沟道的屏蔽栅mosfet器件
CN114843332A (zh) 低功耗高可靠性半包沟槽栅mosfet器件及制备方法
CN212967710U (zh) 一种npn三明治栅结构的沟槽mosfet器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant