CN111403474A - 一种集成肖特基二极管的双沟道碳化硅mosfet器件 - Google Patents

一种集成肖特基二极管的双沟道碳化硅mosfet器件 Download PDF

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CN111403474A
CN111403474A CN202010205715.6A CN202010205715A CN111403474A CN 111403474 A CN111403474 A CN 111403474A CN 202010205715 A CN202010205715 A CN 202010205715A CN 111403474 A CN111403474 A CN 111403474A
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heavily doped
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易波
伍争
赵青
张千
向勇
石文坤
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University of Electronic Science and Technology of China
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Abstract

本发明属于功率半导体技术领域，具体提供一种集成肖特基二极管的双沟道碳化硅MOSFET器件，采用双沟道设计，形成两个接地的电场屏蔽区保护中间的肖特基二极管，使得肖特基结处电位能够被屏蔽的很低，从而降低泄露电流，提高击穿电压；同时，进一步降低肖特基势垒高度而不至于使得泄漏电流明显增大，进而降低肖特基二极管反向导通压降。此外，通过引入第一深槽内的平面沟道，一方面增加了沟道密度、降低了比导通电阻，另一方面通过将浮空电场屏蔽区接地、更好地起到屏蔽肖特基结电势的效果、从而降低肖特基势垒高度、降低反向导通压降，并且接地的电场屏蔽区能够消除浮空电场屏蔽区带来的动态电阻增大、弥勒电容增大的不良影响。

Description

一种集成肖特基二极管的双沟道碳化硅MOSFET器件
技术领域
本发明属于功率半导体技术领域，涉及功率半导体器件，具体为一种集成肖特基二极管的双沟道碳化硅MOSFET器件
背景技术
半导体功率器件是电力电子技术的核心元器件，通常电力电子系统要求功率器件具有低导通压降和高速开关等特性。碳化硅(SiC)材料因其临界击穿电场强度是硅的10倍，导热系数是硅的3倍，因而SiC MOSFET不管在功率密度、开关速度、损耗以及散热等方面都比硅基器件具有显著优势。通常，在MOSFET的应用中需要反并联一个快恢复续流二极管；然而，碳化硅的禁带宽度决定了其MOSFET自身反并联的PN结二极管固有导通压降约为3V，导通损耗过高；所以，在SiC MOSFET的应用中往往是将一个SiC肖特基二极管(SchottkyBarrier Diode:SBD)与其封装在一起构成一个功率模块；但是该方案将增加芯片成本、增大系统体积、引入寄生电感以及增大动态损耗等，所以，在同一芯片内集成低导通压降的反并联的快恢复二极管成为SiC MOSFET的一个重要方向。
传统的集成反并联肖特基二极管的SiC MOSFET结构都是将肖特基结制作在半导体表面或者深槽底部表面，同时需要在肖特基结的周围设置P型电场屏蔽层来抑制肖特基势垒降低效应，避免击穿电压下降；例如文献“C.T.Yen,et al.,“1700V/30A 4H-SiCMOSFET with low cut-in voltage embedded diode and room temperature boronimplanted terminatio n,”in Proc.ISPSD,2015,pp.265-268.”中公开的SiC MOSFET结构，其结构如图1所示；由于P-well通常结深较浅，屏蔽效果有限，所以肖特基势垒高度不宜过低，以免泄漏电流过大；但是，高的势垒高度将导致反向导通电阻增加。为了进一步提高电场屏蔽效果，文献“X.Li,et al.“SiC Trench MOSFET With Integrated Self-Assembled Three-Level Protection Sc hottky Barrier Diode,”IEEE Trans.ElectronDevices,vo.65,no.1,2018,pp.347–351.”中提出一种栅氧下具有浮空电场屏蔽区的SiCMOSFET，如图2所示；但是，浮空的P型电场屏蔽层将增加器件的动态电阻，增大弥勒电容，从而增大损耗，降低系统效率。
基于此，本发明提供一种新的集成肖特基二极管的双沟道碳化硅MOSFET器件。
发明内容
本发明的目的在于针对上述技术问题，提供一种集成肖特基二极管的双沟道碳化硅MOSFET器件，该器件在具有低的导通电阻、低泄漏电流、低弥勒电容以及低的反向导通电压。
为了实现上述目的，本发明采用的技术方案如下：
一种集成肖特基二极管的双沟道碳化硅MOSFET器件，包括：
N型重掺杂半导体衬底2，位于N型重掺杂半导体衬底2下的漏极金属1，位于N型重掺杂半导体衬底2上的N型耐压区3，以及位于N型耐压区3上的有源区；其特征在于，
所述有源区表面设置有第一深槽与第二深槽；所述第一深槽底部半导体内设置有第一基区5-1，所述第二深槽底部半导体内设置有第三基区5-3，所述第一深槽与第二深槽之间半导体内设置有第二基区5-2及位于第二基区5-2下方的N型半导体区4、且N型半导体区4位于第一基区5-1与第三基区5-3之间；
所述第一深槽的侧壁设置有垂直栅氧化层11-1，所述第一深槽的底部设置有水平栅氧化层11-2，所述第一深槽内设置有多晶硅栅8；所述水平栅氧化层11-2与多晶硅栅8的底面相接触，所述垂直栅氧化层11-1与多晶硅栅8的一侧相接触，所述多晶硅栅8的另一侧及顶面由钝化层9包覆；
所述第一基区5-1内设置有作为源极欧姆接触的第一基区内N型重掺杂欧姆接触区6-1与第一基区内P型重掺杂欧姆接触区7-1，所述第一基区内N型重掺杂欧姆接触区6-1与水平栅氧化层11-1相接触，且第一基区内N型重掺杂欧姆接触区6-1与第一基区内P型重掺杂欧姆接触区7-1上覆盖有源极金属10；
所述第二基区5-2内设置有作为源极欧姆接触的第二基区内N型重掺杂欧姆接触区6-2与第二基区内P型重掺杂欧姆接触区7-2，所述第二基区内N型重掺杂欧姆接触区6-2与垂直栅氧化层11-2相接触，且第二基区内N型重掺杂欧姆接触区6-2与第二基区内P型重掺杂欧姆接触区7-2上、以及第二深槽的侧壁与底部均覆盖有源极金属10。
进一步的，所述的N型半导体区4与源极金属10形成N型肖特基二极管。
当多晶硅栅8的栅极电压高于阈值电压时，能够同时在第一基区5-1中形成平面沟道，第二基区5-2中形成垂直沟道。
本发明的有益效果在于：
本发明提供一种集成肖特基二极管的双沟道碳化硅MOSFET器件，采用双沟道设计，形成两个接地的电场屏蔽区保护中间的肖特基二极管，使得肖特基结处电位能够被屏蔽的很低，从而降低泄露电流，提高击穿电压；同时，进一步降低肖特基势垒高度而不至于使得泄漏电流明显增大，进而降低肖特基二极管反向导通压降。此外，通过引入第一深槽内的平面沟道，一方面增加了沟道密度、降低了比导通电阻，另一方面，通过将浮空电场屏蔽区接地、更好地起到屏蔽肖特基结电势的效果、从而降低肖特基势垒高度、降低反向导通压降，并且接地的电场屏蔽区能够消除浮空电场屏蔽区带来的动态电阻增大、弥勒电容增大的不良影响。
附图说明
图1为传统的集成反并联肖特基二极管的SiC MOSFET器件结构示意图。
图2为现有栅氧下具有浮空电场屏蔽区的SiC MOSFET器件结构示意图。
图3为本发明实施例1提供的一种集成肖特基二极管的双沟道SiC MOSFET器件结构示意图；
图中，1为漏极金属，2为N+型半导体衬底，3为耐压区，4为N型半导体区，5-1、5-2、5-3为P型半导体基区，6-1、6-2为N型重掺杂欧姆接触区，7-1、7-2为P型重掺杂欧姆接触区，8为多晶硅栅区，9为钝化层，10为源极金属，11-1、11-2为栅氧化层。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
实施例1
本实施例提供一种集成肖特基二极管的双沟道碳化硅MOSFET器件，其结构如图3所示，具体包括：
N型重掺杂半导体衬底2，位于N型重掺杂半导体衬底2下设置的漏极金属1，位于N型重掺杂半导体衬底2上的N型耐压区3，以及位于N型耐压区3上的有源区；所述有源区用于设置MOSFET的沟道区域以及肖特基二极管区；
所述有源区表面设置有两个深槽，分别为第一深槽和第二深槽；所述第一深槽底部半导体内设置有第一基区5-1，所述第二深槽底部半导体内设置有第三基区5-3，所述第一深槽与第二深槽之间的半导体内设置有第二基区5-2及位于第二基区5-2下方的N型半导体区4、且所述N型半导体区4位于第一基区5-1与第三基区5-3之间；
所述第一深槽的侧壁设置有垂直栅氧化层11-1、用于构成垂直沟道，所述第一深槽的底部设置有水平栅氧化层11-2、用于构成水平沟道，所述第一深槽内设置有多晶硅栅8；所述水平栅氧化层11-2与多晶硅栅8的底面相接触，所述垂直栅氧化层11-1与多晶硅栅8的一侧相接触，所述多晶硅栅8的另一侧及顶面由钝化层9包覆；
所述第一基区5-1内设置有作为源极欧姆接触的第一基区内N型重掺杂欧姆接触区6-1与第一基区内P型重掺杂欧姆接触区7-1，所述N型重掺杂欧姆接触区6-1与水平栅氧化层11-1相接触，所述N型重掺杂欧姆接触区6-1与P型重掺杂欧姆接触区7-1上覆盖有源极金属10；
所述第二基区5-2内设置有作为源极欧姆接触的第二基区内N型重掺杂欧姆接触区6-2与第二基区内P型重掺杂欧姆接触区7-2，所述N型重掺杂欧姆接触区6-2与垂直栅氧化层11-2相接触，所述N型重掺杂欧姆接触区6-2与P型重掺杂欧姆接触区7-2上、以及第二深槽的侧壁与底部均覆盖有源极金属10。
从工作原理上讲：上述集成肖特基二极管的双沟道碳化硅MOSFET器件中，所述第二深槽侧壁的源极金属10与N型半导体区接触形成肖特基二极管，所述第二深槽底部的第三基区5-3和源极金属10接触，同时所述第一基区5-1和源极金属10通过第一基区内P型重掺杂欧姆接触区7-1接地，从而形成两个接地的电场屏蔽区，保护中间的肖特基二极管；由于电场屏蔽区接地，在漏极电压升高时，电场屏蔽区不会像浮空电场屏蔽区那样电位升高，从而肖特基结处电位能够被屏蔽的很低，从而降低泄露电流，提高击穿电压；并且，能够进一步降低肖特基势垒高度而不至于使得泄漏电流明显增大，进而降低肖特基二极管反向导通压降。此外，通过在传统结构中浮空的第一基区5-1处设计平面沟道，一方面提高沟道密度，降低比导通电阻；另一方面，平面沟道的引入使得传统结构中浮空的电场屏蔽区通过第一基区内P型重掺杂欧姆接触区7-1接地，从而两个电场屏蔽区均接地，有效避免浮空电场屏蔽区带来的动态电阻增大、弥勒电容增大的不良效应，降低损耗，提高效率。
以上所述，仅为本发明的具体实施方式，本说明书中所公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换；所公开的所有特征、或所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以任何方式组合。

Claims (3)

1.一种集成肖特基二极管的双沟道碳化硅MOSFET器件，包括：
N型重掺杂半导体衬底2，位于N型重掺杂半导体衬底2下的漏极金属1，位于N型重掺杂半导体衬底2上的N型耐压区3，以及位于N型耐压区3上的有源区；其特征在于，
所述有源区表面设置有第一深槽与第二深槽；所述第一深槽底部半导体内设置有第一基区5-1，所述第二深槽底部半导体内设置有第三基区5-3，所述第一深槽与第二深槽之间半导体内设置有第二基区5-2及位于第二基区5-2下方的N型半导体区4、且N型半导体区4位于第一基区5-1与第三基区5-3之间；
所述第一深槽的侧壁设置有垂直栅氧化层11-1，所述第一深槽的底部设置有水平栅氧化层11-2，所述第一深槽内设置有多晶硅栅8；所述水平栅氧化层11-2与多晶硅栅8的底面相接触，所述垂直栅氧化层11-1与多晶硅栅8的一侧相接触，所述多晶硅栅8的另一侧及顶面由钝化层9包覆；
所述第一基区5-1内设置有作为源极欧姆接触的第一基区内N型重掺杂欧姆接触区6-1与第一基区内P型重掺杂欧姆接触区7-1，所述第一基区内N型重掺杂欧姆接触区6-1与水平栅氧化层11-1相接触，且第一基区内N型重掺杂欧姆接触区6-1与第一基区内P型重掺杂欧姆接触区7-1上覆盖有源极金属10；
所述第二基区5-2内设置有作为源极欧姆接触的第二基区内N型重掺杂欧姆接触区6-2与第二基区内P型重掺杂欧姆接触区7-2，所述第二基区内N型重掺杂欧姆接触区6-2与垂直栅氧化层11-2相接触，且第二基区内N型重掺杂欧姆接触区6-2与第二基区内P型重掺杂欧姆接触区7-2上、以及第二深槽的侧壁与底部均覆盖有源极金属10。
2.按权利要求1所述集成肖特基二极管的双沟道碳化硅MOSFET器件，其特征在于，所述的N型半导体区4与源极金属10形成N型肖特基二极管。
3.按权利要求1所述集成肖特基二极管的双沟道碳化硅MOSFET器件，其特征在于，当多晶硅栅8的栅极电压高于阈值电压时，能够同时在第一基区5-1中形成平面沟道，第二基区5-2中形成垂直沟道。
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