CN113990923B - 一种集成沟道二极管的碳化硅双槽mosfet - Google Patents

一种集成沟道二极管的碳化硅双槽mosfet Download PDF

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CN113990923B
CN113990923B CN202111219760.8A CN202111219760A CN113990923B CN 113990923 B CN113990923 B CN 113990923B CN 202111219760 A CN202111219760 A CN 202111219760A CN 113990923 B CN113990923 B CN 113990923B
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罗小蓉
姜钦峰
黄俊岳
杨可萌
马臻
魏杰
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University of Electronic Science and Technology of China
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Abstract

本发明属于功率半导体技术领域，具体涉及一种集成沟道二极管的碳化硅双槽MOSFET。本发明的主要特征在于：第一：集成了沟道二极管，当器件处于续流工作模式时，沟道二极管导通实现续流功能，通过降低反向导通压降来有效抑制体二极管的导通，同时消除双极退化带来的影响；第二：通过源沟槽下方的P型区域调制电场，降低栅沟槽底部二氧化硅拐角处的电场尖峰，提高器件在阻断工作模式下的击穿电压和可靠性。

Description

一种集成沟道二极管的碳化硅双槽MOSFET
技术领域
本发明属于功率半导体技术领域，具体涉及一种集成沟道二极管的碳化硅双槽MOSFET。
背景技术
相较于传统的SiC平面型MOS器件，SiC槽栅MOS器件因其更大的沟道密度，且降低了JFET效应的影响，因而具有更低的导通电阻。然而SiC槽栅MOS器件存在栅氧化层峰值电场过大的问题，为解决这一问题，已有研究者提出双槽MOSFET，通过源沟槽下方的P型区域来调制电场，使得栅槽拐角处氧化层的峰值电场低于临界击穿值，提高器件耐压。
在转换器和逆变器系统中，通常需要一个续流二极管与开关器件反向并联。尽管使用SiC MOSFET中的体二极管作为续流二极管能够节省成本和面积，然而宽禁带SiC材料的体二极管的开启电压较大，会导致高的导通损耗；同时SiC材料中载流子复合导致的双极退化效应，会引起导通电阻与反向漏电流增大等不利影响。针对上述问题，本发明提出了一种集成了沟道二极管的器件结构，通过沟道二极管来实现反向续流，抑制体二极管的导通来避免双极退化效应，并得到更低的反向导通压降。
发明内容
本发明的目的，就是针对上述问题，提出一种集成沟道二极管的碳化硅双槽MOSFET，可以在保证MOSFET原本性能不下降的同时，避免续流二极管导通压降过大和双极退化效应这两个问题。
本发明的技术方案是：
一种集成沟道二极管的碳化硅双槽MOSFET，包括自下而上依次层叠设置的第一导电材料1、N+衬底层2、N漂移区3、JFET区4、P-body区5和源区结构，所述源区结构位于P-body区5上表面；
其特征在于，还包括源沟槽结构，所述源沟槽结构沿器件垂直方向贯穿源区结构和P-body区5后终止于JFET区4内，源沟槽结构包括P-region区6、P+区12和第一绝缘介质层11，所述P-region区6位于源沟槽下部，其底部和两侧与JFET区4接触，所述P+区12嵌入P-region区6的上部，所述第一绝缘介质层11为源沟槽结构的侧壁，第一绝缘介质层11的两侧分别与位于源沟槽结构两侧的源区结构和P-body区5接触，第一绝缘介质层11的底部与P-region区6的上表面接触；
还包括栅沟槽结构，所述栅沟槽结构沿器件垂直方向贯穿源区结构和P-body区5后终止于JFET区4内部，栅沟槽结构由第二绝缘介质层9、第三绝缘介质层14和N+多晶硅10组成，其中第二绝缘介质层9在栅沟槽的侧壁与底部，N+多晶硅10填充栅沟槽内，第三绝缘介质层14位于N+多晶硅10的上表面，所述N+多晶硅10被第二绝缘介质层9和第三绝缘介质层14包围；
所述源区结构位于源沟槽结构两侧与栅沟槽结构之间，源区结构和栅沟槽结构对称分布于源沟槽结构两侧，源区结构均包括P+源区8和位于P+源区8两侧的第一N+源区71和第二N+源区72，其中第一N+源区71与第二绝缘介质层9接触，第二N+源区72与绝缘介质层11接触；且第三绝缘介质层14还延伸至部分第一N+源区71的上表面；
还包括第二导电材料13，第二导电材料13填满源沟槽结构并覆盖P+区12和P-region区6的上表面，同时第二导电材料13还沿第一绝缘介质层11上表面向两侧延伸至覆盖源极结构上表面和第三绝缘介质层14上表面，所述第二导电材料13顶部引出为源极；
所述第二N+源区72、P-body区5、JFET区4、第一绝缘介质层11和第二导电材料13构成沟道二极管。
本发明采用集成沟道二极管，在器件处于反向续流工作模式时，沟道二极管导通实现续流功能，降低了反向导通压降并有效抑制体二极管的导通，消除双极退化带来的影响；采用双槽结构，通过源沟槽下方的P型区域调制电场，降低栅沟槽底部二氧化硅拐角处的电场尖峰，提高器件在阻断工作模式下的可靠性。
进一步的，所述P-region区6两端向上延伸，形成“U”状的P-region区6，在阻断状态下“U”状的P-region区可以更好地屏蔽氧化层中的高电场，进一步降低氧化层中的电场峰值，使器件在正向阻断时拥有更好的可靠性。
本发明的有益效果为：相比于传统的碳化硅槽栅MOSFET，本发明在器件结构中集成了沟道二极管，利用集成的沟道二极管进行续流，降低反向导通压降以抑制体二极管的开启，并避免双极退化效应，提高器件反向导通能力；源沟槽下方的P-region区能够降低氧化层中的峰值电场，提高耐压和可靠性；相较于采用集成SBD(Schottky Barrier Diode)来消除双极退化效应的方法，本发明反向漏电流更小并且具有更好的耐高温特性，且节省面积。
附图说明
图1为实施例1的结构示意图；
图2为实施例2的结构示意图；
具体实施方式
下面结合附图和实施例，对本发明技术方案进行详细描述：
实施例1
如图1所示，本实例为
一种集成沟道二极管的碳化硅双槽MOSFET，包括自下而上依次层叠设置的第一导电材料1、N+衬底层2、N漂移区3、JFET区4、P-body区5和源区结构，所述源区结构位于P-body区5上表面；
其特征在于，还包括源沟槽结构，所述源沟槽结构沿器件垂直方向贯穿源区结构和P-body区5后终止于JFET区4内，源沟槽结构包括P-region区6、P+区12和第一绝缘介质层11，所述P-region区6位于源沟槽下部，其底部和两侧与JFET区4接触，所述P+区12嵌入P-region区6的上部，所述第一绝缘介质层11为源沟槽结构的侧壁，第一绝缘介质层11的两侧分别与位于源沟槽结构两侧的源区结构和P-body区5接触，第一绝缘介质层11的底部与P-region区6的上表面接触；
还包括栅沟槽结构，所述栅沟槽结构沿器件垂直方向贯穿源区结构和P-body区5后终止于JFET区4内部，栅沟槽结构由第二绝缘介质层9、第三绝缘介质层14和N+多晶硅10组成，其中第二绝缘介质层9在栅沟槽的侧壁与底部，N+多晶硅10填充栅沟槽内，第三绝缘介质层14位于N+多晶硅10的上表面，所述N+多晶硅10被第二绝缘介质层9和第三绝缘介质层14包围；
所述源区结构位于源沟槽结构两侧与栅沟槽结构之间，源区结构和栅沟槽结构对称分布于源沟槽结构两侧，源区结构均包括P+源区8和位于P+源区8两侧的第一N+源区71和第二N+源区72，其中第一N+源区71与第二绝缘介质层9接触，第二N+源区72与绝缘介质层11接触；且第三绝缘介质层14还延伸至部分第一N+源区71的上表面；
还包括第二导电材料13，第二导电材料13填满源沟槽结构并覆盖P+区12和P-region区6的上表面，同时第二导电材料13还沿第一绝缘介质层11上表面向两侧延伸至覆盖源极结构上表面和第三绝缘介质层14上表面，所述第二导电材料13顶部引出为源极；
所述第二N+源区72、P-body区5、JFET区4、第一绝缘介质层11和第二导电材料13构成沟道二极管。本例的工作原理是：
通过在原有源沟槽上部形成一浅槽，得到集成的沟道二极管结构，在MOSFET反向续流工作时，P-body区5感应出负电势，在源电极零电位的作用下形成反型电子沟道，起到反向续流的功能，同时通过降低反向导通压降来抑制体二极管导通，并避免双极退化效应；源沟槽下方的P-region区能够调制电场，使源沟槽处的氧化层中的峰值电场低于临界击穿值，提高器件在阻断工作模式下的可靠性。
实施例2
如图2所示，本实例与实例1相比区别在于，所述P-region区6两端向上延伸，形成“U”状的P-region区，且P-region区6的上表面平齐于或低于P-body区5的下表面，形成阶梯状的源沟槽结构。在阻断状态下“U”状的P-region区可以更好地屏蔽氧化层中的高电场，进一步降低氧化层中的电场峰值，使器件在正向阻断时拥有更好的可靠性。

Claims (2)

1.一种集成沟道二极管的碳化硅双槽MOSFET，包括自下而上依次层叠设置的第一导电材料(1)、N+衬底层(2)、N漂移区(3)、JFET区(4)、P-body区(5)和源区结构，所述源区结构位于P-body区(5)上表面；
其特征在于，还包括源沟槽结构，所述源沟槽结构沿器件垂直方向贯穿源区结构和P-body区(5)后终止于JFET区(4)内，源沟槽结构包括P-region区(6)、P+区(12)和第一绝缘介质层(11)，所述P-region区(6)位于源沟槽下部，其底部和两侧与JFET区(4)接触，所述P+区(12)嵌入P-region区(6)的上部，所述第一绝缘介质层(11)为源沟槽结构的侧壁，第一绝缘介质层(11)的两侧分别与位于源沟槽结构两侧的源区结构和P-body区(5)接触，第一绝缘介质层(11)的底部与P-region区(6)的上表面接触；
还包括栅沟槽结构，所述栅沟槽结构沿器件垂直方向贯穿源区结构和P-body区(5)后终止于JFET区(4)内部，栅沟槽结构由第二绝缘介质层(9)、第三绝缘介质层(14)和N+多晶硅(10)组成，其中第二绝缘介质层(9)位于栅沟槽的侧壁与底部，N+多晶硅(10)填充栅沟槽内，第三绝缘介质层(14)位于N+多晶硅(10)的上表面，所述N+多晶硅(10)被第二绝缘介质层(9)和第三绝缘介质层(14)包围；
所述源区结构位于源沟槽结构两侧与栅沟槽结构之间，源区结构和栅沟槽结构对称分布于源沟槽结构两侧，源区结构均包括P+源区(8)和位于P+源区(8)两侧的第一N+源区(71)和第二N+源区(72)，其中第一N+源区(71)与第二绝缘介质层(9)接触，第二N+源区(72)与绝缘介质层(11)接触；且第三绝缘介质层(14)还延伸至部分第一N+源区(71)的上表面；
还包括第二导电材料(13)，第二导电材料(13)填满源沟槽结构并覆盖P+区(12)和P-region区(6)的上表面，同时第二导电材料(13)还沿第一绝缘介质层(11)上表面向两侧延伸至覆盖源极结构上表面和第三绝缘介质层(14)上表面，所述第二导电材料(13)顶部引出为源极；
所述第二N+源区(72)、P-body区(5)、JFET区(4)、第一绝缘介质层(11)和第二导电材料(13)构成沟道二极管。
2.根据权利要求1所述的任意一种集成沟道二极管的碳化硅双槽MOSFET，其特征在于，所述P-region区(6)两端向上延伸，形成“U”状的P-region区(6)，且P-region区(6)的上表面平齐于或低于P-body区(5)的下表面，形成阶梯状的源沟槽结构。
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