CN113054016B - 一种碳化硅mosfet器件的元胞结构及功率半导体器件 - Google Patents

一种碳化硅mosfet器件的元胞结构及功率半导体器件 Download PDF

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CN113054016B
CN113054016B CN201911370082.8A CN201911370082A CN113054016B CN 113054016 B CN113054016 B CN 113054016B CN 201911370082 A CN201911370082 A CN 201911370082A CN 113054016 B CN113054016 B CN 113054016B
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silicon carbide
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CN113054016A (zh
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王亚飞
陈喜明
郑昌伟
焦莎莎
李诚瞻
罗海辉
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Abstract

本发明公开了一种碳化硅MOSFET器件的元胞结构，包括：位于衬底层上的漂移区，位于漂移区内的第二导电类型阱区和第一JFET区，位于阱区表面内的增强区，位于第一导电类型增强区、阱区以及第一JFET区上且与它们同时接触的栅极绝缘层及其之上的栅极，位于增强区上的源极金属，位于第二电类型增强区和漂移区上的肖特基金属，位于肖特基金属之间漂移区表面的第二JFET区，以及漏极金属。本发明通过在碳化硅MOSFET元胞结构内集成SBD，抑制了体二极管的开启，提高了器件可靠性，通过SBD集成于MOSFET元胞结构的第二导电类型增强区之间，增加了芯片整体功率密度，且肖特基金属与第二JFET区进行间隔设置，实现了导通电阻和漏电流较好的折中关系。

Description

一种碳化硅MOSFET器件的元胞结构及功率半导体器件
技术领域
本发明涉及功率半导体器件领域,尤其涉及一种集成了肖特基二极管(SBD)的碳化硅金属氧化物半导体场效应晶体管(MOSFET)器件的元胞结构及功率半导体器件。
背景技术
随着节能减排、新能源并网、智能电网的发展，第三代半导体碳化硅(SiC)功率器件日益得到重视，其主要优势在于其击穿电场强度是传统硅器件的10倍，或相同电压/电流等级下，比导通电阻是硅器件的近千分之一。SiC器件开关频率是硅器件的20倍，可减小电路中储能元件的体积。理论上，SiC器件可以在600摄氏度以上的高温环境下工作，且具有优异的抗辐射性能，可大大提高系统的可靠性。
然而受限于现有制程技术，在碳化硅双极器件中的双极退化现象会导致器件载流子寿命显著降低并使器件的压降增大、反向偏置漏电流增大，不利于碳化硅器件的可靠性。现有的平面栅N型沟道结构MOSFET还寄生了一个体二极管，如图1，包括：N+衬底层101、N-漂移区102、P阱区103、N+源区104、P+区105、JFET区106、栅极氧化层107、栅极多晶硅108、源极金属109、漏极金属110、体PIN二极管111。
在MOSFET反向偏置时，为抑制体二极管开启引起双极退化，需采用SBD与MOSFET反并联使用，作为其续流二极管。正常情况下，在芯片级别反并联SBD会增加模块封装的成本并会在SBD端引入额外的键合线及杂散电感，导致模块电气性能的下降。
发明内容
本发明所要解决的技术问题之一是平面栅N型沟道结构碳化硅MOSFET寄生了一个体二极管，体二极管开通时会引起器件的双极退化，导致器件载流子寿命显著降低，并使器件的压降增大、反向偏置漏电流增大，不利于碳化硅器件的可靠性。
本发明所要解决的技术问题之二是在芯片级别反并联SBD会增加模块封装的成本，并会在SBD端引入额外的键合线及杂散电感，导致模块电气性能的下降。
为了解决上述技术问题，本发明提供了一种具有三维结构的碳化硅MOSFET器件的元胞结构及功率半导体器件，在元胞级别集成了SBD，改善了碳化硅双极退化现象，提高了芯片可靠性，并降低了模块封装成本，提高了模块电气特性。
本发明提供了一种碳化硅MOSFET器件的元胞结构，包括：
位于第一导电类型衬底层上的第一导电类型漂移区；
在沿元胞结构表面横向延伸的一端，所述漂移区的表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区和第一JFET区；
在所述阱区远离所述第一JFET区的一侧，所述阱区的表面内设置有增强区，所述增强区包括沿元胞结构表面横向邻接的第一导电类型增强区和第二导电类型增强区，其中，所述第一导电类型增强区比所述第二导电类型增强区更加靠近所述第一JFET区；
所述第一导电类型增强区、所述阱区的未被所述增强区覆盖的表面以及所述第一JFET区上设置有与它们同时接触的栅极绝缘层，所述栅极绝缘层上设置有栅极；
所述增强区上设置有源极金属，其中，所述源极金属与其下方的所述增强区形成欧姆接触，同时不与所述漂移区和所述栅极接触；
在沿元胞结构表面横向延伸的另一端，所述漂移区于未被所述阱区和所述第二JFET区覆盖的表面上设置有肖特基金属，所述肖特基金属与其下方的所述漂移区形成肖特基接触；
以及位于所述衬底下方的漏极金属。
根据本发明的实施例，所述肖特基金属还延伸至所述第二导电类型增强区的上方，与所述第二导电类型增强区形成欧姆接触。
根据本发明的实施例，所述肖特基金属与所述源极金属直接接触；
或者，所述肖特基金属与所述源极金属分隔设置，通过设置在元胞结构表面的二次金属进行连接。
根据本发明的实施例，所述漂移区在未被所述阱区、所述第二导电类型增强区和所述肖特基金属覆盖的的区域的表面内设置有第二JFET区。
根据本发明的实施例，所述肖特基金属的边界与所述第二JFET区的边界接触或接近。
根据本发明的实施例，所述第一JFET区和所述阱区在所述漂移区沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
根据本发明的实施例，所述增强区在所述漂移区表面从所述阱区内元胞结构表面纵向延伸至元胞结构表面纵向的另一端，相应地，所述源极金属在所述增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端，所述栅极绝缘层在所述第一JFET区、所述阱区未被所述增强区覆盖表面及所述第一导电类型增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
根据本发明的实施例，所述第二导电类型增强区的深度大于或等于所述第一导电类型增强区的深度。
根据本发明的实施例，所述第一和第二JFET区的浓度相等且高于所述漂移区的浓度。
根据本发明的实施例，
所述衬底的浓度范围为1×1018～1×1019cm-3；
所述漂移区的浓度范围为1×1014～5×1016cm-3；
所述阱区的浓度范围为1×1016～5×1018cm-3；
所述第一和第二JFET区的浓度范围为1×1015～5×1017cm-3；
所述增强区的浓度范围为大于1×1019cm-3；
所述栅极的浓度为大于等于1×1018cm-3。
本发明还提供了一种碳化硅MOSFET功率半导体器件，所述功率半导体器件设置有若干以上内容中任一项所述的碳化硅MOSFET器件的元胞结构；其中，所述元胞结构的形状为条形、四边形或六边形。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
1、本发明提供了一种碳化硅MOSFET元胞结构，通过在元胞级别集成SBD，用作器件反偏时的续流二极管，有效抑制了体二极管的开启，改善了MOSFET器件电特性退化情况，提高了器件可靠性，
2、本发明通过将SBD集成于MOSFET元胞结构的P+增强区之间，SBD部分和MOSFET部分共用部分有源区和终端区面积，提高了器件面积利用率，增加了器件整体功率密度，而肖特基金属与JFET掺杂区域在三维方向进行间隔设置，降低了SBD导通电阻以及降低SBD反向偏置时的漏电流，实现了较好的折中关系。
3、本发明通过在元胞内集成SBD，使模块封装时无需额外再封装SBD，降低了键合线的寄生电感及模块封装成本。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1示出了传统的平面栅N沟道型MOSFET及寄生体二极管结构剖面图；
图2是本发明示例的集成了SBD的三维MOSFET器件的元胞结构示意图；
图3是本发明示例的集成了SBD的三维MOSFET器件的元胞结构整体俯视图；
图4是本发明示例的MOSFET器件的元胞结构漂移区表面的剖面俯视图；
图5是本发明示例的集成了SBD的三维MOSFET元胞结构A-A’剖面图；
图6是本发明示例的集成了SBD的三维MOSFET元胞结构B-B’剖面图；
图7是本发明示例的集成了SBD的三维MOSFET元胞结构C-C’剖面图；
图8是本发明示例的集成了SBD的三维MOSFET元胞结构D-D’剖面图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
第一实施例
图2为本实施例集成了SBD的三维MOSFET器件的元胞结构示意图，如图2所示，包括：第一导电类型衬底层2、第一导电类型漂移区3、第二导电类型阱区4、第一JFET区51、第二JFET区52、第一导电类型增强区6、第二导电类型增强区7、栅极绝缘层8、栅极9、源极金属10、肖特基金属11、漏极金属12。
图3为本实施例集成了SBD的三维MOSFET器件的元胞结构整体俯视图；
图4是本发明示例的MOSFET器件的元胞结构漂移区表面的剖面俯视图；
图5是本发明示例的集成了SBD的三维MOSFET元胞结构A-A’剖面图；
图6是本发明示例的集成了SBD的三维MOSFET元胞结构B-B’剖面图；
图7是本发明示例的集成了SBD的三维MOSFET元胞结构C-C’剖面图；
图8是本发明示例的集成了SBD的三维MOSFET元胞结构D-D’剖面图；
在本实施例中，集成了SBD的三维MOSFET器件的元胞结构以正视图的第一JFET区51为基点和起始端进行描述，对应的另一端为末端，元胞结构的横向方向定义为正视图的水平方向，其中，横向起始端为正视图水平方向的最右端，横向末端为正视图水平方向的最左端，右视图的水平方向定义为元胞结构的纵向方向，其中，纵向起始端为右视图水平方向的最左端，纵向末端为右视图水平方向的最右端。
本说明书中的第一导电类型衬底层2可以包括各种半导体元素，例如单晶、多晶或非晶结构的硅或硅锗，也可以包括混合的半导体结构，例如碳化硅、氮化镓、磷化铟、砷化镓、合金半导体或其组合，在此不做限定。在本实施例中的第一导电类型衬底层2优选采用碳化硅衬底，可采用N型或P型碳化硅衬底，在本实施例中以N型衬底为例进行说明。
本实施例第一导电类型为N型，第二导电类型为P型。
其中JFET为结型场效应晶体管的缩写(Junction Field-Effect Transistor，JFET)。
本实施例提供了一种碳化硅MOSFET器件的元胞结构，包括：
位于第一导电类型衬底层2上的第一导电类型漂移区3；
在沿元胞结构表面横向延伸的一端，漂移区3的表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区4和第一JFET区51；
在阱区远离第一JFET区51的一侧，阱区4的表面内设置有增强区，增强区包括沿元胞结构表面横向邻接的第一导电类型增强区6和第二导电类型增强区7，其中，第一导电类型增强区6比第二导电类型增强区7更加靠近第一JFET区51；
第一导电类型增强区6、阱区4的未被增强区覆盖的表面以及第一JFET区51上设置有与它们同时接触的栅极绝缘层8，栅极绝缘层8上设置有栅极9；
增强区上设置有源极金属10，其中，源极金属10与其下方的增强区形成欧姆接触，同时不与漂移区3和栅极9接触；
在沿元胞结构表面横向延伸的另一端，漂移区3于未被阱区4和第二JFET区52覆盖的表面上设置有肖特基金属11，肖特基金属11与其下方的漂移区3形成肖特基接触，同时肖特基金属11与源极金属10接触；
以及位于衬底2下方的漏极金属12。
本实施例中，肖特基金属11还延伸至所述第二导电类型增强区7的上方，与所述第二导电类型增强区7形成欧姆接触。
本实施例中，肖特基金属11与源极金属10直接接触；
或者，肖特基金属11与源极金属10分隔设置，通过设置在元胞结构表面的二次金属进行连接。
本实施例中，漂移区3在未被所述阱区4、第二导电类型增强区7和肖特基金属11覆盖的的区域的表面内设置有第二JFET区52。
本实施例中，肖特基金属11的边界与所述第二JFET区52的边界接触或接近。
本实施例中，第一JFET区51和阱区4在漂移区3沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
本实施例中，增强区在漂移区3表面从阱区4内元胞结构表面纵向延伸至元胞结构表面纵向的另一端，相应地，源极金属10在增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端，栅极绝缘层8在第一JFET区51、阱区4未被所述增强区覆盖表面及第一导电类型增强区6表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
本实施例中，第二导电类型增强区7的深度大于或等于第一导电类型增强区6的深度。
本实施例中，第一JFET区51和第二JFET区52的浓度相等且高于漂移区3的浓度。
具体地，在第一导电类型衬底层2上设置有第一导电类型漂移区3，在沿元胞结构表面纵向的起始端，在漂移区3表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区4和第一JFET区51，第一JFET区51位于元胞结构横向的起始端，即元胞结构正视图水平方向的最右端，第二导电类型阱区4与第一JFET区5在元胞结构的横向方向上接触；在阱区4表面内设置有增强区，其中阱区4的表面未被增强区完全覆盖，增强区包含第一导电类型增强区6和第二导电类型增强区7，且第一导电类型增强区6和第二导电类型增强区7在元胞结构的横向上邻接及接触，第一导电类型增强区6比第二导电类型增强区7更加靠近第一JFET区51，第二导电类型增强区7位于远离第一JFET区51的元胞结构横向的末端，即元胞结构正视图水平方向的最左端。其中，第一JFET区51和阱区4在漂移区3沿元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端。
第二导电类型增强区7在漂移区3表面从阱区4内沿元胞结构表面从元胞结构纵向起始端延伸至元胞结构纵向的末端，即从元胞结构右视图水平方向的最左端延伸至最右端。
在本实施例中，MOSFET器件包含一个较高浓度的第一导电类型衬底2，浓度范围为1×1018～1×1019cm-3。在第一导电类型衬底层2上设置有第一导电类型漂移区3，该漂移区3浓度范围为1×1014～5×1016cm-3，具体的浓度可以根据器件的耐压要求来进行优化设置。第二导电类型阱区4的浓度范围设置为1×1016～5×1018cm-3；第一JFET区51及第二JFET区52浓度范围设置为1×1015～5×1017cm-3，且两个JFET区浓度设置为高于漂移区3的浓度，有利于改善碳化硅双极退化现象，并提高器件的可靠性；元胞结构中的增强区浓度范围均设置为大于1×1019cm-3，且第二导电类型增强区7的深度设置为大于所述第一导电类型增强区6的深度。
本实施例中，位于第一JFET区51、第二导电类型阱区4以及第一导电类型增强区6之上且与它们同时接触的栅极绝缘层8，其厚度设置为≥50nm，栅极9沉积在栅极绝缘层8之上，掺杂类型为N型，栅极材料设置为金属或多晶硅，栅极9浓度为大于等于1×1018cm-3。栅极9与源极金属10通过高绝缘的层间介质进行隔离。其中第一导电类型增强区6在阱区4表面设置为沿元胞结构表面从纵向的起始端向末端延伸，即从元胞结构右视图的最左端向右端延伸，在本实施例中，一直延伸到元胞结构纵向的末端。
在增强区上设置有用于形成欧姆接触的源极金属10，源极金属10同时接触第一导电类型增强区6和第二导电类型7，且不与漂移区3接触，源极金属10也不与栅极绝缘层8和栅极9接触，源极金属10沿元胞结构表面从纵向的起始端延伸至末端，即从元胞结构右视图的最左端延伸到最右端；源极金属欧姆接触材料设置为具有低接触电阻率的金属或合金，优选为铝、镍，或铝镍合金。
在元胞结构横向的末端，即元胞结构正视图的最左端，在没有被阱区4覆盖的漂移区3的表面上设置有第二JFET区52，漂移区3于未被阱区4和第二JFET区52覆盖的表面与第二导电类型增强区7未被源极金属10覆盖的表面上设置有肖特基金属11，肖特基金属11与其下方的漂移区3形成低势垒的肖特基接触，并与第二导电类型增强区7形成欧姆接触，降低了SBD一部分的导通电阻。同时肖特基金属11与源极金属10接触，肖特基金属11与源极金属10接触部位于第二导电类型增强区7之上。其中，在沿元胞结构表面横向延伸的另一端，第二JFET区52设置于漂移区3于未被阱区4覆盖的表面的中间部位。在沿元胞结构表面横向延伸的另一端，所述漂移区于未被所述第二JFET区和所述第二导电类型增强区覆盖的表面被所述第二JFET区至少分隔为两部分，在本实施例中，相应地，所述肖特基金属也至少分隔设置为两部分。肖特基金属接触材料设置为具有低接触电阻率的金属或合金，优选为钛、铝、镍，或钛铝镍任意组份合成的合金。
增强区在漂移区3表面从阱区4内元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端，相应地，栅极绝缘层8在第一JFET区51、阱区4未被所述增强区覆盖表面及第一导电类型增强区6表面上沿元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端，源极金属10在增强区表面上沿元胞结构表面纵向的起始端延伸至元胞结构表面纵向的末端。
肖特基金属11与第二JFET区52掺杂区域进行错位的间隔设置，肖特基金属11的边界可设置为与第二JFET区52掺杂区域的边界接触或接近，可降低SBD导通电阻。由于肖特基金属下方并没有设置JFET掺杂区，可以降低SBD反向偏置时的漏电流，以实现SBD通态电阻与反向偏置漏电流之间较好的折中关系。
本实施例中，第一JFET区51和阱区4在漂移区3沿元胞结构表面纵向起始端延伸至元胞结构表面纵向的末端，由于把SBD集成于MOSFET元胞结构的JFET区，进而提高了器件的面积利用率，增加了器件整体功率密度。
在衬底2下方还设置有漏极金属12。
漏极金属12、第一导电类型衬底层2、第一导电类型漂移区3、第二导电类型阱区4、肖特基金属11即构成了MOSFET元胞内置的SBD，可以用作MOSFET反偏时的续流二极管，使得MOSFET模块封装时无需额外封装SBD，降低了器件的封装成本，同时也减少了因键合引线产生的寄生电感。同时由于在元胞内集成了SBD，提高了MOSFET器件体二极管的开启电压，改善了MOSFET器件电特性退化情况，提高了器件可靠性。
此外，根据器件的具体应用场合或者基于不同的设计考虑，肖特基金属11还能设置为覆盖在源极金属10上方进行连接，或者肖特基金属11设置为与源极金属10分离，并通过元胞结构表面的二次金属进行连接。
综上所述，
1、本实施例提供了一种三维结构的碳化硅MOSFET元胞结构，通过在元胞级别集成SBD，用作器件反偏时的续流二极管，有效抑制了体二极管的开启，改善了MOSFET器件电特性退化情况，提高了器件可靠性，
2、本实施例通过将SBD集成于MOSFET元胞结构的的P+增强区之间，SBD部分和MOSFET部分共用部分有源区和终端区面积，提高了器件面积利用率，增加了器件整体功率密度，而肖特基金属与JFET掺杂区域在三维方向进行间隔设置，优化了各区域的分布，降低了SBD导通电阻以及降低SBD反向偏置时的漏电流，实现了较好的折中关系。
第二实施例
本发明还提供了一种碳化硅MOSFET功率半导体器件，功率半导体器件设置有若干以上内容中任一项的碳化硅MOSFET器件的元胞结构；其中，元胞结构的形状为条形、四边形或六边形。
综上所述，
本实施例通过在元胞内集成SBD，使模块封装时无需额外再封装SBD，降低了键合线的寄生电感及模块封装成本。
虽然本发明公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所述技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，本发明的保护范围并不局限于文中公开的特定实施例，而是包括落入权利要求范围内的所有技术方案。

Claims (11)

1.一种碳化硅MOSFET器件的元胞结构，其特征在于，包括：
位于第一导电类型衬底层上的第一导电类型漂移区；
在沿元胞结构表面横向延伸的一端，所述漂移区的表面内设置有沿元胞结构表面横向邻接的第二导电类型阱区和第一JFET区；
在所述阱区远离所述第一JFET区的一侧，所述阱区的表面内设置有增强区，所述增强区包括沿元胞结构表面横向邻接的第一导电类型增强区和第二导电类型增强区，其中，所述第一导电类型增强区比所述第二导电类型增强区更加靠近所述第一JFET区；
所述第一导电类型增强区、所述阱区的未被所述增强区覆盖的表面以及所述第一JFET区上设置有与它们同时接触的栅极绝缘层，所述栅极绝缘层上设置有栅极；
所述增强区上设置有源极金属，其中，所述源极金属与其下方的所述增强区形成欧姆接触，同时不与所述漂移区和所述栅极接触；
在沿元胞结构表面横向延伸的另一端，所述漂移区的表面上设置有第二JFET区,且在沿元胞结构表面横向延伸的另一端，所述漂移区于未被所述阱区和所述第二JFET区覆盖的表面上设置有肖特基金属，所述肖特基金属与其下方的所述漂移区形成肖特基接触；以及
位于所述衬底下方的漏极金属。
2.根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其特征在于，
所述肖特基金属还延伸至所述第二导电类型增强区的上方，与所述第二导电类型增强区形成欧姆接触。
3.根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其特征在于：
所述肖特基金属与所述源极金属直接接触；
或者，所述肖特基金属与所述源极金属分隔设置，通过设置在元胞结构表面的二次金属进行连接。
4.根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其特征在于：
所述漂移区在未被所述阱区、所述第二导电类型增强区和所述肖特基金属覆盖的区域的表面内设置有第二JFET区。
5.根据权利要求4所述的碳化硅MOSFET器件的元胞结构，其特征在于，所述肖特基金属的边界与所述第二JFET区的边界接触或接近。
6.根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其特征在于，
所述第一JFET区和所述阱区在所述漂移区沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
7.根据权利要求2所述的碳化硅MOSFET器件的元胞结构，其特征在于，
所述增强区在所述漂移区表面从所述阱区内元胞结构表面纵向延伸至元胞结构表面纵向的另一端，相应地，所述源极金属在所述增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端，所述栅极绝缘层在所述第一JFET区、所述阱区未被所述增强区覆盖表面及所述第一导电类型增强区表面上沿元胞结构表面纵向延伸至元胞结构表面纵向的另一端。
8.根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其特征在于，所述第二导电类型增强区的深度大于或等于所述第一导电类型增强区的深度。
9.根据权利要求1所述的碳化硅MOSFET器件的元胞结构，其特征在于，所述第一和第二JFET区的浓度相等且高于所述漂移区的浓度。
10.根据权利要求9所述的碳化硅MOSFET器件的元胞结构，其特征在于，
所述衬底的浓度范围为1×1018～1×1019cm-3；
所述漂移区的浓度范围为1×1014～5×1016cm-3；
所述阱区的浓度范围为1×1016～5×1018cm-3；
所述第一和第二JFET区的浓度范围为1×1015～5×1017cm-3；
所述增强区的浓度范围为大于1×1019cm-3；
所述栅极的浓度为大于等于1×1018cm-3。
11.一种碳化硅MOSFET功率半导体器件，其特征在于，所述功率半导体器件设置有若干如权利要求1至10中任一项所述的碳化硅MOSFET器件的元胞结构；其中，所述元胞结构的形状为条形、四边形或六边形。
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