CN110473872A - 一种带有多数载流子二极管的碳化硅mos器件 - Google Patents

一种带有多数载流子二极管的碳化硅mos器件 Download PDF

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CN110473872A
CN110473872A CN201910971209.5A CN201910971209A CN110473872A CN 110473872 A CN110473872 A CN 110473872A CN 201910971209 A CN201910971209 A CN 201910971209A CN 110473872 A CN110473872 A CN 110473872A
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黄兴
陈欣璐
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Pinger Semiconductor (hangzhou) Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

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Abstract

本发明提供一种带有多数载流子二极管的碳化硅MOS器件。当MOS器件关断时,本发明通过引入多数载流子二极管和PN结二极管并联,同时利用多数载流子二极管其开启电压低、单极性电流导电的特点和PN结二极管导通电流大、耐压高的特点,在降低了器件在反向续流时的导通损耗的同时提高了反向续流能力和击穿电压,降低了反向恢复电荷并提高了碳化硅MOS器件的可靠性和集成性。当碳化硅MOS器件导通时,为了减低导通电阻从而降低MOS管的导通损耗,本发明在有源区中加入电流加强注入区,减小由于外延掺杂浓度过低而导致的JFET电阻过大的问题。

Description

一种带有多数载流子二极管的碳化硅MOS器件
技术领域
本发明属于半导体领域,具体涉及一种带有多数载流子二极管的碳化硅MOS器件。
背景技术
碳化硅(SiC)是目前发展最快的宽禁带功率半导体材料,使用碳化硅材料制作的MOS场效应晶体管功率器件比Si器件能够承受更高的电压和更快的开关速度。目前,当MOS器件关断时,碳化硅场效应晶体管中寄生的体二极管由于开启电压大,使得MOS器件在续流应用过程中导通损耗变高。因此采用集成多数载流子二极管在碳化硅MOS器件中可以解决这一问题。在现有技术中,已经有采用使用肖特基二极管作为寄生体二极管来减小开启电压的方法,但这一方法同样存在缺陷。首先,肖特基二管的反向漏电大,如果在器件设计时寄生肖特基二极管占有的面积过大,会影响MOS器件的反向击穿电压。其次,肖特基二极管在大电流时的自身压降过大,会使得当续流的电流较大时,在肖特基二极管上的压降损耗非常大。同时,当MOS器件开通时,由于碳化硅外延掺杂浓度较低,使得碳化硅MOS中的JFET电阻占总导通电阻的比例较大,增加MOS器件的导通损耗。
发明内容
针对现有技术的缺陷,本发明提供一种带有多数载流子二极管的碳化硅MOS器件。当MOS器件关断时,本发明通过引入多数载流子二极管和PN结二极管并联,同时利用多数载流子其开启电压低、单极性电流导电的特点和PN结二极管导通电流大、漏电流小的特点,在降低了器件在反向续流时的导通损耗的同时提高了反向续流能力和击穿电压,降低了反向恢复电荷并提高了碳化硅MOS器件的可靠性和集成性。当碳化硅MOS器件导通时,为了减低导通电阻从而降低MOS管的导通损耗,本发明在有源区中加入电流加强注入区,减小由于外延掺杂浓度过低而导致的JFET电阻过大的问题。
本发明提供一种带有多数载流子二极管的碳化硅MOS器件,包括:
碳化硅衬底(001),该衬底材料的掺杂类型为第一导电类型,在碳化硅衬底(001)的正面和背面依次设有第一导电类型半导体漂移区(002)和第一电极(003)。漂移区(002)的顶层设有第一导电类型电流加强注入区(004),电流加强注入区(004)上方设有栅电极(005),电流加强注入区(004)和栅电极(005)之间设有栅介质层(006)。在栅电极(005)两侧的电流加强注入区(004)内部顶层设有与栅介质层(006)相连的第二导电类型基区(007),基区(007)内部设有与栅介质层(006)相连的第一导电类型半导体重掺杂源区(008),基区(007)内部顶层设有第二导电类型半导体重参杂体区(009)。在电流加强注入区(004)中存在第二导电类型结势垒注入区(012),形成多数载流子二极管和PN结二极管,与MOS器件并联。源区(008)和体区(009)与第二电极(010)接触并形成欧姆接触,第二电极(010)与栅电极(005)之间有极间介质层(011)隔离。
其中,在所述的电流加强注入区(004)的上表面与第二电极接触为肖特基或异质结接触,形成新的体寄生二极管,其开启电压较低,减小二极管的导通损耗。另外在电流加强注入区(004)中有第二导电类型结势垒注入区(012)形成PN结二极管,与多数载流子二极管形成并联的体二极管,在大电流时,所述PN结二极管提供空穴注入,使得体二级管能够通过更高密度的电流,并产生更低的通态压降。
附图说明
图1为本发明实施例一的器件结构纵切图。
图2为本发明实施例一的俯视元胞图。
图3为本发明实施例一的俯视版图。
图4为本发明实施例一的另一种俯视版图。
图5为本发明实施例一的PN结二极管和肖特基二极管并联示意图。
图6为本发明实施例一的体二极管I-V曲线和现有技术肖特基二极管I-V曲线对比图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合实施例并参考附图,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
本发明的实施例一如图1所示,碳化硅衬底(001)、漂移区(002)、电流加强注入区(004)和源区(008)均为N型掺杂,其中衬底(001)和源区(008)为重掺杂,浓度可以大于1E18cm-3,漂移区(002)为轻掺杂,浓度可以为8E15cm-3,而电流加强注入区(004)掺杂浓度高于漂移区,在1E17cm-3左右。基区(007)、体区(009)和结势垒注入区(012)为P型掺杂,其中基区(007)为轻掺杂,浓度比漂移区(002)浓度稍高在1E16-1E17 cm-3,体区(009)为重掺杂浓度高于1E18 cm-3
本发明的实施例一中,栅电极(005)为多晶硅,栅极介质(006)为二氧化硅;背面第一电极(003)为Ti/Ni/Ag与碳化硅衬底退火后形成欧姆接触;正面第一层第二电极(010)金属为镍,其中与N型重掺杂源区(008)、P型重掺杂体区(009)和P型掺杂结势垒注入区(012)退火后形成镍硅合金的欧姆接触(图中未示出),与N型电流加强注入区(004)在相同退火条件下形成肖特基接触,从而形成多数载流子二极管,与结势垒注入区(012)所形成的PN结二极管并联,两个二极管并联示意图如图5所示。正面二电极(010)加厚金属为AlCu。
图2是实施例一的元胞俯视图,图中电流加强区(204)为正方形并铺满整个区域。栅电极(205)为空心正方形,下方是N型重掺杂的源区(208)和 P型轻掺杂的基区(207),栅电极(205)的内边缘落在N型掺杂的源区(208)中。源区(208)也为空心正方形,内边缘里面为同为空心正方形的P型重掺杂体区(209)。体区(209)内部是实心正方形P型重掺杂的结势垒注入区(212)。
图3是实施例一的版图,采用错落分布图2所示的元胞结构。
图4是实施例一的版图,采用顺序分布图2所示的元胞结构。
图6是实施例一中带有多数载流子体二极管的I-V曲线和肖特基二极管的I-V曲线的对比图。从图中可以看出,肖特基二极管虽然开启电压小,但是在大电流时产生的压降大;而PN二极管虽然开启电压大,但是由于存在空穴注入机理,所以在大电流时产生的压降小。本实施例使另个二极管并联,取两种二极管的优势。
本发明的实施例二是实施例一的变形方案,第二电极(010)为多晶硅,与重掺杂区域形成欧姆接触,与轻掺杂区域形成异质结接触,在局部形成异质结二极管,与结势垒注入区(012)形成的PN结二极管并联形成体二极管。

Claims (9)

1.一种带有多数载流子二极管的碳化硅MOS器件,其特征在于,包括:
碳化硅衬底,该衬底材料的掺杂类型为第一导电类型;
在碳化硅衬底的正面和背面依次设有第一导电类型半导体漂移区和第一电极;
漂移区的顶层在有源区设有第一导电类型电流加强注入区;
电流加强注入区上方设有栅电极,电流加强注入区和栅电极之间设有栅介质层;
在栅电极两侧的电流加强注入区内部顶层设有与栅介质层相连的第二导电类型基区,基区内部设有与栅介质层相连的第一导电类型半导体重掺杂源区,基区内部顶层设有第二导电类型半导体重参杂体区;
在所述电流加强注入区存在第二导电类型结势垒注入区,与第二电极接触后形成多数载流子二极管和PN结二极管,与MOS器件并联;
源区和体区与第二电极接触并形成欧姆接触;
第二电极与栅电极之间有极间介质层隔离。
2.根据权利要求1所述的带有多数载流子二极管的碳化硅MOS器件,其特征在于,在所述的电流加强注入区和的上表面接触界面处设有第一导电类型载流子势垒,其势垒高度范围在0.3eV到2.7eV之间。
3.根据权利要求1所述的带有多数载流子二极管的碳化硅MOS器件,其特征在于,其第一电极和第二电极可为Ti、TiN、TiW、Ag、Al、Ni、Pt、Cu、Si或Au任意一种或多种的组合。
4.根据权利要求1所述的带有多数载流子二极管的碳化硅MOS器件,其特征在于,所述电流加强注入区的注入浓度为漂移区浓度的1.2~1000倍。
5.根据权利要求1所述的带有多数载流子二极管的碳化硅MOS器件,其特征在于,所述第一导电类型为N型电子导电,其对应掺杂杂质为氮元素;所述第二导电类型为P型空穴导电,其对应掺杂杂质为铝元素。
6.根据权利要求1所述的带有多数载流子二极管的碳化硅MOS器件,其特征在于,所述第一导电类型为P型空穴导电,其对应掺杂杂质为铝元素;所述第二导电类型为N型电子导电,其对应掺杂杂质为氮元素。
7.一种用于多数载流子二极管的碳化硅MOS器件的制作方法,包括:
在具有第一导电类型的碳化硅上表面生长相同导电类型的碳化硅漂移区,通过注入杂质形成电流加强区并形成第一表面;
在所述电流加强区的第一表面通过注入杂质形成基区、源区、体区、多个结势垒注入区;
在所述第一表面部分区域与所述电流加强注入区、基区、源区上方的位置形成栅电极及其外围栅介质;
在所述第一表面结构和栅电极及其外围栅介质上方形成第二电极。
8.根据权利要求7所述的方法,其特征在于,所述第二电极的制作方法分为两步制作,第一步在源区和体区表面制作欧姆接触,第二步制作覆盖欧姆接触、基区、结势垒注入区和电流加强注入区表面的第二电极材料,同时与电流加强注入区形成第一导电类型载流子势垒。
9.根据权利要求7所述的方法,其特征在于,所述第二电极的制作方法为:使用第二电极材料与所述源区、体区和结势垒注入区形成欧姆接触,同时与所述电流加强注入区形成第一导电类型载流子势垒。
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CN117497601B (zh) * 2023-12-28 2024-05-07 深圳天狼芯半导体有限公司 平面型碳化硅晶体管的结构、制造方法及电子设备

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