WO2014177045A1 - 一种半浮栅器件及其制造方法 - Google Patents

一种半浮栅器件及其制造方法 Download PDF

Info

Publication number
WO2014177045A1
WO2014177045A1 PCT/CN2014/076438 CN2014076438W WO2014177045A1 WO 2014177045 A1 WO2014177045 A1 WO 2014177045A1 CN 2014076438 W CN2014076438 W CN 2014076438W WO 2014177045 A1 WO2014177045 A1 WO 2014177045A1
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
region
layer
doping type
insulating film
Prior art date
Application number
PCT/CN2014/076438
Other languages
English (en)
French (fr)
Inventor
王鹏飞
张卫
孙清清
Original Assignee
复旦大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 复旦大学 filed Critical 复旦大学
Priority to US14/651,997 priority Critical patent/US9508811B2/en
Priority to EP14791834.6A priority patent/EP2993695A4/en
Publication of WO2014177045A1 publication Critical patent/WO2014177045A1/zh
Priority to US15/342,328 priority patent/US9748406B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

Definitions

  • the present invention relates to the field of semiconductor memory technology, and in particular to a semi-floating gate device and a method of fabricating the same, and more particularly to a semi-floating gate device with a vertical channel region and a method of fabricating the same. Background technique
  • SRAM static random access memory
  • DRAM standard dynamic random access memory
  • planar channel semiconductor memory of the prior art, comprising: a source region 501 and a drain region 502 formed in a semiconductor substrate 500 having a doping type opposite to a semiconductor substrate, and the semiconductor substrate 500 may be It is monocrystalline silicon, polycrystalline silicon or silicon on insulator.
  • a planar channel region 601 is formed in the semiconductor substrate 500 between the source region 501 and the drain region 502.
  • the planar channel region 601 is a reverse formed in the semiconductor substrate 500 during operation of the semiconductor memory. Type layer.
  • a doping region 509 and a doping region 510 having a high doping concentration are also formed in the source region 501 and the drain region 502, respectively, and the doping region 509 and the doping region 510 have the same doping as the source region 501 and the drain region 502. Types of.
  • a first insulating film 503 is formed over the source region 501, the channel region 601 and the drain region 502, and a floating gate opening region 504 is formed in the first insulating film 503 over the drain region 502.
  • a floating gate 505 as a charge storage node is formed over the first insulating film 503, covering the entire planar channel region 601 and the floating gate opening region 504, and the floating gate 505 has a doping type opposite to the drain region 502, and Doping impurities in the floating gate 505 will diffuse into the drain region 502 through the floating gate opening region 504 to form a diffusion region 602, thereby forming a pn junction diode between the floating gate 505 and the drain region 502 through the floating gate opening region 504.
  • the floating gate 205 and the p-n junction diode structure are formed with a second insulating film 506.
  • a control gate 507 of the device is formed over the second insulating film 506, covering and surrounding the floating gate 505.
  • Gate side walls 508 are also formed on both sides of the control gate 507.
  • the semiconductor memory further includes a contact body 511 formed of a conductive material for connecting the source region 501, the control gate 507, the drain region 502, the semiconductor substrate 500 to the external electrode, the contact body 512 of the control gate, and the drain.
  • the contact body 513 of the region and the contact body 514 of the semiconductor substrate are formed with a second insulating film 506.
  • planar channel semiconductor memory requires a long channel length, which makes the semiconductor memory unit area larger, thereby reducing the chip density, which is disadvantageous for the chip to be miniaturized. Disclosure of invention
  • An object of the present invention is to provide a semi-floating gate device with a vertical channel region, thereby reducing the cell area of the semiconductor memory and increasing the chip density.
  • the invention provides a semi-floating gate device with a vertical channel region, wherein the floating gate and the drain region are connected by a p-n junction diode, so that the floating gate is in a "semi-floating" state.
  • the semi-floating gate device specifically includes: a semiconductor substrate having a first doping type;
  • a bottom of the vertical channel region is connected to a source region having a second doping type, and a top portion of the vertical channel region is connected to a drain region having a second doping type;
  • the floating gate Covering the first insulating film and the floating gate opening region to form a floating gate having a first doping type; the floating gate serving as a charge storage node on the vertical channel region and the floating gate opening region, on the one hand Forming a pn junction diode between the floating gate and the drain region through the floating gate opening region; on the other hand, because the floating gate covers the first insulating film on the vertical channel region, it can be controlled by electric field regulation Turning on and off current in the channel region;
  • a second insulating film formed by covering the source region, the floating gate and the p-n junction diode;
  • a control gate formed by the floating gate and the gate-controlled p-n junction diode is covered.
  • the first doping type is n-type
  • the second doping type is p-type
  • the first doping type is p-type
  • the second The doping type is n type.
  • the first insulating film and the second insulating film are formed of silicon dioxide, silicon nitride, silicon oxynitride or a high dielectric constant insulating material, and the floating gate is made of doped polysilicon.
  • the control gate is formed of metal, alloy or doped polysilicon.
  • the pn junction diode, the second insulating film and the control gate constitute a gated diode having the control gate as a gate, and an anode of the gated diode is connected to the floating gate.
  • the cathode of the gated diode is connected to the drain region; or the cathode of the gated diode is connected to the floating gate, and the anode of the gated diode is connected to the drain region.
  • the invention provides a preparation method of the semi-floating gate device, and the specific steps are as follows:
  • the depth of the etching needs to be deeper than the depth of the lightly doped region having the second doping type, and the lightly doped region having the second doping type is etched away, and the remaining a lightly doped region having a second doping type forms a drain region of the device;
  • a first conductive film having a first doping type is deposited on the exposed surface of the formed structure, and the formed first conductive film is etched back to form a floating gate of the device, wherein the floating gate At least covering the formed vertical channel region and the floating gate opening region;
  • a second doping type of ion implantation is performed to dope the control gate and the semiconductor substrate not covered by the control gate to form a source region of the device and a doping structure of the drain region and the control gate.
  • the first doping type is n-type, and the second doping type is p-type; or, the first doping type is P type, the second doping type is n type.
  • the first insulating film and the second insulating film are silicon dioxide, silicon nitride, silicon oxynitride or an insulating material having a high dielectric constant
  • the first conductive film is doped polysilicon
  • the second conductive film is metal, alloy or doped polysilicon.
  • the floating gate of the semi-floating gate device of the present invention stores information and charges or discharges the floating gate through a gate-controlled pn junction diode, and has a small cell area, high chip density, low operating voltage when data is stored, and data retention. Strong ability and so on. BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a prior art planar channel semiconductor memory device.
  • FIG. 2 is a cross-sectional view and an equivalent circuit diagram of an embodiment of a semi-floating gate device according to the present invention.
  • 3 to 10 are process flow diagrams of an embodiment of a method of fabricating a semi-floating gate device according to the present invention. The best way to implement the invention
  • Figure 2a is a three embodiment of a semi-floating gate device proposed by the present invention, which is a cross-sectional view along the length of the channel of the device.
  • the semi-floating gate device proposed by the present invention comprises a semiconductor substrate 200 having a first doping type and a vertical channel region 401 formed in the semiconductor substrate 200.
  • the vertical channel region 401 is The semi-floating gate device forms an inversion layer within the semiconductor substrate 200 during operation.
  • a source region 201 having a second doping type is formed at the bottom of the vertical channel region 401 in the semiconductor substrate 200, and a drain region 202 having a second doping type is formed at the top of the vertical channel region 401.
  • the semiconductor substrate 200 may be monocrystalline silicon, polycrystalline silicon or silicon on insulator.
  • the first doping type is n-type
  • the second doping type is p-type
  • the first doping type is p-type
  • the second doping type It is n type.
  • the cover source region 201, the drain region 202, and the vertical channel region 401 are formed with a first insulating film 203, and a floating gate opening region is formed in the first insulating film 203 covering the drain region 202 at the top of the vertical channel region 401.
  • the first insulating film 203 may be silicon dioxide, silicon nitride, silicon oxynitride or a high dielectric constant insulating material such as cerium oxide, and its physical thickness preferably ranges from 1 to 20 nanometers.
  • a floating gate 205 having a first doping type as a charge storage node is formed over the first insulating film 203 and covering the vertical channel region 401 and the floating gate opening region 204.
  • the floating gate 205 has a doping type opposite to the drain region 202, and dopant impurities in the floating gate 205 are diffused into the drain region 202 through the floating gate opening region 204 to form a diffusion region 402 having a first doping type, thereby A pn junction diode is formed between the floating gate 205 and the drain region 202 through the floating gate opening region 204.
  • the floating gate 205 and the pn junction diode structure are formed with a second insulating film 206, and the second insulating film 206 may be silicon dioxide, silicon nitride, silicon oxynitride or a high dielectric constant such as yttrium oxide.
  • the insulating material preferably has a physical thickness ranging from 1 to 20 nm.
  • a control gate 207 is formed over the second insulating film 206 and covering the floating gate 205 and the p-n junction diode.
  • the control gate 207 may be metal, alloy or doped polysilicon.
  • Gate side walls 208 of the device are also formed on both sides of the control gate 207.
  • the gate spacers 208 may be silicon dioxide or silicon nitride.
  • the gate spacers are well known in the art for controlling the gate 207. Isolate from other conductive layers in the device.
  • Doped regions 210 of the same doping type as the drain regions 202 are also formed in the drain regions 202, respectively.
  • the doping concentration of the doping regions 210 is significantly higher than the doping concentration of the drain regions 202 for reducing the ohmic contact of the device.
  • the semi-floating gate device of the present invention further includes a contact body 211 formed of a conductive material for connecting the source region 201, the control gate 207, the drain region 202, and the semiconductor substrate 200 to the external electrode, and a control gate.
  • the contact body 212, the contact body 213 of the drain region, and the contact body 214 of the semiconductor substrate are also formed in the drain regions 202, respectively.
  • the doping concentration of the doping regions 210 is significantly higher than the doping concentration of the drain regions 202 for reducing the ohmic contact of the device.
  • the semi-floating gate device of the present invention further includes a contact body 211 formed of a conductive material for connecting the source region 201, the control gate 207
  • Figure 2b shows an equivalent circuit diagram of a semi-floating gate device of the present invention.
  • the semi-floating gate device of the present invention includes a MOSFET 36 having a source 32, a drain 30, a floating gate 33 and a control gate 31, and a gate diode having a gate 31 of the MOSFET 36 as a gate. 35.
  • the floating gate 33 of the MOSFET 36 may be connected to the anode of the gated diode 35 or to the cathode of the gated diode 35. In the embodiment shown in Fig. 2b, the floating gate 33 and the anode of the gated diode 35 are connected. connection.
  • the gate diode 35 can charge or discharge the floating gate 33 to change the amount of charge stored in the floating gate 33, which determines the amount of charge.
  • the logic state of the semi-floating gate device that is, the on and off of the current in the vertical channel region.
  • the semi-floating gate device disclosed in the present invention can be fabricated by a number of methods, and the process flow of one embodiment of the present invention for manufacturing a semi-floating gate device having an n-type channel as shown in FIG. 2a is described below. .
  • an active region (not shown) is formed by a shallow trench isolation (STI) process in a semiconductor substrate 200 having a first doping type, which is an STI process.
  • a first doping type which is an STI process.
  • a lightly doped region 300 having a second doping type is then formed in the semiconductor substrate 200 by an ion implantation process.
  • the semiconductor substrate 200 may be monocrystalline silicon, polycrystalline silicon or silicon on insulator.
  • the first doping type is p-type
  • the second doping type is n-type.
  • a hard mask layer 301 is deposited on the surface of the semiconductor substrate 200, and the hard mask layer 301 is, for example, silicon nitride.
  • a layer of photoresist 302 is then deposited over the hard mask layer 301 and masked, exposed, developed to define the location of the vertical channel region of the device, and then the exposed hard mask layer 301 is etched away and hardened.
  • the mask layer 301 etches the exposed semiconductor substrate 200 by a dry etching process for the mask to form a vertical channel region region within the semiconductor substrate 200.
  • the etch depth of the semiconductor substrate 200 needs to be deeper than the depth of the lightly doped region 300 having the second doping type, and the lightly doped region 300 having the second doping type is also etched away.
  • the remaining lightly doped region 300 having the second doping type forms the drain region 202 of the device, as shown in FIG.
  • the photoresist 303 is stripped and the remaining hard mask layer 301 is etched away, and then a first insulating film 203 is grown on the exposed surface of the semiconductor substrate 200.
  • the first insulating film 203 may be silicon oxide.
  • the silicon nitride, silicon oxynitride or a high dielectric constant insulating material such as cerium oxide has a physical thickness of preferably 1 to 20 nm.
  • a layer of photoresist on the first insulating film 203 and defining the position of the floating gate opening region by a photolithography process, and then etching the exposed first insulating film with the photoresist as a mask 203, thereby forming a floating gate opening region 204 in the first insulating film 203 covering the drain region 202 at the top of the vertical channel region, and stripping the photoresist as shown in FIG.
  • a first conductive film having a first doping type is deposited on the exposed surface of the formed structure, the conductive film being polycrystalline silicon having a P-type doping type. The formed first conductive film is then etched back to form the floating gate 205 of the device.
  • the floating gate 205 covers at least the vertical channel region and the floating gate opening region 204.
  • the doping impurities in the floating gate 205 are diffused into the drain region 202 through the floating gate opening region 204 to form a p-type diffusion region 402, and a pn junction formed between the floating gate 205 and the drain region 202 through the floating gate opening region 204. diode. After stripping the photoresist, it is as shown in FIG. 6.
  • the exposed first insulating film 203 is etched away, and a second insulating film 206 is grown on the exposed surface of the formed structure.
  • the second insulating film 206 may be silicon oxide, silicon nitride, or oxynitride. Silicon or an insulating material having a high dielectric constant such as yttrium oxide has a physical thickness of preferably 1 to 20 nm.
  • a second conductive film 207 is then deposited over the second insulating film 206.
  • the second conductive film 207 may be a metal, an alloy or doped polysilicon.
  • a third insulating film is deposited on the exposed surface of the formed structure, and then a photoresist is deposited on the formed third insulating film and patterned by photolithography, and then etched.
  • the exposed third insulating film is removed, and the exposed second insulating film 206 is further etched away, and the remaining third insulating film forms a gate spacer 208 on both sides of the control gate 207.
  • the process is well known in the art, and the photoresist is stripped as shown in FIG.
  • the gate spacers 208 can be silicon oxide or silicon nitride.
  • the control gate 207 and the semiconductor substrate 200 not covered by the control gate 207 are doped to form doping of the source region 201 and the control gate 207.
  • the structure, and a high concentration doped region 210 is formed in the drain region 202, as shown in FIG.
  • the contact body 21 1 of the source region for connecting the source region 201, the control gate 207, the drain region 202, the semiconductor substrate 200 and the external electrode, the contact body 212 of the control gate, and the contact of the drain region are formed of a conductive material.
  • the body 21 3 and the contact body 214 of the semiconductor substrate are as shown in FIG.
  • the floating gate of the semi-floating gate device of the present invention stores information and charges or discharges the floating gate through a gate-controlled pn junction diode, and has a small cell area, high chip density, low operating voltage when data is stored, and data retention. Strong ability and so on.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

一种半浮栅器件，包括至少一个半导体衬底（200）、一个源区（201）、一个漏区（202）、一个浮栅（205）、一个控制栅（207）、一个垂直沟道区（401）以及一个用于连接所述浮栅（205）与所述漏区（202）的栅控p-n结二极管。该半浮栅器件用浮栅存储信息，并通过所述栅控p-n结二极管对浮栅进行充电或放电，具有单元面积小、芯片密度高、对数据进行存储时操作电压低、数据保持能力强等优点。

Description

一种半浮栅器件及其制造方法 技术领域
本发明属于半导体存储器技术领域， 具体涉及一种半浮栅器件及其制造 方法， 特别涉及一种带垂直沟道区的半浮栅器件及其制造方法。 背景技术
半导体存储器被广泛应用于各种电子产品之中。 不同应用领域对半导体 存储器的构造、 性能和密度有着不同的要求。 比如， 静态随机存储器（SRAM ) 拥有很高的随机存取速度和较低的集成密度， 而标准的动态随机存储器 ( DRAM ) 则具有很高的密度和中等的随机存取速度。
图 1为现有技术的的一种平面沟道的半导体存储器， 包括： 在半导体衬 底 500内形成的具有与半导体衬底相反掺杂类型的源区 501和漏区 502， 半 导体衬底 500可以为单晶硅、多晶硅或者为绝缘体上的硅。在半导体衬底 500 内、 介于源区 501和漏区 502之间形成有器件的平面沟道区 601， 平面沟道 区 601是该半导体存储器在进行工作时在半导体衬底 500内形成的反型层。 在源区 501 和漏区 502 内还分别形成有高掺杂浓度的掺杂区 509和掺杂区 510， 掺杂区 509和掺杂区 510与源区 501和漏区 502具有相同的掺杂类型。
在源区 501、 沟道区 601和漏区 502之上形成有第一层绝缘薄膜 503， 且在漏区 502之上的第一层绝缘薄膜 503中形成有一个浮栅开口区域 504。 在第一层绝缘薄膜 503之上、 覆盖整个平面沟道区 601和浮栅开口区域 504 形成有一个作为电荷存储节点的浮栅 505， 浮栅 505具有与漏区 502相反的 掺杂类型，且浮栅 505中的掺杂杂质会通过浮栅开口区域 504扩散至漏区 502 中形成扩散区 602， 从而通过浮栅开口区域 504在浮栅 505与漏区 502之间 形成一个 p-n结二极管。
覆盖浮栅 205和所述的 p-n结二极管结构形成有第二层绝缘薄膜 506。 在第二层绝缘薄膜 506之上、覆盖并包围浮栅 505形成有器件的控制栅 507。 在控制栅 507的两侧还形成有栅极侧墙 508。 该半导体存储器还包括由导电 材料形成的用于将源区 501、 控制栅 507、 漏区 502、 半导体衬底 500与外部 电极相连接的源区的接触体 511、 控制栅的接触体 512、 漏区的接触体 513 和半导体衬底的接触体 514。
为保证半导体存储器的性能， 平面沟道的半导体存储器需要较长的沟道 长度， 这使得半导体存储器的单元面积较大， 从而降低了芯片密度， 不利于 芯片向微型化的方向发展。 发明的公开
本发明的目的在于提出一种带垂直沟道区的半浮栅器件， 从而可以降低 半导体存储器的单元面积， 提高芯片密度。
本发明提供的一种带垂直沟道区的半浮栅器件， 由于其浮栅和漏区之间 通过 p-n结二极管相连， 使浮栅呈 "半浮"状态。 所述半浮栅器件具体包括： 一个具有第一种掺杂类型的半导体衬底；
在所述半导体衬底内形成的垂直沟道区；
所述垂直沟道区的底部与具有第二种掺杂类型的源区连接， 所述垂直沟 道区的顶部与具有第二种种掺杂类型的漏区连接；
覆盖所述源区、 漏区与垂直沟道区形成的第一层绝缘薄膜；
在半导体衬底水平表面上且覆盖所述漏区的第一层绝缘薄膜中， 形成的 一个浮栅开口区域；
覆盖所述第一层绝缘薄膜和浮栅开口区域，形成一个具有第一种掺杂类 型的浮栅； 该浮栅作为电荷存储节点， 位于垂直沟道区和浮栅开口区之上， 一方面通过所述浮栅开口区，在所述浮栅与漏区之间形成一个 p-n结二极管； 另一方面因为浮栅覆盖在垂直沟道区的第一层绝缘薄膜上， 可以通过电场调 控来控制沟道区内电流的通与断；
覆盖所述源区、 浮栅与 p-n结二极管形成的第二层绝缘薄膜；
在所述第二层绝缘薄膜之上， 且覆盖所述浮栅与栅控 p-n结二极管形成 的控制栅。
本发明中， 所述的第一种掺杂类型为 n型， 所述的第二种掺杂类型为 p 型； 或者， 所述的第一种掺杂类型为 p型， 所述的第二种掺杂类型为 n型。
本发明中， 所述的第一层绝缘薄膜、 第二层绝缘薄膜由二氧化硅、 氮化 硅、 氮氧化硅或者高介电常数的绝缘材料形成， 所述的浮栅由掺杂的多晶硅 形成， 所述的控制栅由金属、 合金或者掺杂的多晶硅形成。
本发明中， 所述的 p-n结二极管、 第二层绝缘薄膜和控制栅构成了一个 以所述控制栅作为栅极的栅控二极管， 所述栅控二极管的阳极与所述浮栅相 连接， 所述栅控二极管的阴极与所述漏区相连接； 或者， 所述栅控二极管的 阴极与所述浮栅相连接， 所述栅控二极管的阳极与所述漏区相连接。
本发明提出了所述半浮栅器件的制备方法， 具体步骤如下：
在具有第一掺杂类型的半导体衬底内形成具有第二种掺杂类型的轻掺 杂区；
在所述半导体衬底表面淀积一硬掩膜层并通过光刻工艺和刻蚀工艺定 义出器件的垂直沟道区的位置；
以所述硬掩膜层为掩膜刻蚀暴露出的半导体衬底， 形成器件的垂直沟道 区区域，刻蚀的深度需深于所形成的具有第二种掺杂类型的轻掺杂区的深度， 此时具有第二种掺杂类型的轻掺杂区会被刻蚀掉一部分， 剩余的具有第二种 掺杂类型的轻掺杂区形成器件的漏区；
刻蚀掉剩余的硬掩膜层；
在半导体衬底的暴露表面上生长第一层绝缘薄膜并刻蚀所形成的第一 层绝缘薄膜形成浮栅开口区域， 所形成的浮栅开口区域在垂直沟道区顶部的 将漏区暴露出来；
接着， 在所形成结构的暴露表面上淀积具有第一种掺杂类型的第一层导 电薄膜， 并对所形成的第一层导电薄膜进行回刻以形成器件的浮栅， 其中， 浮栅至少覆盖所形成的垂直沟道区和浮栅开口区域；
接着， 在已形成结构的暴露表面上生长第二层绝缘薄膜；
在所述第二层绝缘薄膜之上淀积形成第二层导电薄膜， 然后通过光刻工 艺和刻蚀工艺刻蚀所形成的第二层导电薄膜以形成器件的控制栅；
进行第二种掺杂类型的离子注入， 对控制栅和未被控制栅覆盖的半导体 衬底进行掺杂以形成器件的源区以及漏区和控制栅的掺杂结构。
如上所述的半浮栅器件的制备方法， 所述的第一种掺杂类型为 n型， 所 述的第二种掺杂类型为 p型； 或者， 所述的第一种掺杂类型为 p型， 所述的 第二种掺杂类型为 n型。
如上所述的半浮栅器件的制备方法， 所述的第一层绝缘薄膜和第二层绝 缘薄膜为二氧化硅、 氮化硅、 氮氧化硅或者为高介电常数的绝缘材料， 所述 的第一层导电薄膜为掺杂的多晶硅， 所述的第二层导电薄膜为金属、 合金或 者为掺杂的多晶硅。
本发明所提出的半浮栅器件用浮栅存储信息， 并通过栅控 p-n结二极管 对浮栅进行充电或放电， 具有单元面积小、 芯片密度高、 对数据进行存储时 操作电压低、 数据保持能力强等优点。 附图的简要说明
图 1为现有技术的的一种平面沟道的半导体存储器的剖面图。
图 2 为本发明所提出的半浮栅器件的一个实施例的剖面图及等效电路 图。
图 3至图 10为本发明提出的半浮栅器件的制造方法的一个实施例的工 艺流程图。 实现本发明的最佳方式
下面结合附图与具体实施方式对本发明作进一步详细的说明。 在图中， 为了方便说明， 放大了层和区域的厚度， 所示大小并不代表实际尺寸。 参考 图是本发明的理想化实施例的示意图， 所示的实施例不应该被认为仅限于图 中所示区域的特定形状， 而是包括所得到的形状， 比如制造引起的偏差。 例 如刻蚀得到的曲线通常具有弯曲或圓润的特点， 但在实施例中， 均以矩形表 示， 图中的表示是示意性的， 但这不应该被认为是限制本发明的范围。
图 2a 是本发明所提出的半浮栅器件的三个实施例， 它是沿该器件沟道 长度方向的剖面图。如图 2a所示，本发明所提出的半浮栅器件包括一个具有 第一种掺杂类型的半导体衬底 200以及在半导体衬底 200内形成的垂直沟道 区 401， 垂直沟道区 401是该半浮栅器件在进行工作时在半导体衬底 200内 形成的反型层。 在半导体衬底 200内位于垂直沟道区 401的底部形成有具有 第二种掺杂类型的源区 201以及位于垂直沟道区 401的顶部形成有具有第二 种掺杂类型的漏区 202。 半导体衬底 200可以为单晶硅、 多晶硅或者为绝缘 体上的硅。 所述的第一种掺杂类型为 n型， 所述的第二种掺杂类型为 p型， 或者， 所述的第一种掺杂类型为 p型， 所述的第二种掺杂类型为 n型。
覆盖源区 201、 漏区 202和垂直沟道区 401形成有第一层绝缘薄膜 203， 在垂直沟道区 401的顶部覆盖漏区 202的第一层绝缘薄膜 203中形成有一个 浮栅开口区域 204。 第一层绝缘薄膜 203可以为二氧化硅、 氮化硅、 氮氧化 硅或者为氧化铪等高介电常数的绝缘材料， 其物理厚度范围优选为 1-20 纳 米。
在第一层绝缘薄膜 203之上且覆盖垂直沟道区 401和浮栅开口区域 204 形成有一个作为电荷存储节点的具有第一种掺杂类型的浮栅 205。 浮栅 205 具有与漏区 202相反的掺杂类型， 且浮栅 205中的掺杂杂质会通过浮栅开口 区域 204扩散至漏区 202中形成具有第一种掺杂类型的扩散区 402， 从而通 过浮栅开口区域 204在浮栅 205与漏区 202之间形成一个 p-n结二极管。
覆盖浮栅 205和所述的 p-n结二极管结构形成有第二层绝缘薄膜 206， 第二层绝缘薄膜 206可以为二氧化硅、 氮化硅、 氮氧化硅或者为氧化铪等高 介电常数的绝缘材料， 其物理厚度范围优选为 1-20纳米。
在第二层绝缘薄膜 206之上且覆盖浮栅 205和所述的 p-n结二极管形成 有器件的控制栅 207， 控制栅 207可以为金属、 合金或者为掺杂的多晶硅。
在控制栅 207的两侧还形成有器件的栅极侧墙 208， 栅极侧墙 208可以 为二氧化硅或者氮化硅， 栅极侧墙是业界所熟知的结构， 用于将控制栅 207 与器件中的其它导电层隔离。
在漏区 202内还分别形成有与漏区 202相同掺杂类型的掺杂区 210， 掺 杂区 210的掺杂浓度明显高于漏区 202的掺杂浓度， 用于降低器件的欧姆接 触。 本发明的半浮栅器件还包括由导电材料形成的用于将所述源区 201、 控 制栅 207、漏区 202、半导体衬底 200与外部电极相连接的源区的接触体 211、 控制栅的接触体 212、 漏区的接触体 213和半导体衬底的接触体 214。
为进一步详细地描述本发明所公开的半浮栅器件的结构和功能， 图 2b 展示了本发明的半浮栅器件的等效电路图。如图 2b所示，本发明的半浮栅器 件包含一个具有源极 32、 漏极 30、 浮栅 33和控制栅 31的 M0SFET 36以及一 个以 M0SFET 36的控制栅 31为栅极的栅控二极管 35。 M0SFET 36的浮栅 33 可以与栅控二极管 35的阳极相连接，也可以与栅控二极管 35的阴极相连接， 在图 2b所示的实施例中，浮栅 33与栅控二极管 35的阳极相连接。通过对控 制栅 31、 漏极 30和源极 31施加适当的电压， 栅控二极管 35可以对浮栅 33 进行充电或放电以此来改变储存在浮栅 33内的电荷数量，此电荷数量决定了 该半浮栅器件的逻辑状态， 也就是垂直沟道区内电流的通与断。
本发明所公开的半浮栅器件可以通过很多方法制造， 以下所叙述的是本 发明所提出的制造如图 2a所示结构的具有 n型沟道的半浮栅器件的一个实施 例的工艺流程。
首先， 如图 3所示， 在提供的具有第一种掺杂类型的半导体衬底 200内 通过浅沟槽隔离 （STI ) 工序形成有源区 （图中未示出） ，这种 STI工艺是业 界所熟知的。 然后通过离子注入工艺在半导体衬底 200内形成具有第二种掺 杂类型的轻掺杂区 300。 半导体衬底 200可以为单晶硅、 多晶硅或者为绝缘 体上的硅。 所述的第一种掺杂类型为 p型， 所述的第二种掺杂类型为 n型。
接下来，在半导体衬底 200的表面淀积一层硬掩膜层 301，硬掩膜层 301 比如为氮化硅。接着在硬掩膜层 301之上淀积一层光刻胶 302并掩膜、曝光、 显影定义出器件的垂直沟道区的位置， 然后刻蚀掉暴露的硬掩膜层 301， 并 以硬掩膜层 301为掩膜通过干法刻蚀的方法刻蚀暴露出的半导体衬底 200， 从而形成在半导体衬底 200内的垂直沟道区区域。 对半导体衬底 200的刻蚀 深度需深于具有第二种掺杂类型的轻掺杂区 300的深度， 此时具有第二种掺 杂类型的轻掺杂区 300也会被刻蚀掉一部分， 剩余的具有第二种掺杂类型的 轻掺杂区 300形成器件的漏区 202， 如图 4所示。
接下来， 剥除光刻胶 303并续刻蚀掉剩余的硬掩膜层 301， 接着在半导 体衬底 200的暴露表面上生长第一层绝缘薄膜 203， 第一层绝缘薄膜 203可 以为氧化硅、 氮化硅、 氮氧化硅或者为氧化铪等高介电常数的绝缘材料， 其 物理厚度优选为 1-20纳米。接着在第一层绝缘薄膜 203之上淀积一层光刻胶 并通过光刻工艺定义出浮栅开口区域的位置， 然后以光刻胶为掩膜刻蚀掉暴 露出的第一层绝缘薄膜 203， 从而在垂直沟道区的顶部覆盖漏区 202的第一 层绝缘薄膜 203中形成一个浮栅开口区域 204， 剥除光刻胶如图 5所示。 接下来， 在已形成结构的暴露表面上淀积一层具有第一种掺杂类型的第 一层导电薄膜， 该导电薄膜为具有 P型掺杂类型的多晶硅。 接着对所形成的 第一层导电薄膜进行回刻以形成器件的浮栅 205。 浮栅 205至少覆盖垂直沟 道区和浮栅开口区域 204。 浮栅 205 中的掺杂杂质会通过浮栅开口区域 204 扩散至漏区 202中形成 p型扩散区 402，且通过浮栅开口区域 204在浮栅 205 与漏区 202之间形成的一个 p-n结二极管。 剥除光刻胶后如图 6所示。
接下来， 刻蚀掉暴露出的第一层绝缘薄膜 203， 并在已形成结构的暴露 表面上生长第二层绝缘薄膜 206， 第二层绝缘薄膜 206可以为氧化硅、 氮化 硅、 氮氧化硅或者为氧化铪等高介电常数的绝缘材料， 其物理厚度优选为 1-20纳米。 接着在第二层绝缘薄膜 206之上淀积形成第二层导电薄膜 207， 第二层导电薄膜 207可以为金属、 合金或者为掺杂的多晶硅。 然后在第二层 导电薄膜 207之上淀积一层光刻胶并通过光刻工艺定义出器件的控制栅的位 置， 接着以光刻胶为掩膜刻蚀掉暴露出的第二层导电薄膜， 刻蚀后剩余的第 二层导电薄膜形成器件的控制栅 207， 控制栅 207应覆盖浮栅 205与所形成 的 p-n结二极管， 剥除光刻胶后如图 7所示。
接下来， 在已形成结构的暴露表面上淀积形成第三层绝缘薄膜， 接着在 所形成的第三层绝缘薄膜之上淀积一层光刻胶并通过光刻工艺形成图形， 然 后刻蚀掉暴露出的第三层绝缘薄膜， 并继续刻蚀掉暴露出的第二层绝缘薄膜 206， 刻蚀后剩余的第三层绝缘薄膜在控制栅 207的两侧形成栅极侧墙 208， 该工艺是业界所熟知的， 剥除光刻胶后如图 8所示。 栅极侧墙 208可以为氧 化硅或者氮化硅。
接下来， 进行第二种掺杂类型 （n 型） 的杂质离子注入， 对控制栅 207 和未被控制栅 207覆盖的半导体衬底 200进行掺杂， 形成源区 201和控制栅 207的掺杂结构， 并在漏区 202中形成高浓度的掺杂区 21 0， 如图 9所示。
最后， 以导电材料形成用于将源区 201、 控制栅 207、 漏区 202、 半导体 衬底 200与外部电极相连接的源区的接触体 21 1、控制栅的接触体 212、漏区 的接触体 21 3以及半导体衬底的接触体 214， 如图 10所示。
如上所述， 在不偏离本发明精神和范围的情况下， 还可以构成许多有很 大差别的实施例。 应当理解， 除了如所附的权利要求所限定的， 本发明不限 于在说明书中所述的具体实例。 工业应用性
本发明所提出的半浮栅器件用浮栅存储信息， 并通过栅控 p-n结二极管 对浮栅进行充电或放电， 具有单元面积小、 芯片密度高、 对数据进行存储时 操作电压低、 数据保持能力强等优点。

Claims

权利要求
1. 一种半浮栅器件， 其特征在于， 包括：
一个具有第一种掺杂类型的半导体衬底；
在所述半导体衬底内形成的垂直沟道区；
所述垂直沟道区的底部与具有第二种掺杂类型的源区连接， 所述垂 直沟道区的顶部与具有第二种种掺杂类型的漏区连接；
覆盖所述源区、 漏区与垂直沟道区形成的第一层绝缘薄膜； 在半导体衬底水平表面上且覆盖所述漏区的第一层绝缘薄膜中， 形 成的一个浮栅开口区域；
覆盖所述第一层绝缘薄膜和浮栅开口区域，形成一个具有第一种掺 杂类型的浮栅， 所述浮栅作为电荷存储节点； 通过所述浮栅开口区域， 在所述浮栅与漏区之间形成的一个 p-n结二极管； 并且， 所述浮栅覆盖 在所述垂直沟道区的所述第一层绝缘薄膜上， 其通过电场调控来控制所 述垂直沟道区内电流的通与断；
覆盖所述源区、 浮栅与 p-n结二极管形成的第二层绝缘薄膜； 在所述第二层绝缘薄膜之上， 且覆盖所述浮栅与栅控 p-n结二极管 形成的控制栅。
2. 根据权利要求 1所述的半浮栅器件， 其特征在于， 所述的第一种掺杂类 型为 n型， 所述的第二种掺杂类型为 p型； 或者， 所述的第一种掺杂类 型为 P型， 所述的第二种掺杂类型为 n型。
3. 根据权利要求 1所述的半浮栅器件， 其特征在于， 所述的第一层绝缘薄 膜、 第二层绝缘薄膜由二氧化硅、 氮化硅、 氮氧化硅或者高介电常数的 绝缘材料形成，所述的浮栅由掺杂的多晶硅形成，所述的控制栅由金属、 合金或者掺杂的多晶硅形成。
4. 根据权利要求 1所述的半浮栅器件，其特征在于，所述的 p-n结二极管、 第二层绝缘薄膜和控制栅构成了一个以所述控制栅作为栅极的栅控二极 管， 所述栅控二极管的阳极与所述浮栅相连接， 所述栅控二极管的阴极 与所述漏区相连接； 或者， 所述栅控二极管的阴极与所述浮栅相连接， 所述栅控二极管的阳极与所述漏区相连接。
5. 一种如权利要求 1所述的半浮栅器件的制备方法， 其特征在于， 具体步 骤如下：
在具有第一种掺杂类型的半导体衬底内形成具有第二种掺杂类型 的轻掺杂区；
在所述半导体衬底表面淀积一硬掩膜层并通过光刻工艺和刻蚀工 艺定义出器件的垂直沟道区的位置；
以所述硬掩膜层为掩膜刻蚀暴露出的半导体衬底， 形成器件的垂直 沟道区区域， 刻蚀的深度需深于所形成的具有第二种掺杂类型的轻掺杂 区的深度， 此时具有第二种掺杂类型的轻掺杂区会被刻蚀掉一部分， 剩 余的具有第二种掺杂类型的轻掺杂区形成器件的漏区；
刻蚀掉剩余的硬掩膜层；
在半导体衬底的暴露表面上生长第一层绝缘薄膜并刻蚀所形成的 第一层绝缘薄膜形成浮栅开口区域， 所形成的浮栅开口区域在垂直沟道 区的顶部将漏区暴露出来；
接着， 在所形成结构的暴露表面上淀积具有第一种掺杂类型的第一 层导电薄膜， 并对所形成的第一层导电薄膜进行回刻以形成器件的浮 栅， 其中， 浮栅至少覆盖所形成的垂直沟道区和浮栅开口区域；
接着， 在已形成结构的暴露表面上生长第二层绝缘薄膜； 在所述第二层绝缘薄膜之上淀积形成第二层导电薄膜， 然后通过光 刻工艺和刻蚀工艺刻蚀所形成的第二层导电薄膜以形成器件的控制栅； 进行第二种掺杂类型的离子注入， 对控制栅和未被控制栅覆盖的半 导体衬底进行掺杂以形成器件的源区以及漏区和控制栅的掺杂结构。
6. 根据权利要求 5所述的半浮栅器件的制备方法， 其特征在于， 还包括以 导电材料形成用于将所述源区、 控制栅、 漏区、 半导体衬底与外部电极 相连接的源区的接触体、 控制栅的接触体、 漏区的接触体和半导体衬底 的接触体。
7. 根据权利要求 5所述的半浮栅器件的制备方法， 其特征在于， 所述的第 一种掺杂类型为 n型， 所述的第二种掺杂类型为 p型； 或者， 所述的第 一种掺杂类型为 p型， 所述的第二种掺杂类型为 n型。
8. 根据权利要求 5所述的半浮栅器件的制备方法， 其特征在于， 所述的第 一层绝缘薄膜、 第二层绝缘薄膜为二氧化硅、 氮化硅、 氮氧化硅或者为 高介电常数的绝缘材料， 所述的第一层导电薄膜为掺杂的多晶硅， 所述 的第二层导电薄膜为金属、 合金或者为掺杂的多晶硅。
PCT/CN2014/076438 2013-05-02 2014-04-29 一种半浮栅器件及其制造方法 WO2014177045A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US14/651,997 US9508811B2 (en) 2013-05-02 2014-04-29 Semi-floating-gate device and its manufacturing method
EP14791834.6A EP2993695A4 (en) 2013-05-02 2014-04-29 HALF-WAVE GATE DEVICE AND METHOD OF MANUFACTURING THEREOF
US15/342,328 US9748406B2 (en) 2013-05-02 2016-11-03 Semi-floating-gate device and its manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310158971.4 2013-05-02
CN2013101589714A CN103247626A (zh) 2013-05-02 2013-05-02 一种半浮栅器件及其制造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US14/651,997 A-371-Of-International US9508811B2 (en) 2013-05-02 2014-04-29 Semi-floating-gate device and its manufacturing method
US15/342,328 Division US9748406B2 (en) 2013-05-02 2016-11-03 Semi-floating-gate device and its manufacturing method

Publications (1)

Publication Number Publication Date
WO2014177045A1 true WO2014177045A1 (zh) 2014-11-06

Family

ID=48927017

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/076438 WO2014177045A1 (zh) 2013-05-02 2014-04-29 一种半浮栅器件及其制造方法

Country Status (4)

Country Link
US (2) US9508811B2 (zh)
EP (1) EP2993695A4 (zh)
CN (1) CN103247626A (zh)
WO (1) WO2014177045A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104599969A (zh) * 2015-02-02 2015-05-06 上海集成电路研发中心有限公司 一种减小槽栅结构半浮栅器件漏电的方法
US20160365456A1 (en) * 2015-06-15 2016-12-15 Stmicroelectronics, Inc. Semi-floating gate fet

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247626A (zh) * 2013-05-02 2013-08-14 复旦大学 一种半浮栅器件及其制造方法
CN104425522B (zh) * 2013-09-10 2017-10-20 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN104576646B (zh) * 2013-10-11 2017-09-05 苏州东微半导体有限公司 一种集成电路芯片及其制造方法
CN104637945B (zh) * 2013-11-08 2018-08-03 苏州东微半导体有限公司 半浮栅存储器及其制造方法和半浮栅存储器阵列
CN103606351B (zh) * 2013-11-29 2016-04-20 中国科学院上海高等研究院 有源矩阵有机发光二极管像素驱动电路及其驱动方法
CN103594059B (zh) * 2013-11-29 2017-01-11 中国科学院上海高等研究院 有源矩阵有机发光二极管像素驱动电路及其驱动方法
CN103681767B (zh) * 2013-12-19 2017-01-04 中国科学院上海高等研究院 Amoled 像素驱动电路、驱动方法及阵列驱动系统
CN103680408B (zh) * 2013-12-19 2016-07-06 中国科学院上海高等研究院 Amoled像素驱动电路、驱动方法及阵列驱动系统
CN103702043B (zh) * 2014-01-03 2017-02-08 中国科学院上海高等研究院 固定模式噪声消除电路
CN103887313B (zh) * 2014-03-04 2016-08-31 华为技术有限公司 一种半浮栅器件及其制备方法
CN104916640B (zh) * 2014-03-13 2018-07-20 中芯国际集成电路制造(上海)有限公司 一种半浮栅存储器结构
CN104916639B (zh) * 2014-03-13 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种半浮栅存储器结构及其制作方法
CN103972238A (zh) * 2014-03-31 2014-08-06 上海新储集成电路有限公司 一种存储器单元结构
CN103888692B (zh) * 2014-04-01 2017-03-22 中国科学院上海高等研究院 图像传感装置及其操作方法
CN104183594B (zh) * 2014-08-17 2017-01-25 复旦大学 一种采用半浮栅结构的氮化镓功率器件
CN104701316B (zh) * 2015-03-31 2017-09-29 上海集成电路研发中心有限公司 一种双槽形结构的半浮栅器件及其制造方法
KR101958769B1 (ko) * 2017-11-16 2019-03-15 가천대학교 산학협력단 시냅스 모방 반도체 소자 및 이를 이용한 신경망 어레이
CN110010605B (zh) * 2018-01-04 2021-04-02 中芯国际集成电路制造(上海)有限公司 存储器及其工作方法和形成方法
CN109036487B (zh) * 2018-07-20 2021-03-02 福州大学 一种基于短沟道有机晶体管的多级光存储器及其制备方法
CN109742159A (zh) * 2018-12-17 2019-05-10 复旦大学 一种低隧穿漏电半浮栅晶体管及其制备方法
CN109742073A (zh) * 2018-12-17 2019-05-10 复旦大学 一种具有高电荷保持能力的半浮栅晶体管及其制备方法
CN110416287B (zh) * 2019-07-10 2020-10-30 复旦大学 一种外延tfet沟道的半浮栅晶体管及其制备方法
US11990538B2 (en) * 2019-11-27 2024-05-21 Suzhou Oriental Semiconductor Co., Ltd. IGBT device
CN112864222B (zh) * 2019-11-27 2022-04-12 苏州东微半导体股份有限公司 半导体功率器件
CN112864221B (zh) * 2019-11-27 2022-04-15 苏州东微半导体股份有限公司 半导体超结功率器件
CN112908851B (zh) * 2019-12-03 2022-04-15 苏州东微半导体股份有限公司 半导体功率器件的制造方法
CN111477628B (zh) * 2020-04-27 2022-06-21 复旦大学 一种半浮栅tft存储器及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1540762A (zh) * 2003-01-02 2004-10-27 ǰѶϵͳ�ɷ����޹�˾ 具有沟槽型选择栅极的快闪存储器及制造方法
CN101819975A (zh) * 2010-04-28 2010-09-01 复旦大学 垂直沟道双栅隧穿晶体管及其制备方法
CN101901813A (zh) * 2010-07-20 2010-12-01 复旦大学 一种垂直结构的半导体存储器及其制造方法
CN102456745A (zh) * 2010-10-22 2012-05-16 北京大学 一种快闪存储器及其制备方法和操作方法
CN102479823A (zh) * 2010-11-30 2012-05-30 中国科学院微电子研究所 一种垂直型nrom存储结构及其制备方法
CN103247626A (zh) * 2013-05-02 2013-08-14 复旦大学 一种半浮栅器件及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3425853B2 (ja) * 1997-08-29 2003-07-14 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置
US6248633B1 (en) * 1999-10-25 2001-06-19 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
US6936887B2 (en) * 2001-05-18 2005-08-30 Sandisk Corporation Non-volatile memory cells utilizing substrate trenches
US6996009B2 (en) * 2002-06-21 2006-02-07 Micron Technology, Inc. NOR flash memory cell with high storage density
US6951782B2 (en) * 2003-07-30 2005-10-04 Promos Technologies, Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions
US7241654B2 (en) * 2003-12-17 2007-07-10 Micron Technology, Inc. Vertical NROM NAND flash memory array
US7148538B2 (en) * 2003-12-17 2006-12-12 Micron Technology, Inc. Vertical NAND flash memory array
US7190616B2 (en) * 2004-07-19 2007-03-13 Micron Technology, Inc. In-service reconfigurable DRAM and flash memory device
US8288813B2 (en) * 2004-08-13 2012-10-16 Infineon Technologies Ag Integrated memory device having columns having multiple bit lines
US7158410B2 (en) * 2004-08-27 2007-01-02 Micron Technology, Inc. Integrated DRAM-NVRAM multi-level memory
US7378707B2 (en) * 2005-05-26 2008-05-27 Micron Technology, Inc. Scalable high density non-volatile memory cells in a contactless memory array
US7547599B2 (en) * 2005-05-26 2009-06-16 Micron Technology, Inc. Multi-state memory cell
CN101494222B (zh) * 2008-01-23 2010-08-25 苏州东微半导体有限公司 半导体存储器器件、半导体存储器阵列及写入方法
US8138541B2 (en) * 2009-07-02 2012-03-20 Micron Technology, Inc. Memory cells
CN101707202B (zh) * 2009-11-20 2012-01-11 苏州东微半导体有限公司 半导体感光器件及其制造方法和应用
CN102169882B (zh) * 2010-02-26 2015-02-25 苏州东微半导体有限公司 半导体存储器器件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1540762A (zh) * 2003-01-02 2004-10-27 ǰѶϵͳ�ɷ����޹�˾ 具有沟槽型选择栅极的快闪存储器及制造方法
CN101819975A (zh) * 2010-04-28 2010-09-01 复旦大学 垂直沟道双栅隧穿晶体管及其制备方法
CN101901813A (zh) * 2010-07-20 2010-12-01 复旦大学 一种垂直结构的半导体存储器及其制造方法
CN102456745A (zh) * 2010-10-22 2012-05-16 北京大学 一种快闪存储器及其制备方法和操作方法
CN102479823A (zh) * 2010-11-30 2012-05-30 中国科学院微电子研究所 一种垂直型nrom存储结构及其制备方法
CN103247626A (zh) * 2013-05-02 2013-08-14 复旦大学 一种半浮栅器件及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2993695A4 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104599969A (zh) * 2015-02-02 2015-05-06 上海集成电路研发中心有限公司 一种减小槽栅结构半浮栅器件漏电的方法
US20160365456A1 (en) * 2015-06-15 2016-12-15 Stmicroelectronics, Inc. Semi-floating gate fet
US9799776B2 (en) * 2015-06-15 2017-10-24 Stmicroelectronics, Inc. Semi-floating gate FET
US10256351B2 (en) 2015-06-15 2019-04-09 Stmicroelectronics, Inc. Semi-floating gate FET
US10741698B2 (en) 2015-06-15 2020-08-11 Stmicroelectronics, Inc. Semi-floating gate FET

Also Published As

Publication number Publication date
EP2993695A1 (en) 2016-03-09
US20150325663A1 (en) 2015-11-12
US20170148909A1 (en) 2017-05-25
US9508811B2 (en) 2016-11-29
US9748406B2 (en) 2017-08-29
EP2993695A4 (en) 2016-12-14
CN103247626A (zh) 2013-08-14

Similar Documents

Publication Publication Date Title
WO2014177045A1 (zh) 一种半浮栅器件及其制造方法
CN104103640B (zh) 一种u形沟道的半导体器件及其制造方法
CN103872132B (zh) 金属氧化物半导体(mos)晶体管及其制作方法
WO2014161471A1 (zh) 一种u形沟道的半导体器件
US20150044843A1 (en) Semiconductor fin on local oxide
CN102543886B (zh) 一种栅控二极管半导体存储器器件的制造方法
TW200406886A (en) Semiconductor constructions
WO2011095044A1 (zh) 一种动态随机存储器的阵列结构及其制备方法
CN104701316B (zh) 一种双槽形结构的半浮栅器件及其制造方法
US11031467B2 (en) Field effect transistor based on vertically integrated gate-all-round multiple nanowire channels
WO1993007641A1 (en) Semiconductor integrated circuit device and manufacture thereof
CN103915439A (zh) 一种半导体器件及其制造方法
CN104637945B (zh) 半浮栅存储器及其制造方法和半浮栅存储器阵列
WO2021169805A1 (zh) 半导体器件制作方法
CN101393893B (zh) 具有不同侧壁层宽度的cmos器件及其制造方法
KR100832017B1 (ko) 채널면적을 증가시킨 반도체소자 및 그의 제조 방법
CN111916399B (zh) 一种半导体器件的制备方法以及半导体器件
CN102543891B (zh) 栅控二极管半导体存储器器件的制备方法
CN101866858B (zh) 凹陷沟道型pnpn场效应晶体管的制造方法
WO2014108065A1 (zh) 一种平面沟道的半导体器件及其制造方法
TWI565006B (zh) 記憶元件的製造方法
KR0177386B1 (ko) 박막트랜지스터 제조방법
KR100223795B1 (ko) 반도체소자제조방법
KR20040069859A (ko) 모스 트랜지스터 및 그 제조 방법
JPH03188669A (ja) 半導体記憶装置およびその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14791834

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2014791834

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014791834

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 14651997

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE