WO2014108065A1 - 一种平面沟道的半导体器件及其制造方法 - Google Patents

一种平面沟道的半导体器件及其制造方法 Download PDF

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Publication number
WO2014108065A1
WO2014108065A1 PCT/CN2014/070278 CN2014070278W WO2014108065A1 WO 2014108065 A1 WO2014108065 A1 WO 2014108065A1 CN 2014070278 W CN2014070278 W CN 2014070278W WO 2014108065 A1 WO2014108065 A1 WO 2014108065A1
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Prior art keywords
gate
semiconductor device
floating gate
planar channel
drain
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PCT/CN2014/070278
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English (en)
French (fr)
Inventor
刘磊
刘伟
王鹏飞
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苏州东微半导体有限公司
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Priority claimed from CN201310006320.3A external-priority patent/CN103915439A/zh
Priority claimed from CN201310433668.0A external-priority patent/CN104465381B/zh
Application filed by 苏州东微半导体有限公司 filed Critical 苏州东微半导体有限公司
Publication of WO2014108065A1 publication Critical patent/WO2014108065A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Definitions

  • the present invention relates to a planar channel semiconductor device and a method of fabricating the same, and to the field of semiconductor memory technology.
  • Background Art Semiconductor memories are widely used in various electronic products. Different application areas have different requirements for the construction, performance and density of semiconductor memories. For example, static random access memories (SRAMs) have high random access speeds and low integration densities, while standard dynamic random access memories (DRAMs) have high density and moderate random access speeds.
  • SRAMs static random access memories
  • DRAMs standard dynamic random access memories
  • the semiconductor substrate 301 may be single crystal silicon or silicon on an insulator, and is doped with a low concentration of n-type or p-type impurities.
  • the source region 302 has the same doping type as the drain region 303 and is opposite to the doping type of the semiconductor substrate 301.
  • the doping region 304 has a doping type opposite to that of the semiconductor substrate 301, and its doping concentration is significantly lower than the doping concentration of the drain region 303.
  • the floating gate region 306 having conductivity as a charge storage node is generally opposite to the doping type of the source region 302 and the drain region 303, and is the same as the doping type of the semiconductor substrate 301.
  • Impurities in the floating gate region 306 may diffuse into the doped region 304 to form a diffusion region 305.
  • the source region conductive layer 315 and the drain region conductive layer 316 may be metal, alloy or doped polysilicon.
  • the first insulating film 308 and the second insulating film 309 may be silicon dioxide, silicon nitride, silicon oxynitride or a high dielectric constant insulating material.
  • the gate spacer 314 is an insulating film of silicon dioxide or silicon nitride material.
  • the diffusion region 305 and the doping region 304 form a pn junction diode
  • the pn junction diode and the insulating film 309 and the control gate 307 form a gate-controlled pn junction diode with the gate 307 as a gate, and the anode of the gate-controlled pn junction diode.
  • the cathode is connected to the drain region 303; or the cathode of the pn junction gated diode is connected to the floating gate region 306, and the anode is connected to the drain region 303.
  • the amount of charge stored in the floating gate region 306 can be varied by charging or discharging the floating gate region 306 by a gated pn junction diode, the amount of which determines the logic state of the semiconductor memory device.
  • the control gate 307 is only located above the upper surface of the floating gate region 306 and extends over the p-n junction diode.
  • the contact area of the control gate 307 on the upper surface of the floating gate region 306 and the floating gate region 306 is drastically reduced, so that the capacitive coupling ratio of the control gate 307 to the floating gate region 306 is lowered.
  • a higher operating voltage is required to read and write data, which increases the power consumption of the chip.
  • a planar channel semiconductor device comprising:
  • the above-described planar channel semiconductor device wherein: the semiconductor substrate portion between the source and the second doped well forms a current channel region.
  • the above-described planar channel semiconductor device further comprising: a first doped well formed on one side of the source while forming the second doped well, the source Formed in the first doped well, a portion of the semiconductor substrate between the first doped well and the second doped well forms a current channel region.
  • the above-described planar channel semiconductor device wherein: an anode of the pn junction diode is connected to the floating gate, and a cathode of the pn junction diode is connected to the drain; or A cathode of the pn junction diode is connected to the floating gate, and an anode of the pn junction diode is connected to the drain.
  • the above-mentioned planar channel semiconductor device wherein: the first insulating film and the second insulating film are respectively silicon dioxide, silicon nitride, silicon oxynitride, and having a high dielectric constant value.
  • the insulating material or any of the laminates therebetween has a physical thickness ranging from 1 nm to 20 nm.
  • the above-described planar channel semiconductor device wherein: the floating gate is any one of polysilicon, tungsten or titanium nitride.
  • the above-mentioned planar channel semiconductor device wherein: the first doping type is n-type, the second doping type is p-type; or, the first doping type For p-type, The second type of doping is n-type.
  • the above-described planar channel semiconductor device wherein: the source and the drain are doped regions of high doping concentration respectively formed in the semiconductor substrate.
  • the source and the drain are each of silicon germanium or silicon carbide.
  • Etching the first conductive film to form a floating gate the floating gate covers the floating gate opening; depositing a second insulating film on the surface of the formed structure;
  • Etching the doped polysilicon, the remaining doped polysilicon after etching forms a polysilicon control gate, the polysilicon control gate covering and surrounding the floating gate on the upper surface and both sides of the floating gate;
  • Gate sidewalls are formed on both sides of the polysilicon control gate; self-aligned source and drain are formed in the semiconductor substrate on both sides of the polysilicon control gate.
  • the source and the drain form a source and a drain having a high doping concentration in a semiconductor substrate by an ion implantation process.
  • the source and the drain are source and drain etched on the semiconductor substrate on both sides of the polysilicon control gate, and then through an epitaxial process. The source and drain of the silicon carbide or silicon germanium material are grown.
  • the method for manufacturing a planar channel semiconductor device as described above further includes:
  • Polishing is performed so that the polished metal gate material occupies the position of the original polysilicon control gate, thereby forming a metal control gate.
  • the second insulating film is left or etched away, and then a fourth insulating film and a metal gate material are deposited. .
  • the method for fabricating a planar channel semiconductor device wherein: the fourth insulating film is silicon dioxide, silicon nitride, silicon oxynitride, an insulating material having a high dielectric constant value, or between them Any of the laminates having a physical thickness ranging from 1 nm to 20 nm.
  • a planar channel semiconductor device of the present invention stores information by a floating gate and charges or discharges the floating gate through a gate-controlled pn junction diode having a gate as a control gate.
  • the control gate of the planar channel semiconductor device of the present invention covers and surrounds the floating gate on the upper surface and both sides of the floating gate, and can effectively increase the contact area between the control gate and the floating gate even in an advanced process, thereby enabling control
  • the capacitive coupling ratio of the gate to the floating gate is improved, and only a lower operating voltage is required for reading and writing data, which reduces the power consumption of the chip.
  • FIG. 1 is a cross-sectional view of a semiconductor memory device proposed in Chinese Patent No. 201010254185.0;
  • FIG. 2 is a cross-sectional view showing a first embodiment of a planar channel semiconductor device according to the present invention; a transfer characteristic diagram of a semiconductor device of a planar channel;
  • FIGS. 5 to 11 are a first embodiment of a method of fabricating a planar channel semiconductor device of the present invention. Process flow chart;
  • 12 to 15 are process flow diagrams showing a second embodiment of a method of fabricating a planar channel semiconductor device of the present invention.
  • Figure 16 is a cross-sectional view showing one embodiment of a planar channel semiconductor device of a dual memory cell of the present invention.
  • Figure 17 is a circuit diagram of a memory cell array composed of a plurality of planar channel semiconductor devices of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.
  • the thickness of layers and regions are exaggerated for convenience of explanation, and the illustrated sizes do not represent actual dimensions.
  • the drawings are schematic illustrations of idealized embodiments of the present invention, and the illustrated embodiments of the present invention should not be considered limited to the particular shapes of the regions shown in the figures, but rather to the resulting shapes, such as manufacturing variations.
  • the curves obtained by etching generally have the characteristics of being curved or rounded, but in the embodiments of the present invention, they are all represented by rectangles, and the representations in the figures are schematic, but this should not be construed as limiting the scope of the invention.
  • the term substrate as used may be understood to include a semiconductor wafer being processed, possibly including other thin film layers prepared thereon.
  • Figure 2 is a first embodiment of a planar channel semiconductor device of the present invention, which is a cross-sectional view along the length of the current channel of the device.
  • the planar channel semiconductor device of the present embodiment includes a semiconductor substrate 200 having a first doping type, and the semiconductor substrate 200 may be either silicon or silicon on the insulator.
  • the first type of doping may be either n-type doping or p-type doping.
  • the floating gate 205 may be any one of polycrystalline silicon, tungsten or titanium nitride.
  • a floating gate opening 204 is formed in the first insulating film 203, and a second doping well 202 of the second doping type is formed in the semiconductor substrate 200 and under the floating gate opening 204.
  • the second doping type is opposite to the doping type of the first doping type, such as the first doping type n-type, the second doping type is p-type, or, correspondingly, the first doping
  • the impurity type is p type, and the second doping type is n type.
  • a second doping type of highly doped source 209 and drain 210 are formed in the semiconductor substrate 200 by an ion implantation process, and the drain 210 is located in the second doped well 202.
  • the second doped well 202 is formed, the first doped well 201 formed at one side of the source 209, the source 209 is formed in the first doped well 201, such that the first doped well 201 and the second A portion of the semiconductor substrate between the doped wells 202 forms a current channel region 403.
  • only the second doped well 202 may be formed without forming the first doped well 201 such that the portion of the semiconductor substrate between the source 209 and the second doped well 202 forms a current channel region.
  • the doping impurities of the floating gate 205 are diffused into the second doped well 202 through the floating gate opening 204.
  • the first doping type of diffusion region 402, the diffusion region 402 and the second doped well 202 have opposite doping types, such that the diffusion region 402 and the second doped well 202 form a pn junction diode, and the pn junction diode floats
  • the gate opening 204 connects the floating gate 205 and the drain 210.
  • the first doping type is p-type and the second doping type is n-type
  • the anode of the pn junction diode is connected to the floating gate 205, and the cathode thereof is connected to the drain 210.
  • the cathode of the pn junction diode is connected to the floating gate 205, and the anode thereof is connected to the drain 210.
  • a second insulating film 206 and a control gate 207 are formed on the upper surface and both sides of the floating gate 205.
  • the second insulating film 206 may be silicon dioxide, silicon nitride, silicon oxynitride, or a high dielectric constant value.
  • the insulating material or any of the laminates therebetween, the high dielectric constant insulating material includes, but is not limited to, yttrium oxide, and has a physical thickness ranging from 1 nm to 20 nm.
  • Control gate 207 can be any of a polysilicon control gate or a metal control gate.
  • the metal control gate has a lower conduction resistance than the polysilicon control gate, but needs to be formed after the source and drain are formed to avoid damage to the metal control gate caused by the high temperature annealing process of the source and drain.
  • Fig. 3 is a graph showing the transfer characteristics of the planar channel semiconductor device shown in Fig. 2. It can be seen that the turn-on voltage of the device is shifted after writing logic "1" and writing logic "0", so that the planar channel semiconductor device can store logic "1" and logic "0".
  • the source 209 and the drain 210 are high doping concentrations of source and drain formed in the semiconductor substrate 200 by an ion implantation process.
  • the source 209 and the drain 210 of the planar channel semiconductor device of the present invention may also be formed by epitaxial growth of silicon carbide or silicon germanium material.
  • the source and drain formed by the epitaxial process are different from the shapes of the source and drain formed by the ion implantation process, and FIG. 4 exemplarily shows a source formed by growing a silicon carbide or a silicon germanium material by an epitaxial process. Schematic diagram of the structure of the pole 209 and the drain 210.
  • the planar channel semiconductor device of the present invention can be fabricated by a number of methods, and the process flow for fabricating an embodiment of the planar trench semiconductor device of the present invention is described below:
  • a lithography is deposited on the surface of the semiconductor substrate 200 having the first doping type in which a shallow trench isolation structure (a structure well known in the art, not shown) has been formed.
  • the glue 901 is masked, exposed, developed to form a pattern, and then a first doped well 201 having a second doping type is formed on both sides of the formed photoresist pattern in the semiconductor substrate 200 by an ion implantation process.
  • a second doped well 202, and the portion of the semiconductor substrate between the first doped well 201 and the second doped well 202 forms a current channel region of the device.
  • the semiconductor substrate 200 may be any of silicon or silicon on insulator.
  • the first doping type is p-type
  • the second doping type is n-type; or, correspondingly, the first doping type is n-type, and the second doping type is p-type.
  • only the second doped well 202 may be formed without forming the first doped well 201, so that the second doped well 202 is formed by a subsequent process.
  • the portion of the semiconductor substrate between the source 209 forms a current channel region.
  • a first insulating film 203 is grown on the surface of the semiconductor substrate 200.
  • the first insulating film 203 may be silicon dioxide, silicon nitride, silicon oxynitride, or a high dielectric constant value.
  • the insulating material is either any of the laminates between them.
  • a photoresist is deposited on the first insulating film 203 and the position of the floating gate opening 204 is defined by a photolithography process, and then the first insulating film 203 is etched by using the photoresist as a mask.
  • a floating gate opening 204 is formed in the first insulating film 203, and the floating gate opening 204 should be located above the second doped well 202, and a distance from a side edge of the current channel region to the current channel region should be at least More than 1 nm, after stripping the photoresist, as shown in FIG.
  • a first conductive film having a first doping type is deposited on the surface of the formed structure, and then a photoresist is deposited over the formed first conductive film and passed through the light.
  • the engraving process defines the position of the floating gate 205, and then etches the first conductive film with the photoresist as a mask, engraving
  • the first conductive film remaining after the etching forms the floating gate 205, and the floating gate 205 may be any one of polysilicon, tungsten or titanium nitride.
  • the floating gate 205 should cover at least the current channel region and the floating gate opening 204, and when high temperature annealing is performed, dopant impurities in the floating gate 205 are diffused into the second doped well 202 through the floating gate opening 204 to form a diffusion region 402. . Then, the first insulating film 203 is etched by using the floating gate 205 as a mask, and the photoresist is stripped as shown in FIG. 7.
  • a second insulating film 206 is deposited over the formed structure, and the second insulating film 206 may be silicon dioxide, silicon nitride, silicon oxynitride, an insulating material having a high dielectric constant value, or between them. Any of the stacks.
  • a layer of doped polysilicon is deposited on the second insulating film 206, and a third insulating film 401 is deposited over the doped polysilicon.
  • the third insulating film 401 is silicon dioxide or nitrided. Any of silicon.
  • the formed third insulating film 401 and doped polysilicon are etched by a photolithography process and an etching process, and the remaining doped polysilicon after etching forms a polysilicon control gate 207, and the polysilicon control gate 207 should be in the floating gate 205.
  • the upper surface and the two sides cover and surround the floating gate 205, and the photoresist is stripped as shown in FIG.
  • a gate spacer 208 is formed on both sides of the polysilicon control gate 207, and then the exposed second insulating film 206 is continuously etched along the edge of the gate spacer 208, as shown in FIG.
  • the gate spacer 208 may be any one of silicon dioxide or silicon nitride.
  • source and drain etching are performed on both sides of the gate spacer 208, and silicon or silicon carbide material is epitaxially epitaxially grown by a selective epitaxial process at the source and drain etched regions to form a source 209 and a drain.
  • a high concentration ion doping region may be formed in the first doped well 201 and the second doped well 202 by ion implantation without performing source, drain etching, and epitaxial processes, respectively.
  • Source 209 and drain 210 are shown in FIG.
  • FIG. 11 are flowcharts showing a manufacturing process of an embodiment of a planar channel semiconductor device using a polysilicon control gate structure according to the present invention, wherein a polysilicon control gate 207 is formed first, and then a source 209 is formed. Drain 210. If a metal control gate structure is employed, in order to prevent the metal control gate from being damaged in the high temperature annealing of the source 209 and the drain 210, it is necessary to first form the source 209 and the drain 210 to form a metal control gate. When the metal control gate is prepared, the polysilicon control gate 207 can be used as a sacrificial layer material on the basis of FIG. 10 or FIG. 11, and after the polysilicon control gate 207 is etched away, the metal gate material occupies the position of the original polysilicon control gate 207. Thus, a metal control gate is formed, and the main process flow is as follows:
  • first interlayer dielectric material 211 on the surface of the structure shown in FIG. 10, and polishing the formed first interlayer dielectric material 211 by a chemical mechanical polishing technique until the surface of the polysilicon control gate 207 is exposed, as shown in 12 is shown.
  • the polysilicon control gate 207 is then etched away and the exposed second insulating film 206 is etched away, as shown in FIG.
  • a fourth insulating film 212 and a metal gate material are deposited on the surface of the formed structure, followed by chemical mechanical polishing so that the polished metal gate material occupies the position of the original polysilicon control gate 207 to form a metal control gate 213.
  • the fourth insulating film 212 may be any of silicon dioxide, silicon nitride, silicon oxynitride, an insulating material having a high dielectric constant, or a laminate therebetween.
  • the second insulating film 206 may be left, and then the fourth insulating film 212 and the metal gate material may be deposited, or the second insulating film 206 may be retained.
  • a metal gate material is directly deposited on the second insulating film 206.
  • a second interlayer dielectric material 214 is deposited over the formed structure, and then a contact hole is formed in the formed second interlayer dielectric material 214 and the first interlayer dielectric material 211. And forming a source electrode 215, a drain electrode 217, and a gate electrode 216, which are processes well known in the art.
  • Figure 16 is an embodiment of a planar channel semiconductor device structure of a dual memory cell fabricated by a method of fabricating a planar channel semiconductor device of the present invention, which is composed of two planar channels as shown in Figure 15.
  • the semiconductor device is constructed, and the two planar channel semiconductor devices have a symmetrical structure.
  • the two planar channel semiconductor devices share the second doped well 202, the drain 210, and The drain electrode 217, the semiconductor device structure of the planar channel of the dual memory cell can store two bits of data.
  • Figure 17 is a circuit diagram of a memory cell array composed of a plurality of planar channel semiconductor devices as shown in Figure 15 fabricated by a method of fabricating a planar channel semiconductor device of the present invention. As shown in FIG.
  • one of the plurality of source lines SL 603a to 603b is connected to the sources of the plurality of semiconductor devices.
  • any one of them is connected to a control gate of a plurality of semiconductor devices.
  • the plurality of bit lines BL 602a to 602d any one of them is connected to the drains of the plurality of semiconductor devices. Any one of the plurality of bit lines BL 602a-602d can be combined with any of the plurality of word lines WL 601a-601d to select a separate semiconductor gate device.
  • Word lines WL 601a-601d may be selected by word line address decoder 901, bit lines BL 602a-602d may be selected by a bit line selection control module 902, and bit line selection control module 902 generally includes an address decoder, a multiplex A selector and a set of sense amplifiers.
  • the source lines SL 603a and 603b may be connected by a common source line or a source line selection control module.
  • the present invention has various embodiments, and all technical solutions formed by equivalent transformation or equivalent transformation are within the scope of the present invention.

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Abstract

本发明属于半导体存储器技术领域，具体涉及一种平面沟道的半导体器件及其制造方法，包括至少一个半导体衬底、一个源极、一个漏极、一个浮栅、一个控制栅以及一个连接所述浮栅和漏极并以所述控制栅为栅极的栅控p-n结二极管。本发明的平面沟道的半导体器件用浮栅存储信息，并通过所述栅控p-n结二极管对浮栅进行充电或放电，具有控制栅对浮栅的电容耦合率高、对数据进行读写时的操作电压低等优点。本发明的平面沟道的半导体器件可以通过先栅工艺和后栅工艺制造，而且可以自对准的形成源极和漏极，工艺过程简单，易于控制。

Description

一种平面沟道的半导体器件及其制造方法 技术领域 本发明涉及一种平面沟道的半导体器件及其制造方法， 属于半导体存储器 技术领域。 背景技术 半导体存储器被广泛应用于各种电子产品之中。 不同应用领域对半导体存 储器的构造、 性能和密度有着不同的要求。 比如， 静态随机存储器（SRAM)拥 有很高的随机存取速度和较低的集成密度， 而标准的动态随机存储器 （DRAM) 则具有很高的密度和中等的随机存取速度。
图 1为中国专利 201010254185.0中提出的一种半导体存储器， 其中， 半导 体衬底 301可以为单晶硅或者为绝缘体上的硅， 且被低浓度的 n型或 p型杂质 掺杂过。 源区 302与漏区 303的掺杂类型相同， 且与半导体衬底 301的掺杂类 型相反。 掺杂区 304具有与半导体衬底 301相反的掺杂类型， 且其掺杂浓度明 显低于漏区 303 的掺杂浓度。 作为电荷存储节点的具有导电性的浮栅区 306通 常与源区 302、漏区 303的掺杂类型相反，且与半导体衬底 301的掺杂类型相同。 浮栅区 306中的杂质会扩散至掺杂区 304内形成扩散区 305。源区导电层 315和 漏区导电层 316可以为金属、 合金或者为掺杂的多晶硅。 第一层绝缘薄膜 308 和第二层绝缘薄膜 309可以为二氧化硅、 氮化硅、 氮氧化硅或者高介电常数的 绝缘材料。 栅极侧墙 314 为二氧化硅或者氮化硅材料的绝缘薄膜。 扩散区 305 与掺杂区 304构成 p-n结二极管， 该 p-n结二极管与绝缘薄膜 309、 控制栅 307 构成一个以控制栅 307为栅极的栅控 p-n结二极管，该栅控 p-n结二极管的阳极 与浮栅区 306相连接， 阴极与漏区 303相连接； 或者， 该 p-n结栅控二极管的阴 极与浮栅区 306相连接， 阳极与漏区 303相连接。 同时， 通过栅控 p-n结二极管 对浮栅区 306进行充电或放电可以改变储存在浮栅区 306内的电荷数量， 此电 荷数量决定了半导体存储器器件的逻辑状态。
中国专利 201010254185.0中提出的半导体存储器， 控制栅 307仅仅位于浮 栅区 306的上表面之上且延伸至所述 p-n结二极管之上。当半导体器件工艺进入 到 65纳米技术节点及以下， 控制栅 307在浮栅区 306的上表面与浮栅区 306的 接触面积急剧减少， 使得控制栅 307对浮栅区 306的电容耦合率降低， 在对数 据进行读写时需要较高的操作电压， 提高了芯片功耗。 发明内容 鉴于上述现有技术存在的缺陷， 本发明的目的是提出一种平面沟道的半导 体器件及其制造方法。
本发明的目的将通过以下技术方案得以实现：
一种平面沟道的半导体器件， 包括：
在第一种掺杂类型的半导体衬底上形成的第一层绝缘薄膜和第一种掺杂类 型的浮栅；
在所述第一层绝缘薄膜中形成的一个浮栅开口， 在所述半导体衬底内且位 于所述浮栅开口之下形成的第二种掺杂类型的第二掺杂阱；
在所述半导体衬底内形成的第二种掺杂类型的源极和漏极， 所述漏极位于 所述第二掺杂阱内；
通过所述浮栅开口在所述浮栅和漏极之间形成的一个 p-n结二极管； 在所述浮栅的上表面及两侧形成的第二层绝缘薄膜和控制栅，所述 p-n结二 极管、第二层绝缘薄膜和控制栅形成一个以所述控制栅为栅极的栅控 p-n结二极 管。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述源极与第二掺杂 阱之间的半导体衬底部分形成电流沟道区。 优选的， 上述的一种平面沟道的半导体器件， 其中： 还包括在形成所述第 二掺杂阱的同时， 在所述源极的一侧形成的第一掺杂阱， 所述源极形成于所述 第一掺杂阱内， 所述第一掺杂阱与第二掺杂阱之间的半导体衬底部分形成电流 沟道区。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述 p-n结二极管的阳 极与所述浮栅相连接， 所述 p-n结二极管的阴极与所述漏极相连接； 或者， 所述 p-n结二极管的阴极与所述浮栅相连接， 所述 p-n结二极管的阳极与所述漏极相 连接。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述第一层绝缘薄膜 和第二层绝缘薄膜分别为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数值的 绝缘材料或者它们之间的叠层中的任意一种，其物理厚度范围为 1纳米 -20纳米。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述浮栅为多晶硅、 钨或者氮化钛中的任意一种。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述控制栅为多晶硅 控制栅或者金属控制栅中的任意一种。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述第一种掺杂类型 为 n型， 所述第二种掺杂类型为 p型； 或者， 所述第一种掺杂类型为 p型， 所 述第二种掺杂类型为 n型。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述源极和漏极为分 别在所述半导体衬底内形成的高掺杂浓度的掺杂区。 优选的， 上述的一种平面沟道的半导体器件， 其中： 所述源极和漏极分别 为锗化硅或者碳化硅中的任意一种。 如上所述的一种平面沟道的半导体器件的制造方法， 包括：
在第一种掺杂类型的半导体衬底内形成第二种掺杂类型的第二掺杂阱； 在所述半导体衬底的表面形成第一层绝缘薄膜， 并刻蚀所述第一层绝缘薄 膜形成一个浮栅开口， 所述浮栅开口位于所述第二掺杂阱之上；
在已形成的结构的表面淀积第一种掺杂类型的第一层导电薄膜；
刻蚀所述第一层导电薄膜形成浮栅， 所述浮栅覆盖所述浮栅开口； 在已形成的结构的表面淀积第二层绝缘薄膜；
在所述第二层绝缘薄膜之上淀积一层掺杂的多晶硅；
刻蚀所述掺杂的多晶硅， 刻蚀后剩余的掺杂的多晶硅形成多晶硅控制栅， 所述多晶硅控制栅在所述浮栅的上表面及两侧覆盖并包围所述浮栅；
在所述多晶硅控制栅的两侧形成栅极侧墙； 在所述多晶硅控制栅的两侧的半导体衬底内形成自对准的源极和漏极。 优选的， 上述的平面沟道的半导体器件的制造方法， 其中： 所述源极和漏 极是通过离子注入工艺在半导体衬底内形成高掺杂浓度的源极和漏极。 优选的， 上述的平面沟道的半导体器件的制造方法， 其中： 所述源极和漏 极是先在多晶硅控制栅的两侧对半导体衬底进行源、 漏刻蚀， 再通过外延工艺 生长碳化硅或者锗化硅材料的源极和漏极。 如上所述的平面沟道的半导体器件的制造方法， 还包括：
覆盖所形成的结构淀积一层层间介质材料， 之后进行抛光直至露出所述多 晶硅控制栅；
刻蚀掉所述多晶硅控制栅；
在所形成结构的表面淀积金属栅材料；
进行抛光使得抛光后的金属栅材料占据原来的多晶硅控制栅的位置， 从而 形成金属控制栅。 优选的， 上述的平面沟道的半导体器件的制造方法， 其中： 刻蚀掉所述多 晶硅控制栅后， 保留或者刻蚀掉第二层绝缘薄膜， 然后淀积第四层绝缘薄膜和 金属栅材料。
优选的， 上述的平面沟道的半导体器件的制造方法， 其中： 所述第四层绝 缘薄膜为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数值的绝缘材料或者它 们之间的叠层中的任意一种， 其物理厚度范围为 1纳米 -20纳米。
本发明的突出效果为： 本发明的一种平面沟道的半导体器件用浮栅存储信 息， 并通过一个以控制栅为栅极的栅控 p-n结二极管对浮栅进行充电或者放电。 本发明的平面沟道的半导体器件的控制栅在浮栅的上表面及两侧覆盖并包围浮 栅， 即使在先进工艺中也可以有效的增大控制栅与浮栅的接触面积， 从而使得 控制栅对浮栅的电容耦合率提高， 在对数据进行读写时只需要较低的操作电压 便可以实现， 降低了芯片功耗。 本发明的平面沟道的半导体器件可以通过先栅 工艺和后栅工艺制造， 而且可以自对准的形成源极和漏极， 工艺过程简单， 易 于控制。 以下便结合实施例附图， 对本发明的具体实施方式作进一步的详述， 以使 本发明技术方案更易于理解、 掌握。 附图说明 图 1为中国专利 201010254185.0中提出的一种半导体存储器的剖面图； 图 2为本发明的一种平面沟道的半导体器件的第一个实施例的剖面图； 图 3为图 2所示的平面沟道的半导体器件的转移特性曲线图；
图 4为本发明的一种平面沟道的半导体器件的第二个实施例的剖面图； 图 5至图 11是本发明的一种平面沟道的半导体器件的制造方法的第一个实 施例的工艺流程图；
图 12至图 15是本发明的一种平面沟道的半导体器件的制造方法的第二个 实施例的工艺流程图；
图 16是本发明的双存储单元的平面沟道的半导体器件的一个实施例的剖面 图；
图 17是本发明的由多个平面沟道的半导体器件组成的存储单元阵列的电路 示意图。 具体实施方式 下面结合附图与具体实施方式对本发明作进一步详细的说明。 在图中， 为 了方便说明， 放大了层和区域的厚度， 所示大小并不代表实际尺寸。 参考图是 本发明的理想化实施例的示意图， 本发明所示的实施例不应该被认为仅限于图 中所示区域的特定形状， 而是包括所得到的形状， 比如制造引起的偏差。 例如 刻蚀得到的曲线通常具有弯曲或圆润的特点， 但在本发明的实施例中， 均以矩 形表示， 图中的表示是示意性的， 但这不应该被认为是限制本发明的范围。 同 时在下面的描述中， 所使用的术语衬底可以理解为包括正在工艺加工中的半导 体晶片， 可能包括在其上所制备的其它薄膜层。
图 2 是本发明的平面沟道的半导体器件的第一个实施例， 它是沿该器件电 流沟道长度方向的剖面图。 如图 2所示， 本实施例的平面沟道的半导体器件包 括一个具有第一种掺杂类型的半导体衬底 200，半导体衬底 200可以为硅或者绝 缘体上的硅中的任意一种。 第一种掺杂类型可以为 n型掺杂， 也可以为 p型掺 杂。 在半导体衬底 200上形成的第一层绝缘薄膜 203和第一种掺杂类型的浮栅 205， 第一层绝缘薄膜 203可以为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常 数值的绝缘材料或者它们之间的叠层中的任意一种， 高介电常数的绝缘材料包 括但不局限于为氧化铪， 其物理厚度范围为 1纳米 -20纳米。 浮栅 205可以为多 晶硅、 钨或者氮化钛中的任意一种。 在第一层绝缘薄膜 203 中形成的一个浮栅 开口 204，在半导体衬底 200内且位于浮栅开口 204之下形成的第二种掺杂类型 的第二掺杂阱 202。第二种掺杂类型与第一种掺杂类型为相反的掺杂类型， 比如 第一种掺杂类型 n型， 则第二种掺杂类型为 p型， 或者， 相应的， 第一种掺杂 类型为 p型， 则第二种掺杂类型为 n型。
通过离子注入工艺在半导体衬底 200 内形成的第二种掺杂类型的高掺杂浓 度的源极 209和漏极 210， 且漏极 210位于第二掺杂阱 202内。在形成第二掺杂 阱 202时， 在源极 209的一侧同时形成的第一掺杂阱 201， 源极 209形成于第一 掺杂阱 201 内， 这样第一掺杂阱 201与第二掺杂阱 202之间的半导体衬底部分 形成电流沟道区 403。 可选的， 可以只形成第二掺杂阱 202， 而不形成第一掺杂 阱 201，这样源极 209与第二掺杂阱 202之间的半导体衬底部分会形成电流沟道 区。
浮栅 205的掺杂杂质会通过浮栅开口 204扩散至第二种掺杂阱内 202形成 第一种掺杂类型的扩散区 402，扩散区 402与第二掺杂阱 202具有相反的掺杂类 型， 从而扩散区 402与第二掺杂阱 202形成一个 p-n结二极管， p-n结二极管通 过浮栅开口 204将浮栅 205和漏极 210连接。 当第一种掺杂类型为 p型、 第二 种掺杂类型为 n型时， p-n结二极管的阳极与浮栅 205相连接，其阴极与漏极 210 相连接。 当第一种掺杂类型为 n型、 第二种掺杂类型为 p型时， p-n结二极管的 阴极与浮栅 205相连接， 其阳极与漏极 210相连接。 在浮栅 205的上表面及两 侧形成的第二层绝缘薄膜 206和控制栅 207，第二层绝缘薄膜 206可以为二氧化 硅、 氮化硅、 氮氧化硅、 具有高介电常数值的绝缘材料或者它们之间的叠层中 的任意一种， 高介电常数的绝缘材料包括但不局限于为氧化铪， 其物理厚度范 围为 1纳米 -20纳米。 扩散区 402与第二掺杂阱 202形成的 p-n结二极管与第二 层绝缘薄膜 206和控制栅 207形成一个以控制栅 207为栅极的栅控 p-n结二极管。 控制栅 207可以为多晶硅控制栅或者金属控制栅中的任意一种。 金属控制栅具 有比多晶硅控制栅更低的导电电阻， 但是需要在源极和漏极形成之后形成， 以 避免源极和漏极的高温退火工艺对金属控制栅造成损伤。
图 3为图 2所示的平面沟道的半导体器件的转移特性曲线图。 可以看到在 写入逻辑 " 1 "和写入逻辑 "0"后器件的开启电压发生偏移， 使得该平面沟道 的半导体器件能够存储逻辑 " 1 "和逻辑 "0"。
图 2所示的本发明的平面沟道的半导体器件的实施例中， 源极 209和漏极 210是通过离子注入工艺在半导体衬底 200形成的高掺杂浓度的源极和漏极。可 选的， 本发明的平面沟道的半导体器件的源极 209和漏极 210也可以通过外延 工艺生长碳化硅或者锗化硅材料形成。 通过外延工艺形成的源极和漏极与通过 离子注入工艺形成的源极和漏极的形状是不一样的， 图 4示例性的展示了通过 外延工艺生长碳化硅或者锗化硅材料形成的源极 209和漏极 210的结构示意图。 本发明的平面沟道的半导体器件可以通过很多方法制造， 以下所叙述的是 制造本发明的平面沟道的半导体器件的一个实施例的工艺流程：
首先， 如图 5 所示， 在已形成浅沟槽隔离结构 （业界所熟知的结构， 图中 未示出） 的具有第一种掺杂类型的半导体衬底 200 的表面淀积一层光刻胶 901 并掩膜、 曝光、 显影形成图形， 然后通过离子注入工艺在半导体衬底 200 内、 所形成的光刻胶图形的两侧分别形成具有第二种掺杂类型的第一掺杂阱 201 和 第二掺杂阱 202，且位于第一掺杂阱 201和第二掺杂阱 202之间的半导体衬底部 分形成器件的电流沟道区。 半导体衬底 200可以为硅或者绝缘体上的硅中的任 意一种。 第一种掺杂类型为 p型， 第二种掺杂类型为 n型； 或者， 对应的， 第 一种掺杂类型为 n型， 第二种掺杂类型为 p型。
可选的， 在进行上述离子注入时， 通过控制光刻工艺的图形， 可以只形成 第二掺杂阱 202， 而不形成第一掺杂阱 201， 这样第二掺杂阱 202与后续工艺形 成的源极 209之间的半导体衬底部分会形成电流沟道区。
剥除光刻胶 901后， 在半导体衬底 200的表面生长第一层绝缘薄膜 203， 第 一层绝缘薄膜 203 可以为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数值的 绝缘材料或者为它们之间的叠层中的任意一种。 接着在第一层绝缘薄膜 203 之 上淀积一层光刻胶并通过光刻工艺定义出浮栅开口 204 的位置， 然后以光刻胶 为掩膜对第一层绝缘薄膜 203进行刻蚀， 在第一层绝缘薄膜 203 中形成一个浮 栅开口 204， 浮栅开口 204应位于第二掺杂阱 202之上， 并且其靠近电流沟道区 的一侧边沿与电流沟道区的距离应至少大于 1纳米， 剥除光刻胶后如图 6所示。
接下来， 在已形成结构的表面上淀积一层具有第一种掺杂类型的第一层导 电薄膜， 接着在所形成的第一层导电薄膜之上淀积一层光刻胶并通过光刻工艺 定义出浮栅 205 的位置， 然后以光刻胶为掩膜对第一层导电薄膜进行刻蚀， 刻 蚀后剩余的第一层导电薄膜形成浮栅 205， 浮栅 205可以为多晶硅、钨或者氮化 钛中的任意一种。浮栅 205应至少覆盖电流沟道区和浮栅开口 204， 而且在进行 高温退火时，浮栅 205中的掺杂杂质会通过浮栅开口 204扩散至第二掺杂阱 202 中形成扩散区 402。接着以浮栅 205为掩膜对第一层绝缘薄膜 203进行刻蚀， 剥 除光刻胶后如图 7所示。
接下来， 覆盖所形成的结构淀积第二层绝缘薄膜 206， 第二层绝缘薄膜 206 可以为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数值的绝缘材料或者它们 之间的叠层中任意一种。 接着在第二层绝缘薄膜 206之上淀积一层掺杂的多晶 硅， 并在掺杂的多晶硅之上淀积第三层绝缘薄膜 401， 第三层绝缘薄膜 401为二 氧化硅或者为氮化硅中的任意一种。 然后通过光刻工艺和刻蚀工艺刻蚀所形成 的第三层绝缘薄膜 401 和掺杂的多晶硅， 刻蚀后剩余的掺杂的多晶硅形成多晶 硅控制栅 207， 多晶硅控制栅 207应在浮栅 205上表面及两侧覆盖并包围浮栅 205， 剥除光刻胶后如图 8所示。
接下来， 在多晶硅控制栅 207的两侧形成栅极侧墙 208， 之后沿着栅极侧墙 208的边沿继续刻蚀掉暴露出的第二层绝缘薄膜 206，如图 9所示。栅极侧墙 208 可以为二氧化硅或者氮化硅中的任意一种。
接下来， 在栅极侧墙 208 的两侧进行源、 漏刻蚀， 并在源、 漏刻蚀后的位 置处通过选择性外延工艺外延锗化硅或者碳化硅材料， 以形成源极 209和漏极 210， 如图 10所示。 可选的， 可以不进行源、 漏刻蚀和外延工艺， 而直接通过 离子注入的方法在在第一掺杂阱 201和第二掺杂阱 202内分别形成高浓度的离 子掺杂区， 以形成源极 209和漏极 210， 如图 11所示。
图 5至图 11为本发明的采用多晶硅控制栅结构的平面沟道的半导体器件的 实施例的制造工艺流程图， 其中是先形成多晶硅控制栅 207， 再形成源极 209和 漏极 210。 如果采用金属控制栅结构， 为避免金属控制栅在源极 209和漏极 210 的高温退火中被损伤， 需要先形成源极 209和漏极 210再形成金属控制栅。 制 备金属控制栅时， 可以在图 10或者图 11的基础上， 将多晶硅控制栅 207作为 牺牲层材料， 在刻蚀掉多晶硅控制栅 207后， 使得金属栅材料占据原来的多晶 硅控制栅 207的位置， 从而形成金属控制栅， 其主要工艺流程如下：
在图 10所示的结构表面淀积第一层层间介质材料 211， 并通过化学机械抛 光技术对所形成的第一层层间介质材料 211进行抛光直至露出多晶硅控制栅 207 的表面， 如图 12所示。 然后刻蚀掉多晶硅控制栅 207， 并继续刻蚀掉暴露的第 二层层绝缘薄膜 206， 如图 13所示。
接下来， 在所形成结构的表面淀积第四层绝缘薄膜 212和金属栅材料， 之 后进行化学机械抛光使得抛光后的金属栅材料占据原来的多晶硅控制栅 207 的 位置， 以形成金属控制栅 213， 如图 14所示。 第四层绝缘薄膜 212可以为二氧 化硅、 氮化硅、 氮氧化硅、 具有高介电常数的绝缘材料或者为它们之间的叠层 中的任意一种。 可选的， 在刻蚀掉多晶硅控制栅 207后， 可以保留第二层绝缘 薄膜 206， 然后淀积形成第四层绝缘薄膜 212和金属栅材料， 或者， 也可以保留 第二层绝缘薄膜 206， 并在第二层绝缘薄膜 206上直接淀积金属栅材料。
最后， 如图 15所示， 覆盖所形成的结构淀积第二层层间介质材料 214， 然 后在所形成的第二层层间介质材料 214和第一层层间介质材料 211 中形成接触 孔， 并形成源电极 215、漏电极 217和栅电极 216， 该工艺为业界所熟知的工艺。
图 16为利用本发明的一种平面沟道的半导体器件的制造方法制造的双存储 单元的平面沟道的半导体器件结构的一个实施例， 它是由两个如图 15所示的平 面沟道的半导体器件构成， 且该两个平面沟道的半导体器件成对称的结构。 如 图 16所示， 该两个平面沟道的半导体器件共用了第二掺杂阱 202、 漏极 210和 漏电极 217， 双存储单元的平面沟道的半导体器件结构可以存储两位的数据。 图 17为利用本发明的一种平面沟道的半导体器件的制造方法制造的由多个 如图 15所示的平面沟道的半导体器件组成的存储单元阵列的电路示意图。 如图 17所示， 在多条源线 SL 603a-603b中， 其中任意一条与多个半导体器件的源极 相连。 在多条字线 WL 601a-601d中， 其中任意一条与多个半导体器件中的控制 栅相连接。 在多条位线 BL 602a-602d中， 其中任意一条与多个半导体器件的漏 极相连。多条位线 BL 602a-602d中的任何一条可与多条字线 WL 601a-601d中的 任何一条的组合可以选中一个独立的半导体栅器件。字线 WL 601a-601d可以由 字线地址解码器 901选中，位线 BL 602a-602d可以由一个位线选择控制模块 902 选中， 位线选择控制模块 902 —般包括一个地址解码器、 一个多路选择器和一 组感应放大器。 同时， 源线 SL 603a和 603b可以公共源线或一个源线选择控制 模块连接。
本发明尚有多种实施方式， 凡采用等同变换或者等效变换而形成的所有技 术方案， 均落在本发明的保护范围之内。

Claims

权 利 要 求
1 . 一种平面沟道的半导体器件， 包括：
在第一种掺杂类型的半导体衬底上形成的第一层绝缘薄膜和第一种掺杂类型的浮栅； 在所述第一层绝缘薄膜中形成的一个浮栅开口， 在所述半导体衬底内且位于所述浮栅开 口之下形成的第二种掺杂类型的第二掺杂阱；
在所述半导体衬底内形成的第二种掺杂类型的源极和漏极， 所述漏极位于所述第二掺杂 阱内；
通过所述浮栅开口在所述浮栅和漏极之间形成的一个 p-n结二极管；
在所述浮栅的上表面及两侧形成的第二层绝缘薄膜和控制栅， 所述 p-n结二极管、 第二 层绝缘薄膜和控制栅形成一个以所述控制栅为栅极的栅控 p-n结二极管。
2. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 所述源极与第二掺 杂阱之间的半导体衬底部分形成电流沟道区。
3. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 还包括在形成所述 第二掺杂阱的同时， 在所述源极的一侧形成的第一掺杂阱， 所述源极形成于所述第一掺杂阱 内， 所述第一掺杂阱与第二掺杂阱之间的半导体衬底部分形成电流沟道区。
4. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 所述 p-n结二极管 的阳极与所述浮栅相连接， 所述 p-n结二极管的阴极与所述漏极相连接； 或者， 所述 p-n结 二极管的阴极与所述浮栅相连接， 所述 p-n结二极管的阳极与所述漏极相连接。
5. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 所述第一层绝缘薄 膜和第二层绝缘薄膜分别为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数值的绝缘材料或 者它们之间的叠层中的任意一种， 其物理厚度范围为 1纳米 -20纳米。
6.根据权利要求 1所述的一种平面沟道的半导体器件，其特征在于：所述浮栅为多晶硅、 钨或者氮化钛中的任意一种。
7. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 所述控制栅为多晶 硅控制栅或者金属控制栅中的任意一种。
8. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 所述第一种掺杂类 型为 n型， 所述第二种掺杂类型为 p型； 或者， 所述第一种掺杂类型为 p型， 所述第二种掺 杂类型为 n型。
9. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 所述源极和漏极为 分别在所述半导体衬底内形成的高掺杂浓度的掺杂区。
10. 根据权利要求 1所述的一种平面沟道的半导体器件， 其特征在于： 所述源极和漏极 分别为锗化硅或者碳化硅中的任意一种。
11. 如权利要求 1所述的一种平面沟道的半导体器件的制造方法， 包括：
在第一种掺杂类型的半导体衬底内形成第二种掺杂类型的第二掺杂阱；
在所述半导体衬底的表面形成第一层绝缘薄膜， 并刻蚀所述第一层绝缘薄膜形成一个浮 栅开口， 所述浮栅开口位于所述第二掺杂阱之上；
在已形成的结构的表面淀积第一种掺杂类型的第一层导电薄膜；
刻蚀所述第一层导电薄膜形成浮栅， 所述浮栅覆盖所述浮栅开口；
在已形成的结构的表面淀积第二层绝缘薄膜；
在所述第二层绝缘薄膜之上淀积一层掺杂的多晶硅；
刻蚀所述掺杂的多晶硅， 刻蚀后剩余的掺杂的多晶硅形成多晶硅控制栅， 所述多晶硅控 制栅在所述浮栅的上表面及两侧覆盖并包围所述浮栅；
在所述多晶硅控制栅的两侧形成栅极侧墙；
在所述多晶硅控制栅的两侧的半导体衬底内形成自对准的源极和漏极。
12. 根据权利要求 11所述的一种平面沟道的半导体器件的制造方法， 其特征在于： 所述 源极和漏极是通过离子注入工艺在半导体衬底内形成高掺杂浓度的源极和漏极。
13. 根据权利要求 11所述的一种平面沟道的半导体器件的制造方法， 其特征在于： 所述 源极和漏极是先在多晶硅控制栅的两侧对半导体衬底进行源、 漏刻蚀， 再通过外延工艺生长 碳化硅或者锗化硅材料的源极和漏极。
14.根据权利要求 11所述的一种平面沟道的半导体器件的制造方法，其特征在于还包括: 覆盖所形成的结构淀积一层层间介质材料， 之后进行抛光直至露出所述多晶硅控制栅； 刻蚀掉所述多晶硅控制栅；
在所形成结构的表面淀积金属栅材料；
进行抛光使得抛光后的金属栅材料占据原来的多晶硅控制栅的位置， 从而形成金属控制
15. 根据权利要求 14所述的一种平面沟道的半导体器件的制造方法， 其特征在于： 刻蚀 掉所述多晶硅控制栅后， 保留或者刻蚀掉第二层绝缘薄膜， 然后淀积第四层绝缘薄膜和金属 栅材料。
16. 根据权利要求 14所述的一种平面沟道的半导体器件的制造方法， 其特征在于： 所述 第四层绝缘薄膜为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数值的绝缘材料或者它们之 间的叠层中的任意一种， 其物理厚度范围为 1纳米 -20纳米。
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