WO2015032195A1 - 一种半浮栅器件的制造方法 - Google Patents

一种半浮栅器件的制造方法 Download PDF

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Publication number
WO2015032195A1
WO2015032195A1 PCT/CN2014/074531 CN2014074531W WO2015032195A1 WO 2015032195 A1 WO2015032195 A1 WO 2015032195A1 CN 2014074531 W CN2014074531 W CN 2014074531W WO 2015032195 A1 WO2015032195 A1 WO 2015032195A1
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Prior art keywords
layer
insulating film
polysilicon
floating gate
semi
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PCT/CN2014/074531
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English (en)
French (fr)
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刘伟
刘磊
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苏州东微半导体有限公司
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Priority to US14/432,558 priority Critical patent/US9472561B2/en
Publication of WO2015032195A1 publication Critical patent/WO2015032195A1/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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Definitions

  • the present invention relates to the field of semiconductor memory technology, and relates to a method for fabricating a dynamic random access memory, and more particularly to a method for fabricating a semi-floating gate device. Background technique
  • SRAM static random access memory
  • DRAM standard dynamic random access memory
  • the U-shaped channel semiconductor device has a cross-sectional structure along the length of the current channel as shown in FIG. 1 and is included in the semiconductor substrate 200.
  • the source region 201, the drain region 202, and the U-shaped channel region 401 formed therein are formed with a first insulating film 203 and a charge storage node and a notch as a charge storage node over the drain region 202 and the U-shaped channel region 401.
  • Floating gate 205 Floating gate 205.
  • a p-n junction diode is formed between the floating gate 205 and the drain region 202 through the floating gate opening region 204.
  • the cover source region 201, the floating gate 205, and the pn junction diode structure are formed with a second insulating film 206 and a control gate 207.
  • the control gate 207 is formed in the U-shaped groove along the length of the device channel.
  • the top of the source region 201 is isolated from the top of the floating gate 205.
  • the U-shaped channel semiconductor device manufacturing method comprises the steps of: removing the hard mask layer 301 after forming the U-shaped recess, and forming a first layer of insulation over the U-shaped recess and the surface of the semiconductor substrate.
  • a film 203, and then a floating gate opening region 204 is formed in the first insulating film 203 on the top of the U-shaped groove and adjacent to the drain region 202 side wall, as shown in FIG. 2; then the floating gate 205 is formed.
  • a floating gate opening region 204 is formed in the first insulating film 203 on the sidewall on the side of the U-shaped groove near the drain region 202, which is complicated in process, difficult to manufacture, and difficult to control. The quality of the finished product of the semiconductor device is guaranteed.
  • the object of the present invention is to overcome the deficiencies of the prior art and to provide a method for fabricating a semi-floating gate device.
  • the invention can simplify the manufacturing process of the existing semi-floating gate device, reduce the manufacturing difficulty of the semi-floating gate device, and improve the manufacturing process.
  • Half float The yield of the gate device.
  • a method for fabricating a semi-floating gate device comprising the steps of forming a u-shaped groove process, and the third step of forming a source electrode, a drain electrode and a control gate; wherein, step 1 forms a U-shaped groove process
  • step 1 forms a U-shaped groove process
  • a first insulating film and a second insulating film are sequentially formed on the surface of the semiconductor substrate
  • the third is to position the channel region by a photolithography process and etch the second insulating film, the first insulating film and the semiconductor substrate to form a U-shaped recess having a bottom lower than the bottom of the doped well, the U-shaped concave a trench divides the doped well into a drain region and a source region;
  • the method is characterized in that: in the step 1 forming the U-shaped groove process and the step 3 forming the source electrode, the drain electrode and the control gate process, the process of forming the floating gate and the floating gate opening region in the second step is further included, wherein the specific process is:
  • a third insulating film is grown on the surface of the U-shaped groove in the first step
  • the second is to cover the U-shaped groove to deposit the first layer of polysilicon until the first layer of polysilicon fills the U-shaped groove;
  • the first layer of polysilicon is etched back, and the top of the remaining first layer of polysilicon is located between the upper surface of the second insulating film and the bottom of the doped well;
  • the second insulating film, the first insulating film and the exposed third insulating film are etched away; the fifth is to cover the structure formed by the etching process to deposit a second layer of polysilicon, the second layer of polysilicon and The first layer of polysilicon constitutes a polysilicon layer;
  • a layer of photoresist is deposited, and a pattern is formed by a photolithography process, and then the polysilicon layer is etched along the photoresist pattern to form a floating gate and a floating gate opening region, and the etching depth is at the bottom of the drain region and the source region.
  • the specific process of forming the source electrode, the drain electrode and the control gate in the third step of the present invention is as follows: First, a fourth insulating film is formed on the surface of the device having the structure formed in the second step, and the fourth insulating film is deposited to cover the deposition. Third layer of polysilicon;
  • the third is to etch the fifth insulating film and the third polysilicon formed by a photolithography process and an etching process, and form a polysilicon control gate sacrificial material by the third polysilicon remaining after the etching;
  • a device covering the formed structure is deposited to form a sixth insulating film, and the formed sixth insulating film is etched back to form a gate spacer;
  • Fifth, source and drain etching and epitaxial processes are performed on both sides of the formed gate sidewall to form a contact region of the source region and the drain region;
  • a device covering the formed structure is deposited to deposit a first interlayer dielectric material, and polishing is performed until the exposed polysilicon control gate sacrificial material is exposed;
  • the fourth insulating film is etched away, and then the seventh insulating film and the metal control gate are formed.
  • the fourth insulating film is directly covered to form a metal control gate.
  • a high concentration doped region is formed in the source region and the drain region by ion implantation, and a contact region of the source region and the drain region is formed.
  • the material of the first insulating film of the present invention is silicon oxide, and the material of the second insulating film is silicon nitride.
  • the materials of the fifth insulating film and the sixth insulating film of the present invention are respectively silicon oxide or silicon nitride.
  • the materials of the third insulating film, the fourth insulating film and the seventh insulating film of the present invention are respectively silicon dioxide, silicon nitride, an insulating material having a high dielectric constant or a laminate therebetween.
  • the implementation principle of the present invention is: The manufacturing method of the present invention is based on the formation of the original hard mask layer after the U-shaped recess of the existing semi-floating gate device is formed, firstly by depositing the first layer of polysilicon and using a etch back process To protect the gate dielectric layer, and then remove the hard mask layer; then deposit a second layer of polysilicon, and then etch the polysilicon, then form the floating gate of the device from the remaining second layer of polysilicon and the first layer of polysilicon, and The floating gate opening region is automatically formed by the portion of the floating gate that is in contact with the semiconductor substrate.
  • the floating gate of the present invention is formed by two deposition processes, one photolithography process, and two etching processes. Although the fabrication process of the floating gate is increased, the photolithography process and engraving of separately forming the floating gate opening region are omitted.
  • the etching process optimizes the manufacturing process of the U-channel semi-floating gate device as a whole, thereby reducing the manufacturing difficulty and production cost of the U-channel semi-floating gate device.
  • the floating gate opening region of the present invention is self-aligned during the formation of the floating gate, so that the u-shaped channel semi-floating gate
  • the manufacturing process of the device is simple and reliable, and has strong controllability, which can improve the yield of the U-channel semi-floating gate device.
  • FIG. 1 is a schematic cross-sectional view of a U-channel semi-floating gate device described in Chinese Patent No. 201310119651.8
  • FIG. 2 to FIG. 3 are schematic diagrams showing a manufacturing process of a floating gate of a U-channel semi-floating gate device described in Chinese Patent No. 201310119651.8;
  • FIG. 18 are schematic diagrams showing a process flow of manufacturing a semi-floating gate device according to the present invention.
  • Figure 19 is a cross-sectional view showing a semi-floating gate device for fabricating dual memory cells of the present invention.
  • Figure 20 is a schematic illustration of a circuit for fabricating a memory cell array comprised of a plurality of semi-floating gate devices in accordance with the present invention. detailed description
  • the invention provides a method for manufacturing a semi-floating gate device, which comprises forming a U-shaped groove through step one, forming a floating gate and a floating gate opening region in step two, and forming a source electrode, a drain electrode and a control gate in step three, and further A U-shaped channel half floating gate device is obtained.
  • a specific embodiment of a method for fabricating a semi-floating gate device is further disclosed in accordance with the technical solution of the present invention and in conjunction with the accompanying drawings. The process is as follows:
  • a doped well 301 having a second doping type is formed in a semiconductor device 300 having a first doping type in which a shallow trench isolation structure has been formed; a semiconductor substrate 300
  • the material is silicon or silicon-on-insulator; the first doping type is n-type, the second doping type is p-type, or the first doping type is p-type, and the second doping type is n-type.
  • a first insulating film 302 and a second insulating film 303 are sequentially grown on the surface of the semiconductor substrate 300, and then the position of the channel region of the device is determined by a photolithography process, and the second insulating layer is etched by using the photoresist as a mask.
  • the film 303 and the first insulating film 302 are stopped on the surface of the semiconductor substrate 300, and the photoresist is removed as shown in FIG. 5; wherein:
  • One layer of the insulating film 302 is made of silicon oxide
  • the second insulating film 303 is made of silicon nitride.
  • the silicon oxide film serves to improve the stress between the silicon nitride film 303 and the semiconductor substrate 300.
  • the semiconductor substrate 300 is further etched by using the silicon nitride film 303 and the silicon oxide film 302 as a mask, and a U-shaped groove is formed in the semiconductor substrate 300, and the bottom of the formed U-shaped groove is lower than the second doping.
  • the bottom of the doped well 301 of the heterotype separates the doped wells 301 having the second doping type as the source region 304 and the drain region 305 of the device, respectively, and the first doping at the bottom of the U-shaped groove
  • the hetero-type semiconductor substrate connects source region 304 and drain region 305 to form the channel region of the device, as shown in FIG.
  • a third insulating film 306 is grown on the surface of the formed U-shaped groove, and the third insulating film 306 is made of silicon dioxide, silicon nitride, silicon oxynitride, an insulating material having a high dielectric constant or a laminate between them; then covering the formed structure to deposit a first layer of polysilicon 307 having a first doping type, the deposited first layer of polysilicon 307 should fill the formed U-shaped groove, and then The first layer of polysilicon 307 is etched back, and the top of the remaining first layer of polysilicon 307 after etching should be located under the upper surface of the second insulating film 303 and be doped with the second doping type.
  • FIG. 7a is the top of the etched first layer of polysilicon 307 under the second insulating film 303.
  • FIG. 7b is the top of the etched first polysilicon 307 on the upper surface of the second insulating film 303 Under and located Another insulating layer over the lower surface of the film of Example 303.
  • FIG. 8a corresponds to the structure formed after FIG. 7a
  • FIG. 8b corresponds to FIG. 7b.
  • a second layer of polysilicon having a first doping type is continuously deposited on the surface of the device having the above structure, and the second layer of polysilicon having the first doping type and the first layer of polysilicon 307 are combined to form a first doping.
  • Type polysilicon layer 308, polysilicon layer 308 is in contact with source region 304 and drain region 305, as shown in FIG. 9, wherein: polysilicon layer 308 in FIG. 9a is on top of the U-shaped recess and on the surface of semiconductor substrate 300.
  • the source region 304 and the drain region 305 are simultaneously in contact, and the polysilicon layer 308 in FIG. 9b is simultaneously in contact with the source region 304 and the drain region 305 only on the surface of the semiconductor substrate 300.
  • the method for fabricating the semi-floating gate device of the present invention will be further described below by taking a device having the structure shown in FIG. 9a as an example.
  • a layer of photoresist 401 is deposited over the polysilicon layer 308, and then patterned by a photolithography process, as shown in FIG.
  • the remaining photoresist is over the U-shaped recess and covers a portion of the drain region on one side of the drain region 305, while the source region 304 is not covered on one side of the source region 304 and will be located in the U-shaped recess.
  • a portion of the polysilicon layer 308 on the side of the source region 304 is exposed.
  • the polysilicon layer 308 is etched by using the photoresist 401 as a mask. After the semiconductor substrate 300 is exposed, the semiconductor substrate 300 is further etched. The etching depth of the semiconductor substrate 300 should be higher than that of the source region 304 and the drain region. The bottom of the 305 is not higher than the top of the third insulating film 306.
  • the etching depth of the semiconductor substrate 300 in this embodiment is equal to the height of the third insulating film 306;
  • the doped type polysilicon layer 308 forms the floating gate 308 of the device; since the photoresist does not cover the source region 304 and exposes a portion of the polysilicon layer 308 located in the U-shaped recess near the source region 304, the polysilicon layer is exposed
  • the floating gate 308 is formed with a notch on the side close to the source region 304, and is isolated from the source region 304 by the third insulating film 306; and since the photoresist is near the drain A layer 305 of the region 305 covers a portion of the drain region 305 such that after etching the polysilicon layer 308 and the semiconductor substrate 300, the floating gate 308 and the unetched semiconductor substrate are on the side near the drain region 305.
  • the contact points, and a pn junction is formed in contact with the drain region 305, as shown in FIG.
  • a fourth insulating film 309 is formed on the surface of the formed structure, and then the fourth insulating film 309 is formed to form a third layer of polysilicon 310, and is deposited over the third layer of polysilicon 310.
  • a fifth insulating film 311 is formed, and then the formed fifth insulating film 311 and the third polysilicon 310 are etched by a photolithography process and an etching process, and the remaining third polysilicon 310 after etching forms a polysilicon control of the device.
  • the gate sacrificial material is as shown in FIG.
  • the floating gate 308 since the floating gate 308 is in partial contact with the semiconductor substrate 300 during the formation of the floating gate 308, and forms a pn junction contact with the drain region 305, that is, the floating gate 308 covers and protects the portion.
  • the drain region 305 after forming the fourth insulating film 309, automatically forms an opening between the fourth insulating film 309 and the third insulating film 306 (i.e., the portion of the floating gate 308 covering the drain region 305). That is, the floating gate opening region between the floating gate 308 and the drain region 305; the fourth insulating film 309 is made of silicon dioxide, silicon nitride, silicon oxynitride, and an insulating material having a high dielectric constant.
  • the material of the fifth insulating film 311 is made of silicon oxide or silicon nitride.
  • the formed structure is deposited to form a sixth insulating film 312, and the formed sixth insulating film 312 is etched back to form a gate spacer, and then the exposed fourth insulating film 309 is etched away.
  • the source region 304 and the drain region 305 are exposed as shown in FIG. 13; the sixth insulating film 312 is made of silicon oxide or silicon nitride.
  • a portion of the exposed source region 304 and drain region 305 are etched away, and silicon or silicon carbide material is epitaxially grown in the source region 304 and the drain region 305 after etching.
  • the fourth insulating film 309 is not etched, and the polysilicon control is etched away.
  • the seventh insulating film 316 and the metal control gate 317 are directly formed; or the fourth insulating film 309 is not etched, and the fourth insulating film 309 is directly covered to form the metal control gate 317; the seventh insulating film
  • the material of 316 is silicon dioxide, silicon nitride, silicon oxynitride, an insulating material having a high dielectric constant, or a laminate therebetween.
  • a second interlayer dielectric material 318 is deposited, and then a contact hole is formed in the formed second interlayer dielectric material 318 and the first interlayer dielectric material 315, and a source electrode 319 is formed.
  • the drain electrode 320 and the gate electrode (not shown in FIG. 18).
  • a gate dielectric layer 306 formed over the surface of the U-shaped recess, the top of the gate dielectric layer 306 being located above the bottom of the source region 304 and the drain region 305 and not higher than the surface of the semiconductor substrate 300.
  • a floating gate 308 having a first doping type as a charge storage node is formed in the U-shaped recess to cover the gate dielectric layer 306.
  • the floating gate 308 has a notch on the side close to the source region 304, and the bottom of the recess
  • the bottom of the source region 304 and the drain region 305 should be higher than the top of the gate dielectric layer 306, and the side of the floating gate 308 near the drain region 305 extends beyond the gate dielectric layer 306 and over the surface of the semiconductor substrate 300.
  • Contact with the drain region 305 forms a pn junction contact.
  • the surfaces of the source region 304 and the drain region 305 are lower than the surface of the semiconductor substrate 300 and are flush with the bottom of the recess of the floating gate 308 such that the gate dielectric layer 306 connects the source region 304 and the floating gate 308. Isolating; covering the source region 304, the floating dielectric layer 316 formed by the floating gate 308 and the drain region 305, overlying the insulating dielectric layer 316 and surrounding the metal gate 317 formed by the floating gate 308; the gate dielectric layer 306 and the insulating dielectric layer 316 has a floating gate opening area through The floating gate opening region, the floating gate 308 is connected to the drain region 305; in FIG.
  • the floating gate opening region is located at the top of the U-shaped groove and the surface of the semiconductor substrate 300 near the U-shaped groove side in the drain region 305;
  • the height of the gate dielectric layer 306 may be level with the surface of the semiconductor substrate 300 such that the floating gate opening region is located only on the surface of the semiconductor substrate 300 in the drain region 305 near the U-shaped groove side.
  • a gate spacer 312 formed on both sides of the metal control gate 317; a source region contact 313 and a drain region contact 314 are formed on both sides of the gate spacer 312, in the source region 304 and the drain region 305;
  • the interlayer dielectric material insulating dielectric layer material 315 and insulating dielectric material 318) and the contact holes formed in the interlayer dielectric material and the source electrode 319, the drain electrode 320, and the gate electrode (not shown in FIG. i8).
  • FIG. 19 is an embodiment of a structure of a semi-floating gate device of a dual memory cell fabricated by the present invention, which is composed of two semi-floating gate devices as shown in FIG. 18, wherein the two semi-floating gate devices have a symmetrical structure.
  • the two half floating gate devices share a drain region 305, a drain region contact 314, and a drain region electrode 320.
  • the dual floating cell device structure of the dual memory cell can store two bits of data.
  • Figure 20 is a circuit diagram showing the fabrication of a memory cell array composed of a plurality of semi-floating gate devices as shown in Figure 18 of the present invention.
  • any one of the plurality of source lines SL 603a-603b is connected to the sources of the plurality of half floating gate devices; among the plurality of word lines WL 601a-601d, any one of the plurality of word lines WLa 601a-601d
  • the control gates in the floating gate device are connected; any one of the plurality of bit lines BL 602a-602d is connected to the drains of the plurality of half floating gate devices: any one of the plurality of bit lines BL 602a-602d may be A combination of any of the word lines WL 601a-601d may be selected from a separate semi-floating gate device; word lines WL 601a-601d may be selected by word line address decoder 901, and bit lines BL 602a-602d may be selected by a bit line
  • the control module 902 selects, the

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Abstract

一种半浮栅器件的制造方法，主要包括浮栅和浮栅开口区的制造方法，其具体工艺过程为：形成U形凹槽后先保留硬掩膜层，在形成的U形凹槽的表面生长栅介质层，再通过淀积第一层多晶硅（307）并回刻来保护栅介质层，接着刻蚀掉外露的栅介质层和硬掩膜层，之后覆盖所形成的结构淀积第二层多晶硅，然后通过光刻工艺和刻蚀工艺对所形成的多晶硅层（308）进行刻蚀以形成浮栅，并自对准的形成浮栅开口区。上述制造方法能够简化现有半浮栅器件的制造工艺，降低U形沟道的半浮栅器件的制造难度，提高半浮栅器件的成品率。

Description

一种半浮栅器件的制造方法
技术领域
本发明属于半导体存储器技术领域， 涉及一种动态随机存储器的制造方法， 特别是 涉及一种半浮栅器件的制造方法。 背景技术
半导体存储器被广泛应用于各种电子产品之中。 不同应用领域对半导体存储器的构 造、 性能和密度有着不同的要求。 如静态随机存储器 （SRAM) 拥有很高的随机存取速 度和较低的集成密度， 而标准的动态随机存储器 （DRAM) 则具有很高的集成密度和中 等的随机存取速度。 当今随着半导体存储器市场需求的不断扩大， 动态随机存储器制造 工艺方法不断推陈出新， 许多制约动态随机存储器制造工艺的难题正在被不断攻克。
中国专利申请 201310119651.8提出了一种 U形沟道的半导体器件及其制造方法， 该 U形沟道的半导体器件沿电流沟道长度方向的剖面结构如图 1所示， 它包括在半导体衬 底 200内形成的源区 201、 漏区 202和 U形沟道区 401， 在漏区 202及 U形沟道区 401 之上形成有第一层绝缘薄膜 203和一个作为电荷存储节点并设有缺口的浮栅 205。通过浮 栅开口区 204在浮栅 205与漏区 202之间形成一个 p-n结二极管。 覆盖源区 201、 浮栅 205和所述的 p-n结二极管结构形成有第二层绝缘薄膜 206和控制栅 207， 在沿器件沟道 长度的方向上， 控制栅 207在所形成的 U形凹槽的顶部将源区 201与浮栅 205的顶部隔 离。
该 U形沟道的半导体器件的制造方法，它包括在形成 U形凹槽后，先将硬掩膜层 301 去掉， 再在 U形凹槽及半导体衬底的表面之上形成第一层绝缘薄膜 203， 然后在位于 U 形凹槽的顶部并靠近漏区 202—侧侧壁上的第一层绝缘薄膜 203中形成浮栅开口区 204， 如图 2所示； 之后再形成浮栅 205， 如图 3所示； 在位于 U形凹槽的顶部靠近漏区 202 一侧侧壁上的第一层绝缘薄膜 203中形成浮栅开口区域 204，该工艺过程复杂，制造难度 大， 难以控制和保证该半导体器件的成品质量。
发明内容
本发明的目的是为克服现有技术的不足而提出一种半浮栅器件的制造方法， 本发明 能够简化现有半浮栅器件的制造工艺， 降低半浮栅器件的制造难度， 同时能够提高半浮 栅器件的成品率。
根据本发明提出的一种半浮栅器件的制造方法， 它包括步骤一形成 u形凹槽工艺， 步骤三形成源电极、 漏电极和控制栅工艺； 其中， 步骤一形成 U形凹槽工艺的具体过程 依次为：
一是在第一种掺杂类型的半导体衬底内形成第二种掺杂类型的掺杂阱；
二是在半导体衬底表面依次形成第一层绝缘薄膜和第二层绝缘薄膜；
三是通过光刻工艺定位沟道区位置并刻蚀第二层绝缘薄膜、 第一层绝缘薄膜和半导 体衬底， 形成底部低于所述掺杂阱底部的 U形凹槽， 该 U形凹槽将所述掺杂阱分割为漏 区和源区；
其特征是： 在所述步骤一形成 U形凹槽工艺与步骤三形成源电极、 漏电极和控制栅 工艺之间还包括步骤二形成浮栅和浮栅开口区工艺， 其具体过程依次为：
一是在步骤一所述 U形凹槽的表面生长第三层绝缘薄膜；
二是覆盖 U形凹槽淀积第一层多晶硅直至第一层多晶硅填满 U形凹槽；
三是对第一层多晶硅进行回刻， 刻蚀后剩余的第一层多晶硅的顶部位于第二层绝缘 薄膜上表面与掺杂阱底部之间；
四是刻蚀掉第二层绝缘薄膜、 第一层绝缘薄膜以及外露的第三层绝缘薄膜； 五是覆盖经上述刻蚀处理所形成的结构淀积第二层多晶硅， 该第二层多晶硅与第一 层多晶硅组成多晶硅层；
六是淀积一层光刻胶， 并通过光刻工艺形成图形， 然后沿光刻胶图形刻蚀多晶硅层 以形成浮栅和浮栅开口区， 刻蚀深度在漏区和源区底部与第三层绝缘薄膜顶部之间。
本发明进一步的优选方案是：
本发明所述步骤三形成源电极、 漏电极和控制栅工艺的具体过程依次为： 一是在步骤二形成结构的器件表面上生成第四层绝缘薄膜， 覆盖所述第四层绝缘薄 膜淀积第三层多晶硅；
二是在所述第三层多晶硅之上淀积第五层绝缘薄膜；
三是通过光刻工艺和刻蚀工艺刻蚀所形成的第五层绝缘薄膜和第三层多晶硅， 并由 刻蚀后剩余的第三层多晶硅形成多晶硅控制栅牺牲材料；
四是覆盖上述所形成结构的器件淀积形成第六层绝缘薄膜， 并对所形成的第六层绝 缘薄膜进行回刻以形成栅极侧墙； 五是在所形成的栅极侧墙的两侧进行源、 漏刻蚀与外延工艺， 以形成源区和漏区的 接触区；
六是覆盖上述所形成结构的器件淀积第一层层间介质材料， 进行抛光直至外露多晶 硅控制栅牺牲材料；
七是刻蚀掉外露的多晶硅控制栅牺牲材料；
八是覆盖所述第四层绝缘薄膜， 淀积第七层绝缘薄膜和金属控制栅， 进行抛光使金 属控制栅占据所述多晶硅控制栅牺牲材料的位置；
九是覆盖上述所形成结构的器件淀积第二层层间介质材料， 并在所述第二层层间介 质材料和第一层层间介质材料中设置接触孔， 形成源电极、 漏电极和栅电极。
本发明所述步骤三中在刻蚀掉多晶硅控制栅牺牲材料后，先刻蚀掉第四层绝缘薄膜， 再形成第七层绝缘薄膜和金属控制栅。
本发明所述步骤三中在刻蚀掉多晶硅控制栅牺牲材料后， 直接覆盖第四层绝缘薄膜 形成金属控制栅。
本发明所述步骤三中在形成栅极侧墙后， 直接通过离子注入的方法， 在源区和漏区 内形成高浓度的掺杂区， 形成源区和漏区的接触区。
本发明所述第一层绝缘薄膜的材质为氧化硅、 第二层绝缘薄膜的材质为氮化硅。 本发明所述第五层绝缘薄膜和第六层绝缘薄膜的材质分别为氧化硅或氮化硅。
本发明所述第三层绝缘薄膜、 第四层绝缘薄膜和第七层绝缘薄膜的材质分别为二氧 化硅、 氮化硅、 具有高介电常数的绝缘材料或者为它们之间的叠层。 本发明的实现原理是： 本发明的制造方法是在现有半浮栅器件 U形凹槽形成后， 保 留原硬掩膜层的基础上， 首先通过淀积第一层多晶硅并采用回刻工艺来保护栅介质层， 接下来去掉硬掩膜层； 然后淀积第二层多晶硅， 接下来对多晶硅进行刻蚀后， 由剩余的 第二层多晶硅和第一层多晶硅形成器件的浮栅， 并由浮栅与半导体衬底相接触的部分自 动形成浮栅开口区。
本发明与现有技术相比其显著优点在于：
一是本发明的浮栅通过两次淀积工艺、 一次光刻工艺和两次刻蚀工艺形成， 虽然增 加了浮栅的制造工艺， 但省略了单独形成浮栅开口区的光刻工艺和刻蚀工艺， 从整体上 优化了 U形沟道半浮栅器件制造工艺过程， 从而降低了 U形沟道半浮栅器件的制造难度 和生产成本。
二是本发明的浮栅开口区是在浮栅形成过程中自对准形成， 使得 u形沟道半浮栅器 件的制造工艺简单可靠， 且可控性强， 能够提高 U形沟道半浮栅器件的成品率。
附图说明
图 1是中国专利 201310119651.8所述 U形沟道的半浮栅器件的剖面示意图； 图 2至图 3是中国专利 201310119651.8所述 U形沟道的半浮栅器件的浮栅制造工艺 流程示意图；
图 4 至图 18是本发明制造半浮栅器件的工艺流程示意图；
图 19是本发明制造双存储单元的半浮栅器件的剖面示意图；
图 20是本发明制造由多个半浮栅器件组成存储单元阵列的电路的示意图。 具体实施方式
为清楚地说明本发明的具体实施方式， 说明书附图中所列示图， 放大了本发明所述 的层和区域的厚度， 且所示图形大小并不代表实际尺寸； 附图是示意性的， 不应限定本 发明的范围。 说明书中所列实施例不应仅限于附图中所示区域的特定形状， 而是包括所 得到的形状如制造引起的偏差等、 再如刻蚀得到的曲线通常具有弯曲或圆润的特点， 但 在本发明实施例中均以矩形表示； 同时在下面的描述中， 所使用的术语衬底可理解为包 括正在工艺加工中的半导体晶片， 还包括在其上所制备的其它薄膜层。
下面结合附图和实施例对本发明的具体实施方式作进一步的详细说明。
本发明提出的一种半浮栅器件的制造方法， 它包括经步骤一形成 U形凹槽、 步骤二 形成浮栅和浮栅开口区以及步骤三形成源电极、 漏电极和控制栅， 进而制得 U形沟道半 浮栅器件。 现根据本发明的技术方案并结合附图进一步公开一种半浮栅器件制造方法的 具体实施例， 其工艺过程依次如下：
如图 4所示，在现有已形成浅沟槽隔离结构的具有第一种掺杂类型的半导体衬底 300 器件内形成具有第二种掺杂类型的掺杂阱 301 ; 半导体衬底 300的材质为硅或绝缘体上 硅； 第一种掺杂类型为 n型、 第二种掺杂类型为 p型， 或者第一种掺杂类型为 p型、 第 二种掺杂类型为 n型。
在半导体衬底 300的表面依次生长第一层绝缘薄膜 302和第二层绝缘薄膜 303，然后 通过光刻工艺确定器件沟道区的位置， 并以光刻胶为掩膜刻蚀第二层绝缘薄膜 303和第 一层绝缘薄膜 302， 停止在半导体衬底 300的表面， 去除光刻胶后如图 5所示； 其中： 第 一层绝缘薄膜 302的材质为氧化硅， 第二层绝缘薄膜 303的材质为氮化硅； 氧化硅薄膜 的作用在于改善氮化硅薄膜 303与半导体衬底 300之间的应力。
以氮化硅薄膜 303和氧化硅薄膜 302为掩膜继续刻蚀半导体衬底 300，在半导体衬底 300内形成 U形凹槽， 所形成的 U形凹槽的底部低于具有第二种掺杂类型的掺杂阱 301 的底部， 将具有第二种掺杂类型的掺杂阱 301分隔开， 分别作为器件的源区 304和漏区 305，且 U形凹槽底部的第一种掺杂类型半导体衬底将源区 304和漏区 305连接，成为该 器件的沟道区， 如图 6所示。
在所形成的 U形凹槽的表面生长第三层绝缘薄膜 306， 该第三层绝缘薄膜 306的材 质为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数的绝缘材料或者为它们之间的叠层； 接着覆盖所形成的结构淀积具有第一种掺杂类型的第一层多晶硅 307，该淀积的第一层多 晶硅 307应填满所形成的 U形凹槽， 然后， 对所形成的第一层多晶硅 307进行回刻， 刻 蚀后剩余的第一层多晶硅 307的顶部应位于第二层绝缘薄膜 303的上表面下且位于具有 第二种掺杂类型的掺杂阱 301的底部 （即源区 304和漏区 305的底部） 之上， 如图 7所 示， 其中， 图 7a为刻蚀后的第一层多晶硅 307的顶部位于第二层绝缘薄膜 303的下表面 之下且位于具有第二种掺杂类型的掺杂阱 301的底部之上的一个实施例， 图 7b为刻蚀后 的第一层多晶硅 307的顶部位于第二层绝缘薄膜 303的上表面之下且位于第二层绝缘薄 膜 303的下表面之上的另一个实施例。
刻蚀掉第二层绝缘薄膜 303、第一层绝缘薄膜 302以及暴露出的第三层绝缘薄膜 306， 如图 8所示， 其中： 图 8a对应图 7a后形成的结构， 图 8b对应图 7b后形成的结构； 在 图 7b中， 由于第三层绝缘薄膜 306被第一层多晶硅 307覆盖， 所以该工艺中不需要刻蚀 第三层绝缘薄膜 306。
在所形成上述结构的器件表面继续淀积具有第一种掺杂类型的第二层多晶硅， 具有 第一种掺杂类型的第二层多晶硅与第一层多晶硅 307共同构成具有第一种掺杂类型的多 晶硅层 308， 多晶硅层 308与源区 304和漏区 305相接触， 如图 9所示， 其中： 图 9a中 的多晶硅层 308在 U形凹槽的顶部以及半导体衬底 300的表面与源区 304和漏区 305同 时接触， 图 9b中的多晶硅层 308只在半导体衬底 300的表面与源区 304和漏区 305同时 接触。
下面以图 9a所示结构的器件为例， 进一步说明本发明的半浮栅器件的制造方法。 在多晶硅层 308之上淀积一层光刻胶 401， 然后通过光刻工艺形成图形， 如图 10所 示； 剩余的光刻胶位于 U形凹槽上方， 且在漏区 305的一侧覆盖了部分漏区， 而在源区 304的一侧未覆盖源区 304且将位于 U形凹槽内靠近源区 304—侧的部分多晶硅层 308 暴露出来。
以光刻胶 401为掩膜刻蚀多晶硅层 308，在露出半导体衬底 300后，继续对半导体衬 底 300进行刻蚀， 对半导体衬底 300刻蚀的深度应高于源区 304和漏区 305的底部并不 高于第三层绝缘薄膜 306的顶部， 本实施例中所述半导体衬底 300刻蚀的深度与第三层 绝缘薄膜 306的高度相平； 刻蚀后剩余的具有第一种掺杂类型的多晶硅层 308形成器件 的浮栅 308; 由于光刻胶未覆盖源区 304且将位于 U形凹槽内靠近源区 304—侧的部分 多晶硅层 308暴露出来， 因此在对多晶硅层 308和半导体衬底 300进行刻蚀时会使得浮 栅 308在靠近源区 304的一侧形成一个缺口， 并通过第三层绝缘薄膜 306与源区 304隔 离； 且由于光刻胶在靠近漏区 305 的一层覆盖了部分漏区 305， 使得在对多晶硅层 308 和半导体衬底 300进行刻蚀时后， 浮栅 308在靠近漏区 305的一侧会与未被刻蚀的半导 体衬底 300部分接触， 并与漏区 305形成 pn结接触， 如图 11所示。
剥除光刻胶 401后，在所形成结构的表面形成第四层绝缘薄膜 309，接着覆盖所形成 的第四层绝缘薄膜 309形成第三层多晶硅 310，并在第三层多晶硅 310之上淀积第五层绝 缘薄膜 311，然后通过光刻工艺和刻蚀工艺刻蚀所形成的第五层绝缘薄膜 311和第三层多 晶硅 310， 刻蚀后剩余的第三层多晶硅 310形成器件的多晶硅控制栅牺牲材料， 如图 12 所示； 由于在浮栅 308的形成过程中， 浮栅 308与半导体衬底 300部分接触， 并与漏区 305形成 pn结接触， 即浮栅 308覆盖并保护了部分漏区 305， 因此在形成第四层绝缘薄 膜 309后会在第四层绝缘薄膜 309与第三层绝缘薄膜 306之间（即浮栅 308覆盖漏区 305 的部分） 自动形成一个开口， 该开口即为浮栅 308与漏区 305之间的浮栅开口区； 第四 层绝缘薄膜 309的材质为二氧化硅、 氮化硅、 氮氧化硅、 具有高介电常数的绝缘材料或 者为它们之间的叠层， 第五层绝缘薄膜 311的材质为氧化硅或氮化硅。
覆盖所形成的结构淀积形成第六层绝缘薄膜 312，并对所形成的第六层绝缘薄膜 312 进行回刻以形成栅极侧墙， 然后刻蚀掉暴露出的第四层绝缘薄膜 309以露出源区 304和 漏区 305， 如图 13所示； 第六层绝缘薄膜 312的材质为氧化硅或氮化硅。
在所形成的栅极侧墙的两侧，刻蚀掉暴露出的部分源区 304和漏区 305，并在刻蚀后 的源区 304和漏区 305部分外延锗化硅或碳化硅材料以形成源区接触区 313和漏区接触 区 314， 如图 14a所示； 也可选择在栅极侧墙的两侧， 不经过刻蚀工艺和外延工艺， 而直 接通过离子注入的方法在源区 304和漏区 305内形成高浓度的离子掺杂区以形成源区接 触区 313和漏区接触区 314， 如图 14b所示。
覆盖如图 14b所示结构的器件，淀积第一层层间介质材料 315，并通过化学机械抛光 技术对所形成的第一层层间介质材料 315进行抛光直至露出多晶硅控制栅牺牲材料 310， 如图 15所示； 然后刻蚀掉暴露出的多晶硅控制栅牺牲材料 310和第四层绝缘薄膜 309， 如图 16所示； 然后在浮栅 308之上形成第七层绝缘薄膜 316和金属控制栅 317， 之后进 行抛光使金属控制栅 317占据原来的多晶硅控制栅牺牲材料 310的位置， 如图 17所示； 也可选择不刻蚀掉第四层绝缘薄膜 309，而在刻蚀掉多晶硅控制栅牺牲材料 310后直接形 成第七层绝缘薄膜 316和金属控制栅 317; 或者不刻蚀掉第四层绝缘薄膜 309， 直接覆盖 第四层绝缘薄膜 309形成金属控制栅 317;第七层绝缘薄膜 316的材质为二氧化硅、氮化 硅、 氮氧化硅、 具有高介电常数的绝缘材料或者为它们之间的叠层。
如图 18所示， 淀积第二层层间介质材料 318， 然后在所形成的第二层层间介质材料 318和第一层层间介质材料中 315中形成接触孔并形成源电极 319、漏电极 320和栅电极 (图 18中未示出）。
以下结合附图， 进一步说明本发明制造半浮栅器件的实施例。
如图 18所示， 一个具有第一种掺杂类型的半导体衬底 300， 在半导体衬底 300内形 成的具有第二种掺杂类型的源区 304和漏区 305; 凹陷在半导体衬底 300内且介于源区 304与漏区 305之间形成的 U形凹槽， U形凹槽底部的第一种掺杂类型半导体衬底将源 区 304和漏区 305连结， 成为器件的沟道区； 覆盖 U形凹槽的表面形成的栅介质层 306， 栅介质层 306的顶部应位于源区 304和漏区 305的底部之上且不高于半导体衬底 300的 表面。
在 U形凹槽内覆盖栅介质层 306形成的一个作为电荷存储节点的具有第一种掺杂类 型的浮栅 308， 浮栅 308在靠近源区 304的一侧存在一缺口， 该缺口的底部应高于源区 304和漏区 305的底部并不高于栅介质层 306的顶部，浮栅 308靠近漏区 305的一侧超出 栅介质层 306并延伸至半导体衬底 300的表面之上并与漏区 305接触形成 pn结接触。
在浮栅 308的两侧， 源区 304和漏区 305的表面低于半导体衬底 300的表面并与浮 栅 308的缺口的底部相平，使得栅介质层 306将源区 304与浮栅 308隔离；覆盖源区 304、 浮栅 308与漏区 305形成的绝缘介质层 316，在绝缘介质层 316之上覆盖并包围浮栅 308 形成的金属控制栅 317 ;在栅介质层 306与绝缘介质层 316存在一个浮栅开口区域，通过 该浮栅开口区， 浮栅 308与漏区 305相连； 图 18中， 浮栅开口区域位于 U形凹槽的顶部 以及在漏区 305内靠近 U形凹槽一侧半导体衬底 300的表面； 也可选择栅介质层 306的 高度与半导体衬底 300表面相平， 使得浮栅开口区域仅位于在漏区 305内靠近 U形凹槽 一侧的半导体衬底 300的表面。
在金属控制栅 317的两侧形成的栅极侧墙 312; 在栅极侧墙 312的两侧、 源区 304 和漏区 305内形成源区接触 313和漏区接触 314;用于隔离器件形成的层间介质材料（绝 缘介质层材料 315和绝缘介质材料 318 )以及在层间介质材料中形成的接触孔以及源电极 319、 漏电极 320和栅电极 （图 i8中未示出）。
图 19为本发明制造的双存储单元的半浮栅器件结构的实施例， 它是由两个如图 18 所示的半浮栅器件构成， 其中该两个半浮栅器件呈对称的结构， 该两个半浮栅器件共用 了漏区 305、漏区接触 314和漏区电极 320， 双存储单元的半浮栅器件结构可以存储两位 的数据。
图 20为本发明制造由多个如图 18所示的半浮栅器件组成的存储单元阵列的电路示 意图。如图 20所示， 在多条源线 SL 603a-603b中， 其中任意一条与多个半浮栅器件的源 极相连；在多条字线 WL 601a-601d中，其中任意一条与多个半浮栅器件中的控制栅相连； 在多条位线 BL 602a-602d中，其中任意一条与多个半浮栅器件的漏极相连：多条位线 BL 602a-602d中的任何一条可与多条字线 WL 601a-601d中的任何一条的组合， 可选中一个 独立的半浮栅器件；字线 WL 601a-601d可由字线地址解码器 901选中，位线 BL 602a-602d 可由一个位线选择控制模块 902选中，位线选择控制模块 902—般包括一个地址解码器、 一个多路选择器和一组感应放大器； 同时， 源线 SL 603a和 603b可以公共源线或一个源 线选择控制模块连接。
本发明中凡未作说明的技术手段均为本领域技术人员所公知的现有技术。
以上结合附图和实施例所述的具体实施方式是对本发明提出的一种半浮栅器件的制 造方法技术思想的具体支持， 不能以此限定本发明的保护范围， 凡是按照本发明提出的 技术思想， 在本技术方案基础上所做的任何等同变化或等效的改动， 均仍属于本发明技 术方案保护的范围。

Claims

权利要求书
1、 一种半浮栅器件的制造方法， 它包括步骤一形成 u形凹槽工艺， 步骤三形成源电 极、 漏电极和控制栅工艺； 其中， 步骤一形成 U形凹槽工艺的具体过程依次为：
一是在第一种掺杂类型的半导体衬底内形成第二种掺杂类型的掺杂阱；
二是在半导体衬底表面依次形成第一层绝缘薄膜和第二层绝缘薄膜；
三是通过光刻工艺定位沟道区位置并刻蚀第二层绝缘薄膜、 第一层绝缘薄膜和半导 体衬底， 形成底部低于所述掺杂阱底部的 U形凹槽， 该 U形凹槽将所述掺杂阱分割为漏 区和源区；
其特征是： 在所述步骤一形成 U 形凹槽工艺与步骤三形成源电极、 漏电极和控制栅 工艺之间还包括步骤二形成浮栅和浮栅开口区工艺， 其具体过程依次为：
一是在步骤一所述 U形凹槽的表面生长第三层绝缘薄膜；
二是覆盖 U形凹槽淀积第一层多晶硅直至第一层多晶硅填满 U形凹槽；
三是对第一层多晶硅进行回刻， 刻蚀后剩余的第一层多晶硅的顶部位于第二层绝缘 薄膜上表面与掺杂阱底部之间；
四是刻蚀掉第二层绝缘薄膜、 第一层绝缘薄膜以及外露的第三层绝缘薄膜； 五是覆盖经上述刻蚀处理所形成的结构淀积第二层多晶硅， 该第二层多晶硅与第一 层多晶硅组成多晶硅层；
六是淀积一层光刻胶， 并通过光刻工艺形成图形， 然后沿光刻胶图形刻蚀所述多晶 硅层以形成浮栅和浮栅开口区， 刻蚀深度在漏区和源区底部与第三层绝缘薄膜顶部之 间。
2、 根据权利要求 1 所述的一种半浮栅器件的制造方法， 其特征是所述步骤三形成源 电极、 漏电极和控制栅工艺的具体过程依次为：
一是在步骤二形成结构的器件表面上生成第四层绝缘薄膜， 覆盖所述第四层绝缘薄 膜淀积第三层多晶硅；
二是在所述第三层多晶硅之上淀积第五层绝缘薄膜；
三是通过光刻工艺和刻蚀工艺刻蚀所形成的第五层绝缘薄膜和第三层多晶硅， 并由 刻蚀后剩余的第三层多晶硅形成多晶硅控制栅牺牲材料；
四是覆盖上述所形成结构的器件淀积形成第六层绝缘薄膜， 并对所形成的第六层绝 缘薄膜进行回刻以形成栅极侧墙；
五是在所形成的栅极侧墙的两侧进行源、 漏刻蚀与外延工艺， 以形成源区和漏区的 接触区； 六是覆盖上述所形成结构的器件淀积第一层层间介质材料， 进行抛光直至外露多晶 硅控制栅牺牲材料；
七是刻蚀掉外露的多晶硅控制栅牺牲材料；
八是覆盖所述第四层绝缘薄膜、 淀积第七层绝缘薄膜和金属控制栅， 进行抛光使金 属控制栅占据所述多晶硅控制栅牺牲材料的位置；
九是覆盖上述所形成结构的器件淀积第二层层间介质材料， 并在所述第二层层间介 质材料和第一层层间介质材料中设置接触孔， 形成源电极、 漏电极和栅电极。
3、 根据权利要求 2 所述的一种半浮栅器件的制造方法， 其特征是所述步骤三中在刻 蚀掉多晶硅控制栅牺牲材料后， 先刻蚀掉第四层绝缘薄膜， 再形成第七层绝缘薄膜和金
4、 根据权利要求 2 所述的一种半浮栅器件的制造方法， 其特征是所述步骤三中在刻 蚀掉多晶硅控制栅牺牲材料后， 直接覆盖第四层绝缘薄膜形成金属控制栅。
5、 根据权利要求 2 所述的一种半浮栅器件的制造方法， 其特征是所述步骤三中在形 成栅极侧墙后， 直接通过离子注入的方法， 在源区和漏区内形成高浓度的掺杂区， 形成 源区和漏区的接触区。
6、 根据权利要求 1至 5所述的一种半浮栅器件的制造方法， 其特征是所述第一层绝 缘薄膜的材质为氧化硅、 第二层绝缘薄膜的材质为氮化硅。
7、 根据权利要求 1至 5所述的一种半浮栅器件的制造方法， 其特征是所述第五层绝 缘薄膜和第六层绝缘薄膜的材质分别为氧化硅或氮化硅。
8、 根据权利要求 1至 5所述的一种半浮栅器件的制造方法， 其特征是所述第三层绝 缘薄膜、 第四层绝缘薄膜和第七层绝缘薄膜的材质分别为二氧化硅、 氮化硅、 氮氧化 硅、 具有高介电常数的绝缘材料或者为它们之间的叠层。
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