WO2023025311A1 - 一种sfgt存储阵列、存储芯片和读取数据的方法 - Google Patents

一种sfgt存储阵列、存储芯片和读取数据的方法 Download PDF

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Publication number
WO2023025311A1
WO2023025311A1 PCT/CN2022/115267 CN2022115267W WO2023025311A1 WO 2023025311 A1 WO2023025311 A1 WO 2023025311A1 CN 2022115267 W CN2022115267 W CN 2022115267W WO 2023025311 A1 WO2023025311 A1 WO 2023025311A1
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Prior art keywords
floating gate
gate array
target
voltage change
real
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PCT/CN2022/115267
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English (en)
French (fr)
Inventor
拜福君
俞冰
赵善真
张卫
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西安紫光国芯半导体有限公司
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Priority claimed from CN202110996511.3A external-priority patent/CN115910131A/zh
Priority claimed from CN202110995088.5A external-priority patent/CN115881180A/zh
Application filed by 西安紫光国芯半导体有限公司 filed Critical 西安紫光国芯半导体有限公司
Publication of WO2023025311A1 publication Critical patent/WO2023025311A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present application relates to the field of storage technologies, and in particular to an SFGT storage array, a storage chip and a method for reading data.
  • SFGT Semi-Floating gate transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • Floating Gate Transistor floating gate transistor
  • SFGT can be used to store data, and it mainly works by adding different voltages to word lines and bit lines.
  • the SFGT can be integrated into a storage array, which in turn can realize a large amount of data storage.
  • the present application provides a SFGT storage array, a storage chip and a method for reading data to solve the problem existing in the prior art when reading data stored in a storage unit in the SFGT storage array due to the
  • the longer wire leads to a weaker signal read from the storage unit, which makes the process of reading data take longer and the efficiency of reading data is lower.
  • the present application provides a SFGT storage array
  • the SFGT storage array includes a real half-floating gate array, a reference half-floating gate array and a sense amplifier
  • the real half-floating gate array includes a plurality of real half-floating gate storage arrays A cell, a plurality of first bit lines and a plurality of first word lines, each first bit line in the plurality of first bit lines intersects with each first word line in the plurality of first word lines set to operate the real half-floating gate memory cell, each first bit line in the plurality of first bit lines is connected to the first input terminal of the sense amplifier, and the real half-floating gate
  • the storage unit is arranged at the intersection of the first bit line and the first word line
  • the reference half-floating gate array includes a plurality of second bit lines, and each second bit line in the plurality of second bit lines A bit line is connected to the second input of the sense amplifier.
  • the reference half-floating gate array includes a plurality of reference half-floating gate memory cells and a reference word line, and each second bit line in the plurality of second bit lines intersects the reference word line,
  • the reference half-floating gate memory cell is arranged at a position where the second bit line intersects the reference word line.
  • the plurality of first bit lines in the real half-floating gate array are respectively driven to the first reference half-floating gate array and the second reference half-floating gate array on both sides of the real half-floating gate array.
  • the real half-floating gate array corresponds to the first reference half-floating gate array and the second reference half-floating gate array; among the plurality of first bit lines included in the real half-floating gate array, the odd-numbered first The bit line is connected to the first input end of the first sense amplifier, and the even-numbered first bit line among the plurality of first bit lines included in the real half-floating gate array is connected to the first input end of the second sense amplifier; Each second bit line in the plurality of second bit lines included in the first reference half-floating gate array is connected to the second input terminal of the first sense amplifier; the second reference half-floating gate array Each second bit line of the included plurality of second bit lines is connected to a second input terminal of the second sense amplifier.
  • the present application provides a memory chip, including: an SFGT memory array, a column decoding module, a row decoding module, and a logic control module; the logic control module uses the column decoding module and the row decoding module respectively
  • the decoding module is connected with the SFGT storage array, and is used to write and read the SFGT storage array in units of pages according to the access instruction;
  • the SFGT storage array includes a real half-floating gate array, a reference half-floating gate An array and a sense amplifier;
  • the real half-floating gate array includes a plurality of real half-floating gate memory cells, a plurality of first bit lines and a plurality of first word lines, and each of the plurality of first bit lines is first The bit line and each first word line in the plurality of first word lines intersect each other and are used to operate the real half-floating gate memory cell, and each first word line in the plurality of first bit lines The bit line is connected to the first input end of the sense amplifier, and the real half-floating
  • the memory chip further includes a circuit module, the circuit module is connected to the column decoding module, the row decoding module and the logic control module, and the circuit module is used for decoding the column
  • the code module, the row decoding module and the logic control module provide voltages.
  • the memory chip further includes a data transmission path, and the data transmission path is connected to the column decoding module and the logic control module.
  • the memory chip further includes an address input interface connected to the row decoding module and the logic control module.
  • the memory chip further includes an external interface command decoding circuit, and the external interface command decoding circuit is connected to the logic control module.
  • the memory chip further includes an input-output interface, and the input-output interface is connected to the data transmission path.
  • the present application provides a method for reading data, which is applied to a SFGT storage array, and the SFGT storage array includes a real half-floating gate array, a reference half-floating gate array, and a sense amplifier.
  • the method includes: obtaining the first The first voltage change value of the first target bit line corresponding to the target real half-floating gate memory cell passing by a target word line, wherein the first target word line is a plurality of lines included in the real half-floating gate array One of the first word lines in the first word line; obtaining a second voltage change value of the second target bit line in the reference half-floating gate array; controlling a sense amplifier to amplify the first voltage change value to obtain a first Amplify the voltage change value, and amplify the second voltage change value to obtain a second amplified voltage change value; read the target true value according to the first amplified voltage change value and the second amplified voltage change value The target storage value for the half-floating gate memory cell.
  • the obtaining the second voltage change value of the second target bit line in the reference half-floating gate array includes:
  • the method further includes: receiving read data command; select the first target word line and the reference word line according to the read data command; acquire the first target bit line corresponding to the target real half-floating gate memory cell passed by the first target word line
  • the first voltage variation value includes: acquiring the first voltage variation value of the first target bit line corresponding to the target real half-floating gate memory cell passing by the first target word line after a preset time interval.
  • the acquiring the second voltage change value of the second target bit line in the reference half-floating gate array includes: reading the preset second voltage change value from the sense amplifier.
  • reading the target storage value of the target real half-floating gate memory cell according to the first amplified voltage change value and the second amplified voltage change value includes: When the change value is greater than the second amplified voltage change value, read the target storage value of the target real half-floating gate memory cell as a first storage value; when the first amplified voltage change value is less than the In the case of the second amplified voltage change value, reading the target storage value of the target real half-floating gate memory cell is a second storage value, wherein the first storage value is different from the second storage value.
  • the SFGT storage array includes a real half-floating gate array, a reference half-floating gate array and a sense amplifier;
  • the real half-floating gate array includes a plurality of real half-floating gate memory cells, a plurality of first bit lines and a plurality of first word lines, and each first bit line in the plurality of first bit lines and the plurality of first bit lines Each of the first word lines in the first word lines is arranged to intersect with the real half-floating gate memory cell, and each first bit line in the plurality of first bit lines is connected to the sense amplifier.
  • the real half-floating gate memory cell is set at the intersection of the first bit line and the first word line;
  • the reference half-floating gate array includes a plurality of second bit lines, so Each of the plurality of second bit lines is connected to the second input terminal of the sense amplifier.
  • each first bit line in the plurality of first bit lines included in the real half-floating gate array is connected to the first input end of the sense amplifier, and is referred to in the plurality of second bit lines included in the half-floating gate array.
  • Each of the second bit lines is connected to a second input terminal of the sense amplifier. That is, when reading the data stored in the memory cells in the SFGT memory array, the sense amplifier can be used to amplify the signals read from the memory cells. The time-consuming process of reading data can be reduced, and the efficiency of reading data can be improved.
  • FIG. 1 is a schematic diagram of a SFGT storage array provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of another SFGT storage array provided by the embodiment of the present application.
  • FIG. 3 is a flow chart of a method for reading data provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a SFGT provided in the embodiment of the present application.
  • FIG. 5 is an internal structural diagram of a sense amplifier SA provided in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a memory chip provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a memory core provided by an embodiment of the present application.
  • the present application provides an SFGT storage array, and the SFGT storage array includes a real half-floating gate array, a reference half-floating gate array and a sense amplifier.
  • the real half-floating gate array includes a plurality of real half-floating gate memory cells, a plurality of first bit lines and a plurality of first word lines, and each first bit line in the plurality of first bit lines and the Each first word line in the plurality of first word lines intersects and is used to operate the real half-floating gate memory cell, and each first bit line in the plurality of first bit lines is connected to the The first input end of the sense amplifier is connected, and the real half-floating gate memory cell is arranged at the intersection of the first bit line and the first word line.
  • the reference half-floating gate array includes a plurality of second bit lines, and each second bit line in the plurality of second bit lines is connected to the second input end of the sense amplifier.
  • the SFGT memory array may include a real half-floating gate array, a reference half-floating gate array and sense amplifiers.
  • the real half-floating gate array may include multiple real half-floating gate memory cells, multiple first bit lines and multiple first word lines. And each first bit line in the plurality of first bit lines intersects with each first word line in the plurality of first word lines to form a real semi-floating gate memory cell. Each first bit line of the plurality of first bit lines and each first word line of the plurality of first word lines may be arranged to intersect each other, so as to operate on real semi-floating gate memory cells. Each first bit line of the plurality of first bit lines is connected to a first input terminal of the sense amplifier.
  • the real semi-floating gate memory cell may be arranged at the intersection of the first bit line and the first word line.
  • the reference half-floating gate array may include a plurality of second bit lines, and each second bit line in the plurality of second bit lines may be connected to the second input terminal of the sense amplifier.
  • each first bit line in the plurality of first bit lines included in the real half-floating gate array is connected to the first input end of the sense amplifier, and is referred to in the plurality of second bit lines included in the half-floating gate array.
  • Each of the second bit lines is connected to a second input terminal of the sense amplifier. That is, when reading the data stored in the memory cells in the SFGT memory array, the sense amplifier can be used to amplify the signals read from the memory cells. The time-consuming process of reading data can be reduced, and the efficiency of reading data can be improved.
  • the reference half-floating gate array includes a plurality of reference half-floating gate memory cells and a reference word line, and each second bit line in the plurality of second bit lines intersects the reference word line,
  • the reference half-floating gate memory cell is arranged at a position where the second bit line intersects the reference word line.
  • the reference half-floating gate array may include a plurality of reference half-floating gate memory cells and reference word lines. Each second bit line in the plurality of second bit lines can be arranged to intersect with the reference word line, and is used for operating the reference half-floating gate memory cell.
  • the reference half-floating gate memory cell may be disposed at a position where the second bit line intersects the reference word line.
  • FIG. 1 it is a schematic diagram of a SFGT storage array.
  • a total of 8 regions are shown, numbered 1, 2, 3, 4, 5, 6, 7 and 8 respectively.
  • two regions numbered 1 and 2 are taken as examples for illustration.
  • the area numbered 1 may be a real half-floating gate array, and the area numbered 2 may be a reference half-floating gate array.
  • the four vertical straight lines are the first bit lines
  • the three horizontal straight lines are the first word lines.
  • the four vertical first bit lines intersect with the three horizontal first word lines to form 12 real semi-floating gate memory cells A.
  • Each of the four vertical first bit lines is connected to a first input terminal of a sense amplifier (Sense Amplifier, SA).
  • SA sense Amplifier
  • the four vertical lines are the second bit lines, and the horizontal line at the bottom of the reference half-floating gate array is the reference word line.
  • Four vertical second bit lines intersect with horizontal reference word lines to form four reference half-floating gate memory cells B.
  • Each of the four vertical second bit lines is connected to the second input terminal of the sense amplifier SA.
  • the real half-floating gate array and the reference half-floating gate array can be transformed into each other.
  • the area numbered 2 may actually include three horizontal word lines. If the user selects one of the three horizontal word lines in area 1, area 1 is the real half-floating gate array, and area 2 is the reference half-floating gate array. If the user selects one of the three horizontal word lines in area 2, area 2 is the real half-floating gate array, and area 1 is the reference half-floating gate array. That is, the area where the word line selected by the user is located is the real half-floating gate array, and the area connected to the real half-floating gate array and the two input ends of the same SA is the reference half-floating gate array.
  • the real half-floating gate array corresponds to the first reference half-floating gate array and the second reference half-floating gate array.
  • the odd-numbered first bit lines among the multiple first bit lines included in the real half-floating gate array are connected to the first input end of the first sense amplifier, and the multiple first bit lines included in the real half-floating gate array
  • the even-numbered first bit line among the bit lines is connected to the first input terminal of the second sense amplifier.
  • Each of the plurality of second bit lines included in the first reference half-floating gate array is connected to the second input end of the first sense amplifier.
  • Each of the plurality of second bit lines included in the second reference half-floating gate array is connected to the second input end of the second sense amplifier.
  • the real half-floating gate array may correspond to the first reference half-floating gate array and the second reference half-floating gate array.
  • FIG. 2 it is a schematic diagram of another SFGT storage array. In FIG. 2 , a total of 8 regions are shown, numbered 1, 2, 3, 4, 5, 6, 7 and 8 respectively. In this embodiment, three regions numbered 1, 2 and 3 are taken as examples for illustration.
  • the area numbered 2 may be a real half-floating gate array
  • the area numbered 1 may be a first reference half-floating gate array
  • the area numbered 3 may be a second reference half-floating gate array.
  • the eight vertical straight lines are the first bit lines
  • the three horizontal straight lines are the first word lines.
  • the odd-numbered first bit lines among the plurality of first bit lines included in the real half-floating gate array are connected to the first input terminal of the first sense amplifier.
  • the first bit lines numbered 1, 3, 5, and 7 among the eight first bit lines included in the real half-floating gate array may be connected to the first input end of the first sense amplifier.
  • the even-numbered first bit lines among the plurality of first bit lines included in the real half-floating gate array are connected to the first input end of the second sense amplifier.
  • the first bit lines numbered 2, 4, 6, and 8 among the eight first bit lines included in the real half-floating gate array can be connected to the first input terminal of the second sense amplifier.
  • the four vertical lines are the second bit lines
  • the two horizontal lines at the top and bottom of the first reference half-floating gate array are the reference word lines.
  • Eight reference half-floating gate memory cells exist at intersections of the four vertical second bit lines and the two horizontal reference word lines.
  • Each of the plurality of second bit lines included in the first reference half-floating gate array is connected to the second input terminal of the first sense amplifier, that is, the four first reference half-floating gate arrays include the second bit line.
  • Each second bit line of the two bit lines is connected to the second input end of the first sense amplifier.
  • the second reference half-floating gate array four of the eight vertical straight lines are second bit lines, and two horizontal straight lines at the top and bottom of the second reference half-floating gate array are reference word lines. There are 8 reference half-floating gate memory cells at intersections of the 4 vertical second bit lines and the 2 horizontal reference word lines.
  • Each of the plurality of second bit lines included in the second reference half-floating gate array is connected to the second input end of the second sense amplifier, that is, the four second bit lines included in the second reference half-floating gate array
  • the two-bit line is connected with the second input end of the second sense amplifier.
  • the multiple first bit lines included in the real half-floating gate array can be driven by the first reference half-floating gate array and the second reference half-floating gate array on both sides of the odd and even, and are sensed, amplified and stored by two SAs.
  • the data can reduce the coupling effect and reduce the error rate when reading the stored value of the real semi-floating gate memory cell.
  • the real half-floating gate array and the reference half-floating gate array can be transformed into each other.
  • the area numbered 3 may also include three horizontal word lines. If the user selects one of the three horizontal word lines in area 2, then area 2 is the real half-floating gate array, at this time area 1 is the first reference half-floating gate array, and area 3 is the The second reference half-floating gate array. If the user selects one of the three horizontal word lines in area 3, then area 3 is the real half-floating gate array, at this time area 2 is the first reference half-floating gate array, and area 4 is the The second reference half-floating gate array.
  • the area where the word line selected by the user is located is the real half-floating gate array, and the two adjacent areas above and below the real half-floating gate array are the first reference half-floating gate array and the second reference half-floating gate array .
  • each first bit line in the plurality of first bit lines included in the real half-floating gate array is connected to the first input terminal of the sense amplifier, and the plurality of first bit lines included in the half-floating gate array are referred to as Each second bit line of the two bit lines is connected to the second input terminal of the sense amplifier. That is, when reading the data stored in the memory cells in the SFGT memory array, the sense amplifier can be used to amplify the signals read from the memory cells. The time-consuming process of reading data can be reduced, and the efficiency of reading data can be improved.
  • the embodiment of the present application provides a SFGT storage array
  • the SFGT storage array includes a real half-floating gate array, a reference half-floating gate array and a sense amplifier
  • the real half-floating gate array includes a plurality of real half-floating gate arrays
  • a semi-floating gate memory cell a plurality of first bit lines and a plurality of first word lines, each first bit line in the plurality of first bit lines and each first bit line in the plurality of first word lines
  • a word line intersecting setting is used to operate the real semi-floating gate memory cell, each first bit line in the plurality of first bit lines is connected to the first input end of the sense amplifier, the The real half-floating gate memory cell is arranged at the intersection of the first bit line and the first word line;
  • the reference half-floating gate array includes a plurality of second bit lines, and the plurality of second bit lines are Each second bit line is connected to the second input terminal of the sense amplifier.
  • each first bit line in the plurality of first bit lines included in the real half-floating gate array is connected to the first input end of the sense amplifier, and is referred to in the plurality of second bit lines included in the half-floating gate array.
  • Each of the second bit lines is connected to a second input terminal of the sense amplifier. That is, when reading the data stored in the memory cells in the SFGT memory array, the sense amplifier can be used to amplify the signals read from the memory cells. The time-consuming process of reading data can be reduced, and the efficiency of reading data can be improved.
  • FIG. 3 is a flow chart of a method for reading data provided by the present application, which is applied to the SFGT storage array described in the foregoing embodiments. As shown in Figure 3, the following steps are included:
  • Step 301 Obtain the first voltage change value of the first target bit line corresponding to the target real half-floating gate memory cell passing by the first target word line, wherein the first target word line is the real half-floating gate array One first word line among the plurality of first word lines included.
  • Step 302 acquiring a second voltage change value of a second target bit line in the reference half-floating gate array.
  • Step 303 controlling the sense amplifier to amplify the first voltage change value to obtain a first amplified voltage change value, and amplify the second voltage change value to obtain a second amplified voltage change value.
  • Step 304 read the target storage value of the target real half-floating gate memory cell according to the first amplified voltage change value and the second amplified voltage change value.
  • the area numbered 1 and the area numbered 2 in FIG. 1 are taken as an example for illustration.
  • the first voltage change value of the first target bit line corresponding to the target real half-floating gate memory cell passing by the first target word line may be acquired.
  • the first target word line is one first word line among the plurality of first word lines included in the real semi-floating gate array.
  • the first voltage change value of the first target bit line corresponding to the target real half-floating gate memory cell A passed by the uppermost first target word line in the area numbered 1 may be acquired.
  • the first target word line is one of the three first word lines included in the real semi-floating gate array.
  • a second voltage variation value of the second target bit line in the reference half-floating gate array may also be obtained.
  • step 302 it also includes:
  • the second voltage change value of the second target bit line corresponding to the reference half floating gate memory cell passing by the reference word line in the reference half floating gate array may also be acquired.
  • the second voltage change value of the second target bit line corresponding to the reference semi-floating gate memory cell B passed by the reference word line in the area numbered 2 may be acquired.
  • step 302 it also includes:
  • a preset second voltage change value may also be read from the sense amplifier.
  • the sense amplifier may be controlled to amplify the first voltage change value to obtain the first amplified voltage change value, and to amplify the second voltage change value to obtain the second amplified voltage change value.
  • step 301 it also includes:
  • the acquiring the first voltage change value of the first target bit line corresponding to the target real half-floating gate memory cell passed by the first target word line includes:
  • the first voltage change value of the first target bit line corresponding to the target real half-floating gate memory cell passed by the first target word line is acquired.
  • FIG. 4 it is a schematic diagram of a SFGT.
  • the SFGT includes word lines, bit lines and ground.
  • the working principle of SFGT is to apply different voltages to the word line and bit line to work.
  • the read data command can also be received, and then according to the read data command, the uppermost first target word line in the area numbered 1 can be selected, and the reference word line in the area numbered 2 can be selected.
  • word line That is, the first target word line and the reference word line selected according to address decoding can be turned on. After the first target word line is turned on, the current flows to the ground through the SFGT. After a preset time interval, that is, after a period of discharge, the first target real half-floating gate memory cell A corresponding to the first target word line can be obtained. A first voltage change value of a target bit line. In this way, the user can select a word line in the real half-floating gate array according to his own needs, and then realize reading data in the target real half-floating gate memory cell that the word line passes through.
  • the realization process is simple, convenient and fast.
  • the sense amplifier can be controlled to amplify the first voltage change value ⁇ V1 of the first target bit line to obtain the first amplified voltage change value, and to amplify the second voltage change value ⁇ V1.
  • the second voltage change value ⁇ V2 of the target bit line is amplified to obtain a second amplified voltage change value.
  • the target storage value of the target real half-floating gate memory cell may be read according to the first amplified voltage change value and the second amplified voltage change value.
  • the target real half-floating gate storage can be obtained The relationship between the current I1 flowing in the cell and the current I2 flowing in the reference half-floating gate memory cell. Furthermore, the target storage value in the target real half-floating gate memory cell can be determined according to the size relationship between I1 and I2.
  • step 304 also includes:
  • the target storage value of the target real half-floating gate memory cell When the first amplified voltage change value is greater than the second amplified voltage change value, read the target storage value of the target real half-floating gate memory cell as a first storage value; When the amplified voltage variation value is smaller than the second amplified voltage variation value, read the target storage value of the target real half-floating gate memory cell as a second storage value, wherein the first storage value and the The second stored value is different.
  • the first amplified voltage change value is greater than the second amplified voltage change value, it means that the current I1 flowing in the target real half-floating gate memory cell is greater than the current I2 flowing in the reference half-floating gate memory cell, and at this time, it can be read
  • the target storage value of the target real half-floating gate memory cell is taken as the first storage value.
  • the first stored value may be 1.
  • the first amplified voltage change value is smaller than the second amplified voltage change value
  • the current I1 flowing in the target real half-floating gate memory cell is smaller than the current I2 flowing in the reference half-floating gate memory cell, and at this time, it can be read
  • the target storage value of the target real half-floating gate memory cell is taken as the second storage value.
  • the first stored value and the second stored value are different.
  • the second stored value may be 0.
  • the target storage value of the target real half-floating gate memory cell can be determined according to the magnitude relationship between the first amplified voltage change value and the second amplified voltage change value, which can reduce the time-consuming process of reading data and improve the efficiency of reading data. efficiency.
  • all the bit line voltages in the SFGT memory array can be switched to a low potential, and the memory cells in the selected SFGT memory array can be erased
  • the purpose of the operation is to restore the memory cells of the SFGT memory array to the initial state, so as to facilitate the next data writing or programming operation.
  • the erasing operation destroys the original data in the storage unit, and the storage unit of the erased SFGT storage array is in a retained state.
  • the programming operation can also be performed in the SFGT memory array, which is to write the data in the sense amplifier into the selected memory cells.
  • FIG. 5 it is an internal structure diagram of a sense amplifier SA.
  • SA_core is the core of SA work, and its main function is to amplify signals.
  • a multiplexer (multiplexer, MUX) is to realize the gating of the bit lines.
  • bit lines (bit line, bl) are also shown.
  • the sense amplifier can be controlled to amplify the first voltage change value of the first target bit line to obtain the first amplified voltage change value; and to amplify the second voltage change value of the second target bit line to obtain The second amplifies the voltage change value.
  • the target storage value of the target real half-floating gate memory cell can be read according to the first amplified voltage change value and the second amplified voltage change value. That is, when reading the data stored in the memory cells in the SFGT memory array, the sense amplifier can be used to amplify the signals read from the memory cells. The time-consuming process of reading data can be reduced, and the efficiency of reading data can be improved.
  • the method for reading data obtained by the embodiment of the present application obtains the first voltage change value of the first target bit line corresponding to the target real half-floating gate memory cell passing by the first target word line,
  • the first target word line is one of the plurality of first word lines included in the real half-floating gate array; the first word line of the second target bit line in the reference half-floating gate array is obtained.
  • Two voltage change values controlling the sensitive amplifier to amplify the first voltage change value to obtain a first amplified voltage change value, and amplifying the second voltage change value to obtain a second amplified voltage change value; according to the The first amplified voltage change value and the second amplified voltage change value read the target storage value of the target real half-floating gate memory cell.
  • the sense amplifier can be controlled to amplify the first voltage change value of the first target bit line to obtain the first amplified voltage change value; and to amplify the second voltage change value of the second target bit line to obtain the second amplified voltage change value.
  • the target storage value of the target real half-floating gate memory cell can be read according to the first amplified voltage change value and the second amplified voltage change value. That is, when reading the data stored in the memory cells in the SFGT memory array, the signals read from the memory cells can be amplified by the sense amplifier. The time-consuming process of reading data can be reduced, and the efficiency of reading data can be improved.
  • FIG. 6 is a schematic diagram of a memory chip provided by the present application, and the memory chip may include: an SFGT memory array, a column decoding module, a row decoding module and a logic control module;
  • the logic control module is respectively connected to the SFGT storage array through the column decoding module and the row decoding module, and is used to write and read the SFGT storage array in units of pages according to access instructions ;
  • the SFGT storage array includes a real half-floating gate array, a reference half-floating gate array and a sense amplifier;
  • the real half-floating gate array includes a plurality of real half-floating gate memory cells, a plurality of first bit lines and a plurality of first word lines, and each first bit line in the plurality of first bit lines and the Each first word line in the plurality of first word lines intersects and is used to operate the real half-floating gate memory cell, and each first bit line in the plurality of first bit lines is connected to the The first input end of the sense amplifier is connected, and the real half-floating gate memory cell is set at the intersection of the first bit line and the first word line;
  • the reference half-floating gate array includes a plurality of second bit lines, and each second bit line in the plurality of second bit lines is connected to the second input end of the sense amplifier.
  • the SFGT storage array may adopt the SFGT storage array of the embodiments shown in any one of FIG. 1 to FIG. 6 .
  • the memory chip may include an SFGT memory array, a column decoding module (Col_dec), a row decoding module (Row_dec) and a logic control module (Control logic).
  • the logic control module can be connected to the SFGT storage array through the column decoding module and the row decoding module respectively, and is used for writing and reading the SFGT storage array in units of pages according to access instructions.
  • the structure of the SFGT storage array has been described in detail in the foregoing embodiments, and will not be repeated here.
  • the memory chip further includes a circuit module, the circuit module is connected to the column decoding module, the row decoding module and the logic control module, and the circuit module is used for decoding the column
  • the code module, the row decoding module and the logic control module provide voltages.
  • the memory chip may further include a circuit module (Generator), and the circuit module may be connected to a column decoding module, a row decoding module and a logic control module.
  • the circuit module is used to provide voltage for the column decoding module, the row decoding module and the logic control module, and the generator module provides various operating voltages for the memory chip.
  • the memory chip further includes a data transmission path, and the data transmission path is connected to the column decoding module and the logic control module.
  • the memory chip can also include a data transmission path (Data path), and the data transmission path can be connected with the column decoding module and the logic control module.
  • Data path data transmission path
  • the memory chip further includes an address input interface connected to the row decoding module and the logic control module.
  • the memory chip can also include an address input interface (Add dec), and the address input interface can be connected with the row decoding module and the logic control module.
  • Address input interface can be connected with the row decoding module and the logic control module.
  • the memory chip further includes an external interface command decoding circuit, and the external interface command decoding circuit is connected to the logic control module.
  • the memory chip can also include an external interface command decoding circuit (Command dec), and the external interface command decoding circuit can be connected to the logic control module.
  • Common dec an external interface command decoding circuit
  • the memory chip further includes an input-output interface, and the input-output interface is connected to the data transmission path.
  • the memory chip may further include an input/output interface (input/output, IO), and the input/output interface may be connected to a data transmission path.
  • input/output input/output
  • control logic is the control center of the memory chip. It mainly provides various logic and voltage for the core of the memory chip.
  • the core of the memory chip is actually the core of the memory chip.
  • FIG. 7 it is a schematic diagram of a core of a memory chip. It includes a row decoding module (Row_dec), a column decoding module (Col_dec) and a logic control module (Control logic) that generates various timing control signals.
  • Row_dec is a row decoding module, which selects the corresponding word line according to the input address, and then starts to read data.
  • Col_dec is a column decoding module, which decodes the input column address.
  • the embodiment of the present application provides a memory chip, which can amplify the signal read from the memory unit through a sense amplifier.
  • the time-consuming process of reading data can be reduced, and the efficiency of reading data can be improved.

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Abstract

本申请公开了一种SFGT存储阵列、存储芯片和读取数据的方法，SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，多条第一位线中的每条第一位线和多条第一字线中的每条第一字线相交设置，用于对真实半浮栅存储单元进行操作，多条第一位线中的每条第一位线与灵敏放大器的第一输入端连接，真实半浮栅存储单元设置在第一位线和第一字线相交的位置；参考半浮栅阵列包含多条第二位线，多条第二位线中的每条第二位线与灵敏放大器的第二输入端连接。在读取SFGT存储阵列中的存储单元内所存储的数据时，可以通过灵敏放大器对从存储单元读取出的信号进行放大，可以提高读取数据的效率。

Description

一种SFGT存储阵列、存储芯片和读取数据的方法
相关申请的交叉引用
本申请基于2021年8月27日提交的中国专利申请202110995088.5和中国专利申请202110996511.3主张其优先权，此处通过参照引入其全部的记载内容。
【技术领域】
本申请涉及存储技术领域，尤其涉及一种SFGT存储阵列、存储芯片和读取数据的方法。
【背景技术】
半浮栅晶体管(Semi-Floating gate transistor,SFGT)是介于金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)和浮栅晶体管(Floating Gate Transistor)之间的晶体管。SFGT可以用来存储数据，其主要在字线(word line)、位线(bit line)加不同的电压来工作。可以将SFGT集成为存储阵列，进而可以实现大量的数据存储。
现有技术中，在读取SFGT存储阵列中的存储单元内所存储的数据时，由于SFGT存储阵列的位线较长，导致从存储单元读取出的信号比较微弱，使得读取数据的过程耗时较长，读取数据的效率较低。
【发明内容】
本申请提供了一种SFGT存储阵列、存储芯片和读取数据的方法，以解决现有技术中存在的在读取SFGT存储阵列中的存储单元内所存储的数据时，由于SFGT存储阵列的位线较长，导致从存储单元读取出的信号比较微弱，使得读取数据的过程耗时较长，读取数据的效率较低的技术问题。
第一方面，本申请提供了一种SFGT存储阵列，所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设置在所述第一位线和所述第一字线相交的位置；所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。
可选的，所述参考半浮栅阵列包含多个参考半浮栅存储单元和参考字线，所述多条第二位线中的每条第二位线与所述参考字线相交设置，用于对所述参考半浮栅 存储单元进行操作，所述参考半浮栅存储单元设置在所述第二位线和所述参考字线相交的位置。
可选的，所述真实半浮栅阵列、所述参考半浮栅阵列和所述灵敏放大器一一对应。
可选的，所述真实半浮栅阵列中的多条第一位线分别向所述真实半浮栅阵列两侧的第一参考半浮栅阵列和第二参考半浮栅阵列驱动。
可选的，所述真实半浮栅阵列对应第一参考半浮栅阵列和第二参考半浮栅阵列；所述真实半浮栅阵列所包含的多条第一位线中的奇数序号第一位线与第一灵敏放大器的第一输入端连接，所述真实半浮栅阵列所包含的多条第一位线中的偶数序号第一位线与第二灵敏放大器的第一输入端连接；所述第一参考半浮栅阵列所包含的多条第二位线中的每条第二位线与所述第一灵敏放大器的第二输入端连接；所述第二参考半浮栅阵列所包含的多条第二位线中的每条第二位线与所述第二灵敏放大器的第二输入端连接。
第二方面，本申请提供了一种存储芯片，包括:SFGT存储阵列、列译码模块、行译码模块和逻辑控制模块；所述逻辑控制模块分别通过所述列译码模块和所述行译码模块与所述SFGT存储阵列连接，用于根据访问指令对所述SFGT存储阵列进行以页为单位的写入和读取；所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设置在所述第一位线和所述第一字线相交的位置；所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。
可选的，所述存储芯片还包括电路模块，所述电路模块与所述列译码模块、所述行译码模块和所述逻辑控制模块连接，所述电路模块用于为所述列译码模块、所述行译码模块和所述逻辑控制模块提供电压。
可选的，所述存储芯片还包括数据传输路径，所述数据传输路径与所述列译码模块和所述逻辑控制模块连接。
可选的，所述存储芯片还包括地址输入接口，所述地址输入接口与所述行译码模块和所述逻辑控制模块连接。
可选的，所述存储芯片还包括外部接口命令译码电路，所述外部接口命令译码电路与所述逻辑控制模块连接。
可选的，所述存储芯片还包括输入输出接口，所述输入输出接口与所述数据传 输路径连接。
第三方面，本申请提供了一种读取数据的方法，应用于SFGT存储阵列，所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器，所述方法包括：获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值，其中，所述第一目标字线为所述真实半浮栅阵列所包含的多条第一字线中的一条第一字线；获取所述参考半浮栅阵列中第二目标位线的第二电压变化值；控制灵敏放大器对所述第一电压变化值进行放大，获得第一放大电压变化值，以及对所述第二电压变化值进行放大，获得第二放大电压变化值；根据所述第一放大电压变化值以及所述第二放大电压变化值，读取所述目标真实半浮栅存储单元的目标存储值。
可选的，所述获取所述参考半浮栅阵列中第二目标位线的第二电压变化值，包括：
获取所述参考半浮栅阵列中的参考字线经过的参考半浮栅存储单元所对应的第二目标位线的第二电压变化值。
可选的，在所述获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值的步骤之前，所述方法还包括：接收读取数据命令；根据所述读取数据命令，选择所述第一目标字线以及所述参考字线；所述获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值，包括：在经过预设时间间隔之后，获取所述第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值。
可选的，所述获取所述参考半浮栅阵列中第二目标位线的第二电压变化值，包括：从所述灵敏放大器内读取预先设置的所述第二电压变化值。
可选的，所述根据所述第一放大电压变化值以及所述第二放大电压变化值，读取所述目标真实半浮栅存储单元的目标存储值，包括：在所述第一放大电压变化值大于所述第二放大电压变化值的情况下，读取所述目标真实半浮栅存储单元的所述目标存储值为第一存储值；在所述第一放大电压变化值小于所述第二放大电压变化值的情况下，读取所述目标真实半浮栅存储单元的所述目标存储值为第二存储值，其中，所述第一存储值和所述第二存储值不同。
由以上技术方案可知，本申请实施例提供的一种SFGT存储阵列、存储芯片和读取数据的方法，所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设 置在所述第一位线和所述第一字线相交的位置；所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。这样，真实半浮栅阵列所包含的多条第一位线中的每条第一位线与灵敏放大器的第一输入端连接，且参考半浮栅阵列所包含的多条第二位线中的每条第二位线与灵敏放大器的第二输入端连接。即在读取SFGT存储阵列中的存储单元内所存储的数据时，可以通过灵敏放大器对从存储单元读取出的信号进行放大。可以减少读取数据的过程的耗时，提高读取数据的效率。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1为本申请实施例提供的一种SFGT存储阵列的示意图；
图2为本申请实施例提供的另一种SFGT存储阵列的示意图；
图3为本申请实施例提供的一种读取数据的方法的流程图；
图4为本申请实施例提供的一种SFGT的示意图；
图5为本申请实施例提供的一种灵敏放大器SA的内部结构图；
图6为本申请实施例提供的一种存储芯片的示意图；
图7为本申请实施例提供的一种存储器的核的示意图。
【具体实施方式】
为了更好的理解本说明书实施例提供的技术方案，下面通过附图以及具体实施例对本说明书实施例的技术方案做详细的说明，应当理解本说明书实施例以及实施例中的具体特征是对本说明书实施例技术方案的详细的说明，而不是对本说明书技术方案的限定，在不冲突的情况下，本说明书实施例以及实施例中的技术特征可以相互组合。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外 的相同要素。术语“两个以上”包括两个或大于两个的情况。
本申请提供一种SFGT存储阵列，所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器。
所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设置在所述第一位线和所述第一字线相交的位置。
所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。
在具体实施例中，SFGT存储阵列可以包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器。
真实半浮栅阵列可以包含多个真实半浮栅存储单元、多条第一位线和多条第一字线。且多条第一位线中的每条第一位线和多条第一字线中的每条第一字线相交形成真实半浮栅存储单元。多条第一位线中的每条第一位线和多条第一字线中的每条第一字线可以相交设置，用于对真实半浮栅存储单元进行操作。多条第一位线中的每条第一位线与灵敏放大器的第一输入端连接。真实半浮栅存储单元可以设置在第一位线和第一字线相交的位置。
参考半浮栅阵列可以包含多条第二位线，且多条第二位线中的每条第二位线可以与灵敏放大器的第二输入端连接。这样，真实半浮栅阵列所包含的多条第一位线中的每条第一位线与灵敏放大器的第一输入端连接，且参考半浮栅阵列所包含的多条第二位线中的每条第二位线与灵敏放大器的第二输入端连接。即在读取SFGT存储阵列中的存储单元内所存储的数据时，可以通过灵敏放大器对从存储单元读取出的信号进行放大。可以减少读取数据的过程的耗时，提高读取数据的效率。
可选的，所述参考半浮栅阵列包含多个参考半浮栅存储单元和参考字线，所述多条第二位线中的每条第二位线与所述参考字线相交设置，用于对所述参考半浮栅存储单元进行操作，所述参考半浮栅存储单元设置在所述第二位线和所述参考字线相交的位置。
在具体实施例中，参考半浮栅阵列可以包含多个参考半浮栅存储单元和参考字线。多条第二位线中的每条第二位线可以与参考字线相交设置，用于对参考半浮栅存储单元进行操作。参考半浮栅存储单元可以设置在第二位线和参考字线相交的位置。
可选的，所述真实半浮栅阵列、所述参考半浮栅阵列和所述灵敏放大器一一对应。
在具体实施例中，真实半浮栅阵列、参考半浮栅阵列和灵敏放大器一一对应。如图1所示，为一种SFGT存储阵列的示意图。在图1中，一共示出了8个区域，编号分别为1、2、3、4、5、6、7和8。在本实施例中，以编号为1以及编号为2的两个区域为例进行说明。
编号为1的区域可以为真实半浮栅阵列，编号为2的区域可以为参考半浮栅阵列。在真实半浮栅阵列中，竖直的四条直线均为第一位线，水平的三条直线为第一字线。竖直的四条第一位线与水平的三条第一字线相交形成12个真实半浮栅存储单元A。竖直的四条第一位线中的每条第一位线与灵敏放大器(Sense Amplifier,SA)的第一输入端连接。
在参考半浮栅阵列中，竖直的四条直线均为第二位线，位于参考半浮栅阵列底部的水平直线为参考字线。竖直的四条第二位线与水平的参考字线相交形成4个参考半浮栅存储单元B。竖直的四条第二位线中的每条第二位线与灵敏放大器SA的第二输入端连接。
需要说明的是，真实半浮栅阵列和参考半浮栅阵列是可以相互转化的。例如，在图1中，实际上编号为2的区域也可以包含水平的三条字线。如果用户选中的为区域1中的水平的三条字线中的某一条字线，则区域1即为真实半浮栅阵列，此时区域2即为参考半浮栅阵列。如果用户选中的为区域2中的水平的三条字线中的某一条字线，则区域2即为真实半浮栅阵列，此时区域1即为参考半浮栅阵列。也即用户选中的字线所在的区域即为真实半浮栅阵列，而与该真实半浮栅阵列连接于同一个SA的两个输入端的区域即为参考半浮栅阵列。
可选的，所述真实半浮栅阵列对应第一参考半浮栅阵列和第二参考半浮栅阵列。
所述真实半浮栅阵列所包含的多条第一位线中的奇数序号第一位线与第一灵敏放大器的第一输入端连接，所述真实半浮栅阵列所包含的多条第一位线中的偶数序号第一位线与第二灵敏放大器的第一输入端连接。
所述第一参考半浮栅阵列所包含的多条第二位线中的每条第二位线与所述第一灵敏放大器的第二输入端连接。
所述第二参考半浮栅阵列所包含的多条第二位线中的每条第二位线与所述第二灵敏放大器的第二输入端连接。
在具体实施例中，真实半浮栅阵列可以对应第一参考半浮栅阵列和第二参考半浮栅阵列。如图2所示，为另一种SFGT存储阵列的示意图。在图2中，一共示出了8个区域，编号分别为1、2、3、4、5、6、7和8。在本实施例中，以编号为1、编号为2以及编号为3的三个区域为例进行说明。在图2中，编号为2的区域可以为真实半浮栅阵列，编号为1的区域可以为第一参考半浮栅阵列，编号为3的区域可以为第二参考半浮栅阵列。
在真实半浮栅阵列中，竖直的8条直线均为第一位线，水平的三条直线为第一字线。竖直的8条第一位线与水平的三条第一字线的相交位置处存在24个真实半浮栅存储单元。且真实半浮栅阵列所包含的多条第一位线中的奇数序号第一位线与第一灵敏放大器的第一输入端连接。例如，真实半浮栅阵列所包含的8条第一位线中的序号为1、3、5、7的第一位线可以与第一灵敏放大器的第一输入端连接。真实半浮栅阵列所包含的多条第一位线中的偶数序号第一位线与第二灵敏放大器的第一输入端连接。例如，真实半浮栅阵列所包含的8条第一位线中的序号为2、4、6、8的第一位线可以与第二灵敏放大器的第一输入端连接。
在第一参考半浮栅阵列中，竖直的四条直线均为第二位线，位于第一参考半浮栅阵列顶部和底部的两条水平直线为参考字线。竖直的四条第二位线与水平的两条参考字线的相交位置处存在8个参考半浮栅存储单元。第一参考半浮栅阵列所包含的多条第二位线中的每条第二位线与第一灵敏放大器的第二输入端连接，即第一参考半浮栅阵列所包含的4条第二位线中的每条第二位线与第一灵敏放大器的第二输入端连接。
在第二参考半浮栅阵列中，竖直的8条直线中的4条直线为第二位线，位于第二参考半浮栅阵列顶部和底部的两条水平直线为参考字线。竖直的4条第二位线与水平的两条参考字线的相交位置处存在8个参考半浮栅存储单元。第二参考半浮栅阵列所包含的多条第二位线中的每条第二位线与第二灵敏放大器的第二输入端连接，即第二参考半浮栅阵列所包含的4条第二位线与第二灵敏放大器的第二输入端连接。这样，真实半浮栅阵列中所包含的多条第一位线可以分奇偶向两侧的第一参考半浮栅阵列和第二参考半浮栅阵列驱动，并由两个SA去感应放大存储数据，可以减少耦合效应，降低读取真实半浮栅存储单元的存储值时的错误率。
需要说明的是，在图2这种SFGT存储阵列中，真实半浮栅阵列和参考半浮栅阵列是可以相互转化的。例如，在图2中，编号为3的区域也可以包含水平的三条字线。如果用户选中的为区域2中的水平的三条字线中的某一条字线，则区域2即为真实半浮栅阵列，此时区域1即为第一参考半浮栅阵列，区域3即为第二参考半浮栅阵列。如果用户选中的为区域3中的水平的三条字线中的某一条字线，则区域3即为真实半浮栅阵列，此时区域2即为第一参考半浮栅阵列，区域4即为第二参考半浮栅阵列。也即用户选中的字线所在的区域即为真实半浮栅阵列，而与该真实半浮栅阵列上下相邻的两个区域即为第一参考半浮栅阵列和第二参考半浮栅阵列。
现有技术中，在读取SFGT存储阵列中的存储单元内所存储的数据时，由于SFGT存储阵列的位线较长，导致从存储单元读取出的信号比较微弱，使得读取数据的过程耗时较长，读取数据的效率较低。
而在本申请中，真实半浮栅阵列所包含的多条第一位线中的每条第一位线与灵 敏放大器的第一输入端连接，且参考半浮栅阵列所包含的多条第二位线中的每条第二位线与灵敏放大器的第二输入端连接。即在读取SFGT存储阵列中的存储单元内所存储的数据时，可以通过灵敏放大器对从存储单元读取出的信号进行放大。可以减少读取数据的过程的耗时，提高读取数据的效率。
由以上技术方案可知，本申请实施例提供的一种SFGT存储阵列，所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设置在所述第一位线和所述第一字线相交的位置；所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。这样，真实半浮栅阵列所包含的多条第一位线中的每条第一位线与灵敏放大器的第一输入端连接，且参考半浮栅阵列所包含的多条第二位线中的每条第二位线与灵敏放大器的第二输入端连接。即在读取SFGT存储阵列中的存储单元内所存储的数据时，可以通过灵敏放大器对从存储单元读取出的信号进行放大。可以减少读取数据的过程的耗时，提高读取数据的效率。
参见图3，图3是本申请提供的一种读取数据的方法的流程图，应用于前述实施例中所述的SFGT存储阵列。如图3所示，包括以下步骤：
步骤301、获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值，其中，所述第一目标字线为所述真实半浮栅阵列所包含的多条第一字线中的一条第一字线。
步骤302、获取所述参考半浮栅阵列中第二目标位线的第二电压变化值。
步骤303、控制灵敏放大器对所述第一电压变化值进行放大，获得第一放大电压变化值，以及对所述第二电压变化值进行放大，获得第二放大电压变化值。
步骤304、根据所述第一放大电压变化值以及所述第二放大电压变化值，读取所述目标真实半浮栅存储单元的目标存储值。
在具体实施例中，在步骤301中，以图1中的编号为1的区域和编号为2的区域为例进行说明。可以获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值。其中，第一目标字线为真实半浮栅阵列所包含的多条第一字线中的一条第一字线。例如，可以获取编号为1的区域中的位于最上面的第一目标字线经过的目标真实半浮栅存储单元A所对应的第一目标位线的第一电压变化值。其中，第一目标字线为真实半浮栅阵列所包含的3条第一字线中的一条第一字线。
在具体实施例中，在步骤302中，还可以获取参考半浮栅阵列中第二目标位线的第二电压变化值。
在具体实施例中，在步骤302中，还包括：
获取所述参考半浮栅阵列中的所述参考字线经过的参考半浮栅存储单元所对应的第二目标位线的第二电压变化值。
在具体实施例中，在步骤302中，还可以获取参考半浮栅阵列中的参考字线经过的参考半浮栅存储单元所对应的第二目标位线的第二电压变化值。例如，可以获取编号为2的区域中的参考字线经过的参考半浮栅存储单元B所对应的第二目标位线的第二电压变化值。
在具体实施例中，在步骤302中，还包括：
从所述灵敏放大器内读取预先设置的所述第二电压变化值。
在具体实施例中，在步骤302中，还可以从灵敏放大器内读取预先设置的第二电压变化值。
在具体实施例中，在步骤303中，可以控制灵敏放大器对第一电压变化值进行放大，获得第一放大电压变化值，以及对第二电压变化值进行放大，获得第二放大电压变化值。
在具体实施例中，在步骤301之前，还包括：
接收读取数据命令；
根据所述读取数据命令，选择所述第一目标字线以及所述参考字线；
所述获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值，包括：
在经过预设时间间隔之后，获取所述第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值。
如图4所示，为一种SFGT的示意图。在图4中，SFGT包含字线、位线和地。SFGT的工作原理为在字线，位线加不同的电压来工作。
在具体实施过程中，还可以接收读取数据命令，进而可以根据读取数据命令，选择编号为1的区域中的位于最上面的第一目标字线，以及选择编号为2的区域中的参考字线。即可以打开根据地址译码选择的第一目标字线以及参考字线。打开第一目标字线之后电流经SFGT流向地，在经过预设时间间隔之后，即经过一段时间的放电之后，可以获取第一目标字线经过的目标真实半浮栅存储单元A所对应的第一目标位线的第一电压变化值。这样，用户可以根据自身需要选择真实半浮栅阵列中的一条字线，进而实现对该字线所经过的目标真实半浮栅存储单元内的数据进行读取。实现过程简单，方便快捷。
需要说明的是，根据Q＝I×t＝C×V，随着时间的变化，则ΔQ＝I×Δt＝C×ΔV。 因此，在经过预设时间间隔之后，即经过一段时间的放电之后，可以控制灵敏放大器对第一目标位线的第一电压变化值ΔV1进行放大，获得第一放大电压变化值，以及对第二目标位线的第二电压变化值ΔV2进行放大，获得第二放大电压变化值。
在具体实施例中，在步骤304中，可以根据第一放大电压变化值以及第二放大电压变化值，读取目标真实半浮栅存储单元的目标存储值。
由于第一目标位线的电容值C1与第二目标位线的电容值C2相同，因此根据第一放大电压变化值与第二放大电压变化值的大小关系，可以得出目标真实半浮栅存储单元内流过的电流I1与参考半浮栅存储单元内流过的电流I2的大小关系。进而可以根据I1与I2的大小关系，确定目标真实半浮栅存储单元内的目标存储值。
在具体实施例中，步骤304还包括：
在所述第一放大电压变化值大于所述第二放大电压变化值的情况下，读取所述目标真实半浮栅存储单元的所述目标存储值为第一存储值；在所述第一放大电压变化值小于所述第二放大电压变化值的情况下，读取所述目标真实半浮栅存储单元的所述目标存储值为第二存储值，其中，所述第一存储值和所述第二存储值不同。
在第一放大电压变化值大于第二放大电压变化值的情况下，说明目标真实半浮栅存储单元内流过的电流I1大于参考半浮栅存储单元内流过的电流I2，此时可以读取目标真实半浮栅存储单元的目标存储值为第一存储值。例如，该第一存储值可以为1。
在第一放大电压变化值小于第二放大电压变化值的情况下，说明目标真实半浮栅存储单元内流过的电流I1小于参考半浮栅存储单元内流过的电流I2，此时可以读取目标真实半浮栅存储单元的目标存储值为第二存储值。其中，第一存储值和第二存储值不同。例如，该第二存储值可以为0。这样，可以根据第一放大电压变化值与第二放大电压变化值的大小关系，确定目标真实半浮栅存储单元的目标存储值，可以减少读取数据的过程的耗时，提高读取数据的效率。
需要说明的是，读取目标真实半浮栅存储单元的目标存储值之后，可以将SFGT存储阵列中所有的位线电压切换到低电位，可以对选中的SFGT存储阵列中的存储单元做擦除操作，其目的是将SFGT存储阵列的存储单元恢复到初始状态，以方便下一步数据的写入即编程操作。擦除操作破坏了存储单元中原来的数据，擦除完的SFGT存储阵列的存储单元处于保持的状态。还可以在SFGT存储阵列中进行编程操作，该过程是将灵敏放大器中的数据写入所选择的存储单元中。
需要说明的是，如图5所示，为一种灵敏放大器SA的内部结构图。其中，SA_core是SA工作的核心，主要作用就是进行信号放大。多路复用器(multiplexer，MUX)则是实现位线的选通。在图5中，还示出了位线(bit line，bl)。
需要说明的是，现有技术中，在读取SFGT存储阵列中的存储单元内所存储的 数据时，由于SFGT存储阵列的位线较长，导致从存储单元读取出的信号比较微弱，使得读取数据的过程耗时较长，读取数据的效率较低。
而在本申请中，可以控制灵敏放大器对第一目标位线的第一电压变化值进行放大，获得第一放大电压变化值；以及对第二目标位线的第二电压变化值进行放大，获得第二放大电压变化值。进而可以根据第一放大电压变化值以及第二放大电压变化值，读取目标真实半浮栅存储单元的目标存储值。即在读取SFGT存储阵列中的存储单元内所存储的数据时，可以通过灵敏放大器对从存储单元读取出的信号进行放大。可以减少读取数据的过程的耗时，提高读取数据的效率。
由以上技术方案可知，本申请实施例提供的一种读取数据的方法，获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值，其中，所述第一目标字线为所述真实半浮栅阵列所包含的多条第一字线中的一条第一字线；获取所述参考半浮栅阵列中第二目标位线的第二电压变化值；控制灵敏放大器对所述第一电压变化值进行放大，获得第一放大电压变化值，以及对所述第二电压变化值进行放大，获得第二放大电压变化值；根据所述第一放大电压变化值以及所述第二放大电压变化值，读取所述目标真实半浮栅存储单元的目标存储值。这样，可以控制灵敏放大器对第一目标位线的第一电压变化值进行放大，获得第一放大电压变化值；以及对第二目标位线的第二电压变化值进行放大，获得第二放大电压变化值。进而可以根据第一放大电压变化值以及第二放大电压变化值，读取目标真实半浮栅存储单元的目标存储值。即在读取SFGT存储阵列中的存储单元内所存储的数据时，可以通过灵敏放大器对从存储单元读取出的信号进行放大。可以减少读取数据的过程的耗时，提高读取数据的效率。
参见图6，图6是本申请提供的一种存储芯片的示意图，该存储芯片可以包括:SFGT存储阵列、列译码模块、行译码模块和逻辑控制模块；
所述逻辑控制模块分别通过所述列译码模块和所述行译码模块与所述SFGT存储阵列连接，用于根据访问指令对所述SFGT存储阵列进行以页为单位的写入和读取；
所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；
所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设置在所述第一位线和所述第一字线相交的位置；
所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。
本实施例中SFGT存储阵列可以采用如图1-图6任意一项所示实施例的SFGT存储阵列。
如图6所示，该存储芯片可以包括SFGT存储阵列、列译码模块(Col_dec)、行译码模块(Row_dec)和逻辑控制模块(Control logic)。逻辑控制模块可以分别通过列译码模块和行译码模块与SFGT存储阵列连接，用于根据访问指令对SFGT存储阵列进行以页为单位的写入和读取。SFGT存储阵列的结构已在前述实施例中进行详细描述，在此不再赘述。
可选的，所述存储芯片还包括电路模块，所述电路模块与所述列译码模块、所述行译码模块和所述逻辑控制模块连接，所述电路模块用于为所述列译码模块、所述行译码模块和所述逻辑控制模块提供电压。
如图6所示，存储芯片还可以包括电路模块(Generator)，电路模块可以与列译码模块、行译码模块和逻辑控制模块连接。电路模块用于为列译码模块、行译码模块和逻辑控制模块提供电压，generator模块为存储芯片提供了各种操作电压。
可选的，所述存储芯片还包括数据传输路径，所述数据传输路径与所述列译码模块和所述逻辑控制模块连接。
如图6所示，存储芯片还可以包括数据传输路径(Data path)，数据传输路径可以与列译码模块和逻辑控制模块连接。
可选的，所述存储芯片还包括地址输入接口，所述地址输入接口与所述行译码模块和所述逻辑控制模块连接。
如图6所示，存储芯片还可以包括地址输入接口(Add dec)，地址输入接口可以与行译码模块和逻辑控制模块连接。
可选的，所述存储芯片还包括外部接口命令译码电路，所述外部接口命令译码电路与所述逻辑控制模块连接。
如图6所示，存储芯片还可以包括外部接口命令译码电路(Command dec)，外部接口命令译码电路可以与逻辑控制模块连接。
可选的，所述存储芯片还包括输入输出接口，所述输入输出接口与所述数据传输路径连接。
如图6所示，存储芯片还可以包括输入输出接口(input/output，IO)，输入输出接口可以与数据传输路径连接。
需要说明的是，control logic就是存储芯片工作的控制中心，其主要为存储芯片的核提供各种逻辑与电压，存储芯片的核其实也是存储芯片的核心。如图7所示，为一种存储芯片的核的示意图。包括行译码模块(Row_dec)，列译码模块(Col_dec)与产生各种时序的控制信号的逻辑控制模块(Control logic)。在整个SFGT存储阵列中，里面包含字线的驱动，SA等模块。字线的驱动主要是提供驱动能力，让字线 处于最远端时不至于信号太弱，SA主要功能就是将小信号放大为全摆幅。Row_dec则是行译码模块，根据输入地址选择出相应的字线，进而开始读取数据操作。而Col_dec为列译码模块，对输入的列地址进行译码。
由以上技术方案可知，本申请实施例提供的一种存储芯片，该存储芯片可以通过灵敏放大器对从存储单元读取出的信号进行放大。可以减少读取数据的过程的耗时，提高读取数据的效率。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修该或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (16)

  1. 一种SFGT存储阵列，其中，所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；
    所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设置在所述第一位线和所述第一字线相交的位置；
    所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。
  2. 根据权利要求1所述的SFGT存储阵列，其中，所述参考半浮栅阵列包含多个参考半浮栅存储单元和参考字线，所述多条第二位线中的每条第二位线与所述参考字线相交设置，用于对所述参考半浮栅存储单元进行操作，所述参考半浮栅存储单元设置在所述第二位线和所述参考字线相交的位置。
  3. 根据权利要求2所述的SFGT存储阵列，其中，所述真实半浮栅阵列、所述参考半浮栅阵列和所述灵敏放大器一一对应。
  4. 根据权利要求2所述的SFGT存储阵列，其中，所述真实半浮栅阵列中的多条第一位线分别向所述真实半浮栅阵列两侧的第一参考半浮栅阵列和第二参考半浮栅阵列驱动。
  5. 根据权利要求4所述的SFGT存储阵列，其中，所述真实半浮栅阵列对应第一参考半浮栅阵列和第二参考半浮栅阵列；
    所述真实半浮栅阵列所包含的多条第一位线中的奇数序号第一位线与第一灵敏放大器的第一输入端连接，所述真实半浮栅阵列所包含的多条第一位线中的偶数序号第一位线与第二灵敏放大器的第一输入端连接；
    所述第一参考半浮栅阵列所包含的多条第二位线中的每条第二位线与所述第一灵敏放大器的第二输入端连接；
    所述第二参考半浮栅阵列所包含的多条第二位线中的每条第二位线与所述第二灵敏放大器的第二输入端连接。
  6. 一种存储芯片，其中，包括:
    SFGT存储阵列、列译码模块、行译码模块和逻辑控制模块；
    所述逻辑控制模块分别通过所述列译码模块和所述行译码模块与所述SFGT存储阵列连接，用于根据访问指令对所述SFGT存储阵列进行以页为单位的写入和读取；
    所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器；
    所述真实半浮栅阵列包含多个真实半浮栅存储单元、多条第一位线和多条第一字线，所述多条第一位线中的每条第一位线和所述多条第一字线中的每条第一字线相交设置，用于对所述真实半浮栅存储单元进行操作，所述多条第一位线中的每条第一位线与所述灵敏放大器的第一输入端连接，所述真实半浮栅存储单元设置在所述第一位线和所述第一字线相交的位置；
    所述参考半浮栅阵列包含多条第二位线，所述多条第二位线中的每条第二位线与所述灵敏放大器的第二输入端连接。
  7. 根据权利要求6所述的存储芯片，其中，所述存储芯片还包括电路模块，所述电路模块与所述列译码模块、所述行译码模块和所述逻辑控制模块连接，所述电路模块用于为所述列译码模块、所述行译码模块和所述逻辑控制模块提供电压。
  8. 根据权利要求6所述的存储芯片，其中，所述存储芯片还包括数据传输路径，所述数据传输路径与所述列译码模块和所述逻辑控制模块连接。
  9. 根据权利要求6所述的存储芯片，其中，所述存储芯片还包括地址输入接口，所述地址输入接口与所述行译码模块和所述逻辑控制模块连接。
  10. 根据权利要求6所述的存储芯片，其中，所述存储芯片还包括外部接口命令译码电路，所述外部接口命令译码电路与所述逻辑控制模块连接。
  11. 根据权利要求6所述的存储芯片，其中，所述存储芯片还包括输入输出接口，所述输入输出接口与数据传输路径连接。
  12. 一种读取数据的方法，其中，应用于SFGT存储阵列，所述SFGT存储阵列包含真实半浮栅阵列、参考半浮栅阵列和灵敏放大器，所述方法包括：
    获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值，其中，所述第一目标字线为所述真实半浮栅阵列所包含的多条第一字线中的一条第一字线；
    获取所述参考半浮栅阵列中第二目标位线的第二电压变化值；
    控制灵敏放大器对所述第一电压变化值进行放大，获得第一放大电压变化值，以及对所述第二电压变化值进行放大，获得第二放大电压变化值；
    根据所述第一放大电压变化值以及所述第二放大电压变化值，读取所述目标真实半浮栅存储单元的目标存储值。
  13. 根据权利要求12所述的方法，其中，所述获取所述参考半浮栅阵列中第二目标位线的第二电压变化值，包括：
    获取所述参考半浮栅阵列中的参考字线经过的参考半浮栅存储单元所对应的第二目标位线的第二电压变化值。
  14. 根据权利要求12所述的方法，其中，在所述获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值的步骤之前，所述方法还包括：
    接收读取数据命令；
    根据所述读取数据命令，选择所述第一目标字线以及所述参考字线；
    所述获取第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值，包括：
    在经过预设时间间隔之后，获取所述第一目标字线经过的目标真实半浮栅存储单元所对应的第一目标位线的第一电压变化值。
  15. 根据权利要求12所述的方法，其中，所述获取所述参考半浮栅阵列中第二目标位线的第二电压变化值，包括：
    从所述灵敏放大器内读取预先设置的所述第二电压变化值。
  16. 根据权利要求12至15中任一项所述的方法，其中，所述根据所述第一放大电压变化值以及所述第二放大电压变化值，读取所述目标真实半浮栅存储单元的目标存储值，包括：
    在所述第一放大电压变化值大于所述第二放大电压变化值的情况下，读取所述目标真实半浮栅存储单元的所述目标存储值为第一存储值；
    在所述第一放大电压变化值小于所述第二放大电压变化值的情况下，读取所述目标真实半浮栅存储单元的所述目标存储值为第二存储值，其中，所述第一存储值和所述第二存储值不同。
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