CN113506826A - Groove type silicon carbide transistor and preparation method thereof - Google Patents
Groove type silicon carbide transistor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention belongs to the technical field of semiconductors, and discloses a groove type silicon carbide transistor which comprises a silicon carbide semiconductor film, a base region doping region, a source region doping region, a gate groove, an insulating medium film I, an insulating medium film II, a gate electrode, a base region conductive film, an isolation medium film, a source electrode and a drain electrode. The invention etches the edge of the main junction into a mesa shape, changes the appearance of the junction edge in the device, thereby relieving the electric field concentration near the junction edge and improving the reverse breakdown voltage, the voltage resistance and the reliability of the device. When the gate oxide layer is prepared, firstly, polycrystalline silicon or amorphous silicon is deposited in the gate groove, and then, the polycrystalline silicon or the amorphous silicon is etched and oxidized, so that the thickness of the gate oxide layer at the bottom of the groove is enhanced, the gate oxide layer is prevented from being broken down, and the reliability of the transistor is further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a groove type silicon carbide transistor and a manufacturing method thereof.
Background
With the rapid development of modern electronic technology and its application, power devices have been greatly developed in structure and performance, and especially, power devices represented by silicon (Si) have promoted the rapid development of photoelectronic and microelectronic technologies. However, with the emergence and popularization of technologies such as super junctions, trenches, insulated gate bipolar transistors and the like, the performance of silicon-based power devices has approached the limit of materials, and in many cases, the silicon-based power devices can only work in an environment lower than 250 ℃, especially when the environment simultaneously exists in high temperature, high power, high frequency, extremely strong radiation and the like, the traditional silicon-based power devices cannot meet the working requirements, and each small improvement of the performance of the silicon-based power devices needs to pay a huge cost, which prompts people to find a novel semiconductor material, namely silicon carbide (SiC), with more excellent performance.
The silicon carbide as a third-generation semiconductor material has the outstanding advantages of large forbidden band width, high breakdown field strength, high thermal conductivity, high carrier saturation mobility, strong irradiation resistance and the like, and is particularly suitable for severe application environments such as high temperature, high pressure, large current, high frequency, high irradiation and the like related to modern power electronic systems. In the aspects of design, development and application technology of the silicon carbide power device, compared with a silicon-based power device with the same power voltage level, the on-resistance and the switching loss of the silicon carbide power device are greatly reduced, so that the silicon carbide power device is more suitable for working scenes under the conditions of high working frequency and high temperature. Although silicon carbide power device samples of various voltage classes are emerging, they are still limited by epitaxial material quality and surface treatment processes. With the continuous maturity of key technologies such as epitaxial technology, surface treatment, ion implantation and the like, the bulk defects of the silicon carbide epitaxial material are improved to a great extent, and the surface mobility is gradually improved. For example, patent with publication number CN111276545A discloses a novel trench type silicon carbide transistor and a manufacturing method thereof, which utilizes means such as etching to etch the edge of a main junction into a double-mesa shape on the basis of a MOSFET or an IGBT, and the double-mesa shape is respectively a second conductive type well region mesa and an epitaxial layer mesa, so as to achieve the purpose of changing the morphology of the junction edge in a device, thereby improving the electric field distribution of the surface near the junction, relieving the electric field concentration near the junction edge, improving the reverse breakdown voltage of the device, and improving the voltage resistance and the reliability of the device. However, the patent publication No. CN111276545A discloses that the trench on the substrate is a vertical trench, and the vertical trench type sic transistor is advantageous for high current and high integration devices, but the conventional vertical trench type sic transistor still has the following defects:
(1) because the silicon carbide material has a large forbidden band width, compared with the traditional semiconductor devices such as silicon materials and the like, the inversion layer can be formed only by needing larger gate voltage, the carrier concentration in the inversion layer of the silicon carbide device under the same gate voltage is generally smaller than that of the traditional semiconductor devices, and the excessive gate voltage exceeds the bearing range of the gate oxide layer to cause early breakdown.
(2) The low channel mobility in the vertical channel results in a large channel resistance, reducing the influence of emitter injection effects on the conductance modulation effect in the drift region.
(3) The double-mesa structure has high requirements on processing, complex processing technology and low reliability.
Based on the analysis, the problems that a channel inversion layer of the existing vertical type groove type silicon carbide transistor is difficult to form, channel resistance is overlarge, a gate oxide layer is easy to break down, a processing process is complex, process reliability is poor and the like generally exist. Therefore, there is a need in the art to provide a new trench-type sic transistor and a method for fabricating the same to eliminate the drawbacks of the prior art.
Disclosure of Invention
The invention aims to provide a groove type silicon carbide transistor, and the technical scheme adopted for realizing the aim of the invention is as follows:
a groove type silicon carbide transistor comprises a silicon carbide film, wherein the silicon carbide film sequentially comprises a substrate, a buffer layer and an epitaxial film from bottom to top, and the epitaxial film is in a convex shape;
a base region doping region in a shape like a Chinese character 'ji' is arranged along the top outline of the epitaxial thin film, and a source region doping region is arranged on the upper surface of a middle boss of the base region doping region;
the gate trench penetrates through the base region doping region and the source region doping region, extends into the epitaxial film, and is positioned above the platform bottoms on two sides of the epitaxial film boss in the vertical direction;
the bottom of the gate trench is provided with a concave insulating dielectric film I, the side wall of the gate trench is provided with an insulating dielectric film II, and the gate trench is filled with a T-shaped gate electrode matched with the concave bottom insulating dielectric film;
base region conductive films are further arranged on the platforms on the two sides of the boss of the base region doping region;
the top of the gate electrode, the source region doped region and the base region conductive film is also provided with an isolation medium thin layer and a source electrode from bottom to top;
and the lower surface of the substrate is also provided with a drain electrode.
The silicon carbide film in the invention is a film in the prior art and mainly comprises a substrate, a buffer layer and an epitaxial film. Wherein, the epitaxial film is a multilayer epitaxial film or a single-layer epitaxial film. The silicon carbide film is 4H-SiC or 6H-SiC or 3C-SiC, 4H-SiC is preferred in the invention, and the mobility of the crystal face of the 4H-SiC material is higher than that of the 3C-SiC material and the 6H-SiC material, so that the surface mobility can be further improved, and the body defect of the transistor can be reduced. The silicon carbide film has an overall thickness of 50 μm to 800. mu.m, preferably 500. mu.m. The thickness of the substrate is 10-300 mu m, the thickness of the buffer layer is 20-100 mu m, the number of layers of the epitaxial thin film is 2-100, and the thickness of each layer of the epitaxial thin film is 20-200 mu m. The thickness of the base region doping region and the source region doping region is 20-100 mu m.
Another objective of the present invention is to provide a method for manufacturing a trench-type silicon carbide transistor, and the technical solution adopted to achieve the another objective of the present invention is:
a manufacturing method of a groove type silicon carbide transistor specifically comprises the following steps:
step S1, sequentially forming a first base region doping area and a source region doping area on the upper surface of the epitaxial film of the silicon carbide film through secondary epitaxy or ion implantation;
step S2, forming a graphical mask layer I on the upper surface of the source region doping region through medium film deposition, photoetching and etching, and forming base region channels on two sides of the upper end of the sample through etching to enable the sample to be in a convex shape integrally;
step S3, forming a second base region doping region along the outline of the two sides of the epitaxial film through an ion implantation process;
step S4, removing the graphical mask layer I, carrying out high-temperature annealing on the sample, and activating the injected impurities;
step S5, forming a graphical mask layer II on the upper surface of the sample again through medium film deposition, photoetching and etching, forming a gate groove in the middle of the upper end of the sample through etching, and enabling the bottom of the gate groove to be above the bottoms of the platforms on two sides of the epitaxial film boss in the vertical direction;
step S6, depositing a layer of semiconductor film on the bottom and the side wall of the gate trench and the surface of the mask layer II;
a step S7 of oxidizing the semiconductor film deposited in the step S6 to form an oxide film;
step S8, coating photoresist on the outer surface of the oxide film, and filling the photoresist in the gate trench;
step S9, etching the photoresist in the step S8, and only reserving all the photoresist in the gate groove;
step S10, removing all mask layers II on two sides of the gate trench, oxide films on the upper surfaces of the mask layers II and oxide films on the upper parts of the side walls of the gate trench by adopting an etching or corrosion process, only keeping the oxide films on the lower parts of the side walls of the gate trench and the bottom of the gate trench to obtain an insulating medium film I, and then removing residual photoresist;
step S11, oxidizing the side wall of the groove to obtain an insulating medium film II, and then depositing a grid electrode film in the grid groove to form a grid electrode; depositing a base conductive film on the upper surface of the base channel; then depositing an isolation medium film on the top of the gate electrode, the source region doped region and the conductive film;
and step S12, photoetching and etching the sample to form ohmic contact openings of the source electrode and the base electrode, forming ohmic contact and pressure welding source electrodes on the upper surfaces of the base region doping area and the source region doping area, and forming ohmic contact and pressure welding drain electrodes on the back surface of the lower surface of the substrate.
The invention has the beneficial effects that:
(1) when the gate oxide layer is prepared, the polycrystalline silicon or the amorphous silicon is firstly deposited in the gate groove, and then the polycrystalline silicon or the amorphous silicon is etched and oxidized, so that the thickness of the gate oxide layer at the bottom of the groove is enhanced, the gate oxide layer is prevented from being broken down, and the reliability of the transistor is further improved. The critical breakdown electric field intensity of the silicon carbide is high, the electric field intensity born by the gate oxide layer of the groove type silicon carbide transistor at the corner of the groove is often very high, and when the electric field intensity exceeds the range born by the oxide layer, destructive failure of a device is easily caused.
(2) The base region doping region and the source region doping region are formed through an epitaxial process, damage to the silicon carbide crystal lattice caused by high-energy ion implantation is avoided, the grid channel is located in the doping region, the method can also avoid the ion implantation of the grid channel region, reduce the damage to the grid oxide layer caused by ions, and ensure the reliability of the device.
(3) The invention utilizes means such as etching and the like to etch the edge of the main junction into a mesa shape, changes the appearance of the junction edge in the device, thereby improving the electric field distribution of the surface near the junction, relieving the electric field concentration near the junction edge, and improving the reverse breakdown voltage of the device, the voltage resistance of the device and the reliability of the device.
(4) The processing technology of the invention is simple, easy to realize and convenient for large-scale production.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of the process of step S1 according to the present invention.
Fig. 2 is a schematic diagram of a structure after step S1 is completed.
Fig. 3 is a schematic diagram of a structure after step S3 is completed.
Fig. 4 is a schematic diagram of a structure after step S5 is completed.
Fig. 5 is a schematic diagram of a structure after step S6 is completed.
Fig. 6 is a schematic diagram of a structure after step S7 is completed.
Fig. 7 is a schematic diagram of a structure after step S8 is completed.
Fig. 8 is a schematic diagram of a structure after step S9 is completed.
Fig. 9 is a schematic view of a structure of the process of step S10 according to the present invention.
Fig. 10 is a schematic view of a structure of the process of step S11 according to the present invention.
Fig. 11 is a schematic diagram of a structure after step S11 is completed.
Fig. 12 is a schematic diagram of a structure after step S12 is completed.
In the figure: 1. a silicon carbide film; 101. a substrate; 102. a buffer layer; 103. an epitaxial thin film; 2. a base region doping region; 201. a first base region doping region; 202. a second base region doping region; 3. a source region doped region; 4. a gate trench; 5. an insulating dielectric film I; 6. an insulating dielectric film II; 7. a gate electrode; 8. a base region conductive film; 9. an isolation dielectric film; 10. a source electrode; 11. a drain electrode; 12. a mask layer I; 13. a base region channel; 14. a mask layer II; 15. a semiconductor thin film; 16. oxidizing the thin film; 17. and (7) photoresist.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiments and drawings are merely reference embodiments for describing the present invention, and the present invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. For the purpose of further illustrating the invention, the dimensions of some of the elements in the figures may be exaggerated and not drawn on scale. The dimensions and relative dimensions do not correspond to actual reductions in practice of the invention. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Furthermore, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. It is to be noticed that the term 'comprising', used in the claims, should not be interpreted as being restricted to the means listed thereafter, but it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, parameters, steps or components, but does not preclude the presence or addition of one or more other features, parameters, steps or components, or groups thereof.
Example 1
In this embodiment, the trench type silicon carbide transistor is a MOSFET device. The doping types of the substrate 101, the buffer layer 102, the epitaxial thin film 103 and the source region doping region 3 are all a first conductivity type, and the doping type of the base region doping region 2 is a second conductivity type, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The doping concentration is 1 x 1014～5×1021cm-3。
A groove type silicon carbide transistor comprises a silicon carbide film 1, wherein the silicon carbide film 1 sequentially comprises a substrate 101, a buffer layer 102 and an epitaxial film 103 from bottom to top, and the epitaxial film 103 is in a convex shape; a base region doping region 2 shaped like a Chinese character 'ji' is arranged along the top outline of the epitaxial thin film 103, and a source region doping region 3 is arranged on the upper surface of a middle boss of the base region doping region 2; the epitaxial thin film structure further comprises a gate trench 4 penetrating through the base region doping region 2 and the source region doping region 3, the gate trench 4 extends into the epitaxial thin film 103, and the bottom of the gate trench 4 is located above the platform bottoms on two sides of the lug boss of the epitaxial thin film 103 in the vertical direction; the bottom of the gate trench 4 is provided with a concave insulating dielectric film I5, the side wall of the gate trench 4 is provided with an insulating dielectric film II 6, and the gate trench 4 is filled with a T-shaped gate electrode 7 matched with the concave bottom insulating dielectric film; base region conductive films 8 are further arranged on the platforms on the two sides of the boss of the base region doping region 2; the top parts of the gate electrode 7, the source region doped region 3 and the base region conductive film 8 are also provided with an isolation medium thin layer and a source electrode 10 from bottom to top; the lower surface of the substrate 101 is also provided with a drain electrode 11.
The manufacturing method of the groove type silicon carbide transistor comprises the following steps:
step S1, sequentially forming a first base region doping region 201 and a source region doping region 3 on the upper surface of the epitaxial film 103 of the silicon carbide film 1 by secondary epitaxy or ion implantation, as shown in fig. 1 and 2 specifically;
step S2, forming a patterned mask layer I12 on the upper surface of the source region doped region 3 through dielectric film deposition, photoetching and etching, and forming base region channels 13 on two sides of the upper end of the sample through etching to enable the sample to be in a convex shape integrally;
the dielectric film is a single-layer film or a composite layer film formed by any combination of silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon and common metal (Ni, Al, W, Ti or any alloy compound thereof), and the thickness of the film is 10-100 um.
In the photoetching technology and the wet method or dry etching technology, the pattern of the mask plate is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 1-200 mu m, the etching depth is 1-200 mu m, and the width of the table top area is 1-200 mu m; wherein the length of the parallel long strip-shaped patterns and the interdigital patterns is 1 mu m-20 cm.
Step S3, forming a second base doping region 202 by an ion implantation process along the profile of the two sides of the epitaxial thin film 103, as shown in fig. 3 specifically;
by adopting an ion mode, the method can accurately control the aspects of implantation dosage, implantation angle, implantation depth, transverse diffusion and the like, overcomes the limitation of the conventional process, improves the integration level, the starting speed, the yield and the service life of the circuit, and reduces the costCost and power consumption are reduced. The ion implantation material is aluminum or boron, and the energy of the ion implantation is 10 Kev-15 Mev. Preferably, the energy of the ion implantation is 50 Kev-1 Mev; more preferably, the energy of the ion implantation is preferably 200 Kev. The temperature of the ion implantation is 22-1000 ℃. Preferably, the temperature of the ion implantation is 150-800 ℃; more preferably, the temperature of the ion implantation is 450 ℃. The dosage of the ion implantation is 1 x 1010～5×1016cm-2. Preferably, the ion implantation is performed at a dose; 2X 1011～5×1015cm-2。
Step S4, removing the graphical mask layer I12, carrying out high-temperature annealing on the sample, and activating the injected impurities;
the high-temperature annealing can activate interstitial atoms to move to lattice positions, repair lattice damage and defects and eliminate residual stress generated in the ion implantation process. The annealing mode adopts high-temperature furnace annealing, rapid annealing or rapid thermal annealing (RTP) because the speed is higher. Rapid annealing is preferred, and the advantages of better uniformity among chips, minimized impurity diffusion and the like can be realized. The annealing atmosphere is vacuum, nitrogen or argon atmosphere, the annealing temperature is 300-3000 ℃, and the annealing time is 0.1 min-2 h. Preferably, the annealing temperature is 600 ℃ to 1000 ℃; more preferably, the annealing temperature is 800 ℃.
Step S5, forming a patterned mask layer II 14 on the upper surface of the sample again through medium film deposition, photoetching and etching, forming a gate trench 4 in the middle of the upper end of the sample through etching, wherein in the vertical direction, the bottom of the gate trench 4 is above the bottom of the platform on both sides of the lug boss of the epitaxial film 103, as shown in FIG. 4 specifically;
the dielectric film is a single-layer film or a composite layer film formed by any combination of silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon and common metal (Ni, Al, W, Ti or any alloy compound thereof). The thickness of the film is 10um-100 um.
The etching is a reactive ion etching technology or an inductive coupling plasma etching technology or a combination thereof; etching gases include, but are not limited to, SF6、CF4、O2HBr, etc. in any combinationAn atmosphere. The mesa pattern is an interdigital structure or a parallel long strip-shaped or polygonal mesa or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal mesa, the width of a window area is 1-200 mu m, the etching depth is 1-200 mu m, and the width of the mesa area is 1-200 mu m; wherein the length of the parallel long strip-shaped patterns and the interdigital patterns is 1 mu m-20 cm.
Step S6, depositing a semiconductor film 15 on the bottom and the sidewall of the gate trench 4 and the surface of the mask layer ii 14, as shown in fig. 5;
the semiconductor film is a polycrystalline silicon or amorphous silicon or monocrystalline silicon single layer or composite film thereof, and the thickness of the film is 10-200 mu m.
Step S7, oxidizing the semiconductor film 15 deposited in step S6 to form an oxide film 16, as shown in fig. 6;
step S8, coating a photoresist 17 on the outer surface of the oxide film 16, and filling the photoresist 17 into the gate trench 4, as shown in fig. 7;
the photoresist is common photoresist and can be positive photoresist or negative photoresist.
Step S9, etching the photoresist 17 in step S8, and only remaining all the photoresist 17 in the gate trench 4, as shown in fig. 8 specifically;
step S10, removing all the mask layer ii 14 on both sides of the gate trench 4, the oxide film 16 on the upper surface of the mask layer ii 14, and the oxide film 16 on the upper portion of the sidewall of the gate trench 4 by using an etching or etching process, and only remaining the oxide film 16 on the lower portion of the sidewall of the gate trench 4 and the bottom of the gate trench 4 to obtain an insulating dielectric film i 5, as shown in fig. 9 specifically; then removing the residual photoresist 17;
the etching is a reactive ion etching technology or an inductive coupling plasma etching technology or a combination thereof; etching gases include, but are not limited to, SF6、CF4、O2HBr and the like in any combination; the corrosion is hydrofluoric acid or a mixed solution of hydrofluoric acid, hydrogen peroxide and deionized water in any proportion.
Step S11, oxidizing the side wall of the groove to obtain an insulating medium film II 6, as shown in FIG. 10; then depositing a gate film in the gate trench 4 to form a gate electrode 7; depositing a base conductive film 8 on the upper surface of the base channel 13; then depositing an isolation medium film on the top of the gate electrode 7, the source region doped region 3 and the conductive film, as shown in fig. 11;
the grid film is a single-layer film of highly doped polysilicon or common metals (Al, Ni, Ti, W, Ag and Au) or a composite film of any combination of the single-layer film and the composite film, and the thickness of the film is 10-200 mu m.
The isolation dielectric film 9 is a single-layer or multi-layer composite film of insulating silicon dioxide, silicon nitride, polysilicon, amorphous silicon, phosphosilicate glass, borosilicate glass, TEOS and the like.
Step S12, performing photolithography and etching on the sample to form ohmic contact openings for the source and the base, forming ohmic contacts and bonding source electrodes 10 on the upper surfaces of the base doping region 2 and the source doping region 3, and forming ohmic contacts and bonding drain electrodes 11 on the back surface of the lower surface of the substrate 101, as shown in fig. 12.
The ohmic contact, the source electrode and the drain electrode are all metal or conductive materials, and the thickness of the film is 0.001-100 um. Wherein, the metal can be a single-layer film or a plurality of composite films of Ti, Ni, Al, Cu, Au, Ag, Mo, W, TiW, TiC, Fe, Cr and the like.
The ohmic contact may be achieved by a high temperature process including Rapid Thermal Annealing (RTA) or Laser Annealing (LA) or other high temperature furnace, wherein the atmosphere in the process is a vacuum atmosphere or an inert gas atmosphere such as nitrogen, argon, or the like.
Example 2
In this embodiment, the trench type silicon carbide transistor of the present invention is a MOSFET device. The doping types of the substrate 101, the buffer layer 102, the epitaxial thin film 103 and the source region doping region 3 are all a first conductivity type, and the doping type of the base region doping region 2 is a second conductivity type, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The doping concentration is 1 x 1014～5×1021cm-3. In this embodiment, the trench type sic transistor is the same as that in embodiment 1 in both structure and processing steps, only in that there is nothing but a doping type of each portion.
Example 3
In the present embodiment, the trench type silicon carbide transistor of the present invention is an IGBT device. The doping types of the buffer layer 102, the epitaxial thin film 103 and the source region doping region 3 are all first conductivity types; the doping types of the substrate 101 and the base region doping region 2 are both a second conduction type, wherein the first conduction type is an N type, and the second conduction type is a P type. The doping concentration is 1 x 1014～5×1021cm-3. In this embodiment, the trench type sic transistor is the same as that in embodiment 1 in both structure and processing steps, only in that there is nothing but a doping type of each portion.
Example 4
In the present embodiment, the trench type silicon carbide transistor of the present invention is an IGBT device. The doping types of the buffer layer 102, the epitaxial thin film 103 and the source region doping region 3 are all first conductivity types; the doping types of the substrate 101 and the base region doping region 2 are both a second conductivity type, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The doping concentration is 1 x 1014～5×1021cm-3. In this embodiment, the trench type sic transistor is the same as that in embodiment 1 in both structure and processing steps, only in that there is nothing but a doping type of each portion.
The above-mentioned embodiments are further described in detail for the purpose of illustrating the invention, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the invention and are not intended to limit the invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit of the invention should be included in the scope of the invention.
Claims (10)
1. The utility model provides a trench type silicon carbide transistor, includes silicon carbide film (1), silicon carbide film (1) includes substrate (101), buffer layer (102) and epitaxial film (103) from bottom to top in proper order, its characterized in that:
the epitaxial film (103) is in a shape of a Chinese character 'tu';
a base region doping region (2) shaped like a Chinese character 'ji' is arranged along the top outline of the epitaxial thin film (103), and a source region doping region (3) is arranged on the upper surface of a middle boss of the base region doping region (2);
the epitaxial thin film transistor also comprises a gate trench (4) penetrating through the base region doping region (2) and the source region doping region (3), and the gate trench (4) extends into the epitaxial thin film (103);
a concave-shaped insulating medium film I (5) is arranged at the bottom of the gate trench (4), an insulating medium film II (6) is arranged on the side wall of the gate trench (4), and a T-shaped gate electrode (7) matched with the concave-shaped bottom insulating medium film is filled in the gate trench (4);
base region conductive films (8) are also arranged on the platforms on the two sides of the boss of the base region doping region (2);
the tops of the gate electrode (7), the source region doped region (3) and the base region conductive film (8) are also provided with an isolation dielectric film (9) and a source electrode (10) from bottom to top;
the lower surface of the substrate (101) is also provided with a drain electrode (11).
2. The trench silicon carbide transistor of claim 1, wherein:
the trench type silicon carbide transistor is an MOSFET device, the doping types of the substrate (101), the buffer layer (102), the epitaxial thin film (103) and the source region doping region (3) are all a first conduction type, the doping type of the base region doping region (2) is a second conduction type, and the first conduction type and the second conduction type are opposite in doping type; wherein, the doping type is N type or P type, if the doping type is N type, the doping impurity is nitrogen or phosphorus; if P-type doping is adopted, the doping impurity is aluminum or boron, and the doping concentration is 1 multiplied by 1014～5×1021cm-3。
3. The trench silicon carbide transistor of claim 1, wherein:
the trench type silicon carbide transistor is an IGBT device, and the doping types of the buffer layer (102), the epitaxial thin film (103) and the source region doping region (3) are all the first conduction type; the doping types of the substrate (101) and the base region doping region (2) are both secondThe conductive type is opposite to the doping type of the second conductive type; wherein, the doping type is N type or P type, if the doping type is N type, the doping impurity is nitrogen or phosphorus; if P-type doping is adopted, the doping impurity is aluminum or boron, and the doping concentration is 1 multiplied by 1014～5×1021cm-3。
4. The trench type silicon carbide transistor according to any one of claims 1 to 3, further comprising a method for manufacturing the trench type silicon carbide transistor, wherein the method comprises the following steps:
step S1, sequentially forming a first base region doping region (201) and a source region doping region (3) on the upper surface of the epitaxial film (103) of the silicon carbide film (1) through secondary epitaxy or ion implantation;
step S2, forming a graphical mask layer I (12) on the upper surface of the source region doped region (3) through medium film deposition, photoetching and etching, and forming base region channels (13) on two sides of the upper end of the sample through etching to enable the sample to be in a convex shape integrally;
step S3, forming a second base region doping region (202) along the outline of the two sides of the epitaxial film (103) through an ion implantation process;
step S4, removing the patterned mask layer I (12), annealing the sample at high temperature, and activating the injected impurities;
step S5, forming a patterned mask layer II (14) on the upper surface of the sample again through medium film deposition, photoetching and etching, and forming a gate trench (4) in the middle of the upper end of the sample through etching;
step S6, depositing a semiconductor film (15) on the bottom and the side wall of the gate trench (4) and the surface of the mask layer II (14);
a step S7 of oxidizing the semiconductor thin film (15) deposited in the step S6 to form an oxide thin film (16);
step S8, coating photoresist (17) on the outer surface of the oxide film (16), and filling the photoresist (17) into the gate trench (4);
step S9, etching the photoresist (17) in the step S8, and only reserving all the photoresist (17) in the gate trench (4);
step S10, removing all mask layers II (14) on two sides of the gate trench (4), the oxide film (16) on the upper surface of the mask layers II (14) and the oxide film (16) on the upper part of the side wall of the gate trench (4) by adopting an etching or corrosion process, only keeping the oxide film (16) on the lower part of the side wall of the gate trench (4) and the bottom of the gate trench (4) to obtain an insulating medium film I (5), and then removing the residual photoresist (17);
step S11, oxidizing the side wall of the groove to obtain an insulating medium film II (6), and then depositing a grid electrode film in the grid groove (4) to form a grid electrode (7); depositing a base conductive film (8) on the upper surface of the base channel (13); then, depositing an isolation medium film on the top of the gate electrode (7), the source region doping region (3) and the conductive film;
and step S12, photoetching and etching the sample to form ohmic contact openings of a source electrode and a base electrode, forming ohmic contact and pressure welding source electrodes (10) on the upper surfaces of the base region doping region (2) and the source region doping region (3), and forming ohmic contact and pressure welding drain electrodes (11) on the back surface of the lower surface of the substrate (101).
5. The method of manufacturing a trench type silicon carbide transistor according to claim 4,
in steps S1 and S3, the ion implantation material is N, P, B or Al, the energy of the ion implantation is 10 Kev-15 Mev, the temperature of the ion implantation is 22-1000 ℃, and the dose of the ion implantation is 1 x 1010～5×1016cm-2。
6. The method of manufacturing a trench type silicon carbide transistor according to claim 4,
the dielectric film in step S2 and step S5 is a single-layer film or a composite-layer film of any combination of silicon dioxide, silicon nitride, polysilicon, amorphous silicon or metal.
7. The method of manufacturing a trench type silicon carbide transistor according to claim 4,
in step S4, the annealing atmosphere is vacuum, nitrogen or argon, the annealing temperature is 300 to 3000 ℃, and the annealing time is 0.1min to 1000 hours.
8. The method of manufacturing a trench type silicon carbide transistor according to claim 4,
in step S5, the etching is a reactive ion etching technique or an inductively coupled plasma etching technique or a combination thereof; the etching gas is SF6、CF4、O2Or more than one species of HBr.
9. The method of manufacturing a trench type silicon carbide transistor according to claim 4,
in step S6, the semiconductor thin film (15) is one or more of polycrystalline silicon, amorphous silicon, and single crystal silicon.
10. The method of manufacturing a trench type silicon carbide transistor according to claim 4,
in step S12, the ohmic contact, the source electrode (10), and the drain electrode (11) are all metal or conductive material.
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