CN113643970A - Manufacturing method of silicon carbide semiconductor device - Google Patents

Manufacturing method of silicon carbide semiconductor device Download PDF

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Publication number
CN113643970A
CN113643970A CN202110908129.2A CN202110908129A CN113643970A CN 113643970 A CN113643970 A CN 113643970A CN 202110908129 A CN202110908129 A CN 202110908129A CN 113643970 A CN113643970 A CN 113643970A
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silicon carbide
epitaxial
semiconductor device
epitaxial layer
manufacturing
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何志
郑柳
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Chongqing Weitesen Electronic Technology Co ltd
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Chongqing Weitesen Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices

Abstract

The invention belongs to the technical field of semiconductors, and particularly discloses a manufacturing method of a silicon carbide semiconductor device, which comprises the following steps: s1, performing epitaxy on the surface of the silicon carbide substrate by adopting an epitaxy process to obtain a buffer layer and an epitaxial layer in sequence; s2, sequentially depositing a dielectric film and photoetching on the epitaxial layer to form a patterned first mask layer, and then forming a gate trench through etching; s3, carrying out epitaxial growth again on the surface of the sample epitaxial layer obtained in the step S2 to form a gate doped region; and S4, removing the redundant epitaxial film on the surface of the epitaxial layer by adopting chemical mechanical polishing, and flattening the surface of the sample. The invention adopts the outer etching process and the process of combining secondary epitaxy and surface planarization, thus realizing the preparation of various silicon carbide device structures; and the preparation process is simple, the practicability is strong, and the method is suitable for large-scale production.

Description

Manufacturing method of silicon carbide semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a silicon carbide semiconductor device.
Background
The power semiconductor device is a core element of a power electronic circuit, the traditional power semiconductor device is dominated by silicon, with the development of science and technology, people have a further improvement on the period of efficient energy conversion, higher requirements are put on the performance of power electronic technology, particularly power electronic devices, and a wide-bandgap semiconductor device represented by silicon carbide is produced.
With the continuous improvement of the quality of silicon carbide, the preparation process of the silicon carbide device is continuously developed, and the performance of the silicon carbide device is influenced by the processing process. If the doping concentration is reduced, the withstand voltage is increased, the thickness of the epitaxial layer is increased, and the withstand voltage is also increased. In order to coordinate the relationship between the performance of the semiconductor device and the processing parameters, the prior art is usually customized for the processing parameters of a certain silicon carbide semiconductor device, the processing method is not suitable for being transferred to other types of silicon carbide semiconductor devices, and the existing silicon carbide semiconductor device processing method has poor stability and repeatability and cannot be used for large-scale production. Accordingly, there is a need in the art for a method of fabricating a silicon carbide semiconductor device that obviates the drawbacks and limitations of the related art.
Disclosure of Invention
The invention aims to provide a manufacturing method of a silicon carbide semiconductor device, which is suitable for different types of silicon carbide semiconductor devices, has simple preparation process and strong practicability and is suitable for large-scale production.
The technical scheme for realizing the purpose of the invention is as follows:
a method for manufacturing a silicon carbide semiconductor device includes the steps of:
s1, performing epitaxy on the surface of the silicon carbide substrate by adopting an epitaxy process to obtain a buffer layer and an epitaxial layer in sequence;
s2, sequentially depositing a dielectric film and photoetching on the epitaxial layer to form a patterned first mask layer, and then forming a gate trench through etching;
s3, carrying out epitaxial growth again on the surface of the sample epitaxial layer obtained in the step S2 to form a gate doped region;
and S4, removing the redundant epitaxial film on the surface of the epitaxial layer by adopting chemical mechanical polishing, and flattening the surface of the sample.
The silicon carbide semiconductor device prepared by the invention is not a processing step of a complete power device, but a preorder processing step of a common power device, and is suitable for basic processing of common different types of power devices. On the basis of the manufacturing process, the silicon carbide sample can be processed and manufactured into various planar or groove type or super junction structure silicon carbide diodes, JFETs, MOSFETs, IGBTs and other devices.
The invention has the beneficial effects that:
1. the invention adopts the outer etching process and the process of combining secondary epitaxy and surface planarization, thereby realizing the preparation of various silicon carbide device structures.
2. The preparation method is simple in preparation process, strong in practicability and suitable for large-scale production.
3. The manufacturing method of the invention can coordinate each processing requirement of the silicon carbide semiconductor device and realize the optimization of the performance of the silicon carbide semiconductor device to the maximum extent.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a structure of the present invention after step S1 is completed;
FIG. 2 is a schematic diagram of a structure after step S2 according to the present invention is completed;
FIG. 3 is a schematic diagram of a structure after step S3 according to the present invention is completed;
FIG. 4 is a schematic diagram illustrating a structure of the present invention after step S4 is completed;
FIG. 5 is a schematic structural diagram of the embodiment 1 of the present invention after step S5 is completed;
fig. 6 is a schematic structural diagram after step S6 in embodiment 2 of the present invention is completed;
fig. 7 is a schematic structural diagram after step S8 in embodiment 3 of the present invention is completed;
fig. 8 is a schematic structural view of a conventional planar SiC MOSFET device;
fig. 9 is a schematic view of a structure of a conventional trench type SiC MOSFET device;
FIG. 10 is a schematic structural view of a SiC semiconductor device obtained by the production method of the present invention;
FIG. 11 is a simulated comparison of the devices of FIGS. 8-10;
fig. 12 is a comparison graph of another simulation of the devices shown in fig. 8-10.
In the figure: 1. a substrate; 2. a buffer layer; 3. an epitaxial layer; 4. a gate trench; 5. a gate doped region; 6. a second mask layer; 7. a source region doped region; 8. an ohmic contact region; 9. an isolation dielectric film; 10. a first pressure welding electrode; 11. and a second bonding electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A method for manufacturing a silicon carbide semiconductor device includes the steps of:
s1, performing epitaxy on the surface of the silicon carbide substrate 1 by adopting an epitaxy process to obtain a buffer layer 2 and an epitaxial layer 3 in sequence;
s2, sequentially depositing a dielectric film and photoetching on the epitaxial layer 3 to form a patterned first mask layer, and then forming a gate trench 4 by etching;
s3, carrying out epitaxial growth again on the surface of the sample epitaxial layer 3 obtained in the step S2 to form a gate doped region 5;
and S4, removing the redundant epitaxial film on the surface of the epitaxial layer 3 by adopting chemical mechanical polishing, and flattening the surface of the sample.
The buffer layer 2 and the epitaxial layer 3 prepared by the epitaxial growth method can grow a layer of crystal with the same crystal orientation as the substrate 1 and with good lattice structure integrity and different resistivity and thickness on the silicon carbide substrate 1 with a certain crystal orientation. Compared with a silicon-based power device with the same power voltage grade, the silicon carbide power device has the advantages that the on-resistance and the switching loss are greatly reduced, and therefore the silicon carbide power device is more suitable for working scenes under the conditions of high working frequency and high temperature. The silicon carbide material in the invention is 4H-SiC or 6H-SiC or 3C-SiC, 4H-SiC is preferred in the invention, because the mobility of the crystal face of the 4H-SiC material is higher than that of the 3C-SiC material and the 6H-SiC material, the surface mobility can be further improved, and the body defect of the transistor is reduced. The thickness of the substrate 1 is 20-150 mu m, the thickness of the buffer layer 2 is 30-80 mu m, the number of layers of the epitaxial thin film is 5-80, and the thickness of each layer of the epitaxial thin film is 30-180 mu m.
In the photoetching and etching technology, the adopted mask plate pattern is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combination pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 0.01-200 mu m, the etching depth is 0.01-200 mu m, and the width of the table top area is 0.01-200 mu m; wherein the length of the parallel long strip-shaped patterns and the interdigital patterns is 0.01 mu m-20 cm. The shape or other size parameters of the mask plate are selected according to actual conditions.
When the size of a semiconductor electronic device is small enough, global planarization is required, and the traditional planarization technology such as a heat flow method, a rotating glass method, an etch back method, an electron surround resonance method, low-pressure CVD, plasma enhanced CVD and the like belongs to a local planarization process, so that the global planarization cannot be realized. The Chemical Mechanical Polishing (CMP) technique not only satisfies the requirements of silicon wafer patterning in terms of processability and speed, but also enables global planarization. The chemical polishing solution used in the present invention is a polishing solution in the prior art, such as the polishing solution disclosed in publication No. CN111234705A for chemical mechanical polishing of silicon carbide.
Further, the substrate 1, the buffer layer 2 and the epitaxial layer 3 are all of a first conductivity type; the gate doped region 5 is of a second conductivity type, and the first conductivity type and the second conductivity type are opposite in doping type. The doping type is N-type or P-type doping; if the doping is N-type doping, the doping impurities are nitrogen (N) or phosphorus (P); if P-type doping, the doping impurity is aluminum (Al) or boron (B), which is dopedThe concentration is 1X 1014-5×1021cm-3。
Further, in step S1, the epitaxial process is performed by a chemical vapor deposition method, and the reaction temperature is 900 to 2000 ℃. In the present invention, the reaction temperature of the chemical vapor deposition is preferably 1200 ℃. The chemical vapor deposition growth method meets the requirements of crystal integrity, device structure diversification, controllable and simple device, batch production, purity guarantee and uniformity.
Further, in step S2, the dielectric film is made of photoresist, and the temperature in the deposition process of the photoresist is 20-30 ℃; photoresist is removed by a wet method and/or a dry method and the like; the adopted etching mode is a reactive ion etching technology and/or an inductive coupling plasma etching technology; the etching gas is SF6、CF4、O2And HBr.
The gluing temperature is 20-30 ℃, can be adjusted according to actual conditions, and is the same as the room temperature to the greatest extent, so that the temperature fluctuation of the photoresist can be reduced to the greatest extent, and the process fluctuation is reduced. The photoresist is preferably positive photoresist which has good contrast, so that the generated pattern has good resolution, and other characteristics such as good step coverage and good contrast; the negative adhesive has the characteristics of good adhesive capacity, barrier effect and high photosensitive speed; deformation and swelling occur at the time of development. Negative resists can easily obtain isolated single lines, while positive resists can easily obtain isolated holes or trenches, and therefore positive resists are preferred for the photoresists of the invention.
Compared with a plasma dry method, the wet method photoresist removing method has some defects, for example, photoresist removing liquid is repeatedly used for many times, the photoresist removing capability is gradually weakened, and the photoresist removing speed is changed along with time; the surface tension and material transportation of the liquid phase make the photoresist removal difficult or nonuniform; impurities accumulated in the degumming solution become a source of impurity particles. Therefore, plasma dry photoresist stripping has advantages over wet photoresist stripping, and dry plasma etching photoresist stripping is based on the principle that a plasma field excites oxygen to a high energy state, so that photoresist components are oxidized into gas which is sucked away from a reaction chamber by a vacuum pump, but the oxygen plasma cannot remove metal contamination of mobile ions, and has a certain degree of metal residue and radiation damage. Therefore, the invention preferably removes the photoresist by combining plasma dry photoresist removal and wet photoresist removal, firstly removes the photoresist layer used for hardening by using plasma, and then removes the residues which are not removed by the plasma by using a wet method.
Further, in step S3, the material used for the gate doped region 5 is the same as the material used for the substrate 1, and is a silicon carbide material, and the epitaxial process uses a chemical vapor deposition method.
Example 1
In the embodiment 1 of the present invention, a silicon carbide diode is taken as an example, and a relatively complete silicon carbide diode is prepared by processing the silicon carbide diode on the basis of the preparation method.
A method for manufacturing a silicon carbide semiconductor device includes the steps of:
and S1, performing epitaxy on the surface of the silicon carbide substrate 1 by adopting an epitaxy process to obtain a buffer layer 2 and an epitaxial layer 3 in sequence. The substrate 1, the buffer layer 2 and the epitaxial layer 3 are doped in the same type, and the doping type is N-type or P-type doping; if the doping is N-type doping, the doping impurities are nitrogen (N) or phosphorus (P); if P-type doping is adopted, the doping impurity is aluminum (Al) or boron (B) with the doping concentration of 1 × 1014-5×1021cm-3。
And S2, sequentially depositing a dielectric film and photoetching on the epitaxial layer 3 to form a patterned first mask layer, and then forming a gate trench 4 by etching. In the photoetching or etching process, the pattern of the mask plate is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 0.01-200 mu m, the etching depth is 0.01-200 mu m, and the width of the table top area is 0.01-200 mu m; wherein the length of the parallel long strip-shaped patterns and the interdigital patterns is 0.01 mu m-20 cm. The etching is a reactive ion etching technology or an inductive coupling plasma etching technology or a combination thereof; the etching gas includes but is not limited to SF6, CF4, O2, HBr and other atmosphere in any combination.
S3, carrying out epitaxial growth again on the surface of the sample epitaxial layer 3 obtained in the step S2 to form a gate doped region 5; type of gate doped region 5 andthe doping types of the substrates 1 are the same, and the doping types are N-type doping or P-type doping; if the doping is N-type doping, the doping impurities are nitrogen (N) or phosphorus (P); if P-type doping is adopted, the doping impurity is aluminum (Al) or boron (B) with the doping concentration of 1 × 1014-5×1021cm-3。
And S4, removing the redundant epitaxial film on the surface of the epitaxial layer 3 by adopting chemical mechanical polishing, and flattening the surface of the sample.
S5, forming a patterned ohmic contact region 8 on the surface of the sample through a stripping process or deposition, photoetching and etching of a dielectric film, and combining a metal film deposition process and a metal alloying process; then forming a first bonding electrode 10 on the upper surface of the sample through conductive film deposition; ohmic contacts and second bonding electrodes 11 are formed on the back surface of the substrate 1.
Example 2
In embodiment 2 of the present invention, a JFET device is taken as an example, and a relatively complete JFET transistor is fabricated by processing the JFET device on the basis of the method for fabricating the JFET device.
A method for manufacturing a silicon carbide semiconductor device includes the steps of:
and S1, performing epitaxy on the surface of the silicon carbide substrate 1 by adopting an epitaxy process to obtain a buffer layer 2 and an epitaxial layer 3 in sequence. The substrate 1, the buffer layer 2 and the epitaxial layer 3 are doped in the same type, and the doping type is N-type or P-type doping; if the doping is N-type doping, the doping impurities are nitrogen (N) or phosphorus (P); if P-type doping is adopted, the doping impurity is aluminum (Al) or boron (B) with the doping concentration of 1 × 1014-5×1021cm-3。
And S2, sequentially depositing a dielectric film and photoetching on the epitaxial layer 3 to form a patterned first mask layer, and then forming a gate trench 4 by etching. In the photoetching or etching process, the pattern of the mask plate is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 0.01-200 mu m, the etching depth is 0.01-200 mu m, and the width of the table top area is 0.01-200 mu m; wherein the length of the parallel long strip-shaped patterns and the interdigital patterns is 0.01 mu m-20 cm. The etching is a reactive ion etching technology or an inductive coupling plasma etching technology or a combination thereof; the etching gas includes but is not limited to SF6, CF4, O2, HBr and other atmosphere in any combination.
S3, carrying out epitaxial growth again on the surface of the sample epitaxial layer 3 obtained in the step S2 to form a gate doped region 5; the type of the gate doped region 5 is the same as the doping type of the substrate 1, and the doping type is N-type or P-type doping; if the doping is N-type doping, the doping impurities are nitrogen (N) or phosphorus (P); if P-type doping is adopted, the doping impurity is aluminum (Al) or boron (B) with the doping concentration of 1 × 1014-5×1021cm-3。
And S4, removing the redundant epitaxial film on the surface of the epitaxial layer 3 by adopting chemical mechanical polishing, and flattening the surface of the sample.
And S5, depositing, photoetching and etching the dielectric film again on the upper surface of the gate doped region to form a patterned second mask layer 6. The dielectric film is a single-layer film or a composite layer film of any combination formed by silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon or common metals (Ni, Al, W, Ti or any alloy compound thereof). The thickness of the second mask layer 6 is 0.01um-100 um.
S6, forming a source region doped region 7 on the upper surface of the epitaxial layer through ion implantation, wherein the ion implantation material is N, P, B or Al, the ion implantation energy is 10 kev-15 Mev, the ion implantation temperature is 22-1000 ℃, and the ion implantation dosage is 1 x 1010～5×1016cm-2。
And S7, removing the second mask layer 6, carrying out high-temperature annealing on the sample, and activating the injected impurities. The annealing atmosphere is vacuum, nitrogen or argon, the annealing temperature is 300-3000 ℃, and the annealing time is 0.1 min-1000 hours.
S8, forming a patterned ohmic contact region 8 on the surface of the sample through a stripping process or deposition, photoetching and etching of a dielectric film, and combining a metal film deposition process and a metal alloying process; and then, carrying out deposition, photoetching and etching on an isolation dielectric film 9 on the upper surface of the gate doped region 5, wherein the isolation dielectric film 9 is a single-layer or multi-layer composite film of insulated silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon, phosphosilicate glass, borosilicate glass, TEOS and the like. Finally, forming a first bonding electrode 10 on the upper surface of the sample through conductive film deposition; ohmic contacts and second bonding electrodes 11 are formed on the back surface of the substrate 1.
The ohmic contact and pressure welding electrode is made of metal or other conductive materials, specifically a single-layer film or a plurality of composite films of Ti, Ni, Al, Cu, Au, Ag, Mo, W, TiW, TiC, Fe, Cr and the like, and the thickness of the film is 0.001-100 um. The ohmic contact may be achieved by a high temperature process including Rapid Thermal Annealing (RTA) or Laser Annealing (LA) or other high temperature furnace, wherein the atmosphere in the process is a vacuum atmosphere or an inert gas atmosphere such as nitrogen, argon, or the like.
The depth-to-width ratio of the silicon carbide groove etched by the preparation method can reach more than 5:1, and the width and the space of the groove can reach 1 mu m and below. When the super junction structure is prepared by adopting the scheme of groove etching and inclined angle injection, ideal side wall doping cannot be realized at a high depth-to-width ratio, and the problem can be effectively solved by the method.
Comparing the silicon carbide semiconductor device prepared by the method with the common planar and groove type SiC MOSFET, wherein the minimum cell size of the common planar SiC MOSFET is 5 mu m; the minimum cell size of a common groove type SiC MOSFET is 3.4 mu m; the minimum cell size of the SiC JFET device processed by the method is 2 mu m. The comparison graphs of the three structures are shown in fig. 8-10, the simulation results are shown in fig. 11-12, and according to the simulation results, the withstand voltage of the structure obtained by the method of the invention can be equivalent to that of a common planar SiC MOSFET, and the resistance of the SiC device prepared by the method of the invention per unit area is minimum. Based on the results, the device processed by the method has better reliability and stronger practicability. The above embodiments are only some of the embodiments of the present invention, and the method of the present invention may be used for processing other types of silicon carbide semiconductor devices.
The above-mentioned embodiments are further described in detail for the purpose of illustrating the invention, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the invention and are not intended to limit the invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit of the invention should be included in the scope of the invention.

Claims (8)

1. A method for manufacturing a silicon carbide semiconductor device, comprising the steps of:
s1, performing epitaxy on the surface of the silicon carbide substrate (1) by adopting an epitaxy process to obtain a buffer layer (2) and an epitaxial layer (3) in sequence;
s2, sequentially depositing a dielectric film and photoetching on the epitaxial layer (3) to form a patterned first mask layer, and then forming a gate trench (4) by etching;
s3, carrying out epitaxial growth again on the surface of the sample epitaxial layer (3) obtained in the step S2 to form a gate doped region (5);
and S4, removing the redundant epitaxial film on the surface of the epitaxial layer (3) by adopting chemical mechanical polishing, and flattening the surface of the sample.
2. A method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the substrate (1), the buffer layer (2) and the epitaxial layer (3) are all of a first conductivity type; the gate doped region (5) is of a second conductivity type, and the first conductivity type and the second conductivity type are of opposite doping types.
3. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein in step S1, the epitaxial process is performed by chemical vapor deposition, and the reaction temperature is 900 to 2000 ℃.
4. The method for manufacturing the silicon carbide semiconductor device according to claim 1 or 2, wherein in step S2, the dielectric film is made of photoresist, and the temperature during the deposition of the photoresist is 20-30 ℃; photoresist is removed by a wet method and/or a dry method and the like; the adopted etching mode is a reactive ion etching technology and/or an inductive coupling plasma etching technology; the etching gas is one or more of SF6, CF4, O2 and HBr.
5. The method of manufacturing a silicon carbide semiconductor device according to claim 3,
in step S2, the dielectric film is made of photoresist, and the temperature in the deposition process of the photoresist is 20-30 ℃; photoresist is removed by a wet method and/or a dry method and the like; the adopted etching mode is a reactive ion etching technology and/or an inductive coupling plasma etching technology; the etching gas is one or more of SF6, CF4, O2 and HBr.
6. The method of manufacturing a silicon carbide semiconductor device according to claim 1, 2 or 5, wherein in step S3, the gate doped region (5) is made of the same material as the substrate (1), and is made of silicon carbide material, and the epitaxial process is chemical vapor deposition.
7. The method of claim 3, wherein in step S3, the gate doped region (5) is made of the same material as the substrate (1) and is made of silicon carbide material, and the epitaxial process is chemical vapor deposition.
8. The method of claim 4, wherein in step S3, the gate doped region (5) is made of the same material as the substrate (1) and is made of silicon carbide material, and the epitaxial process is chemical vapor deposition.
CN202110908129.2A 2021-08-09 2021-08-09 Manufacturing method of silicon carbide semiconductor device Pending CN113643970A (en)

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CN114188213A (en) * 2021-12-06 2022-03-15 上海稷以科技有限公司 Method for solving problem of transmission failure of silicon carbide wafer

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Publication number Priority date Publication date Assignee Title
CN114188213A (en) * 2021-12-06 2022-03-15 上海稷以科技有限公司 Method for solving problem of transmission failure of silicon carbide wafer
CN114188213B (en) * 2021-12-06 2023-04-07 上海稷以科技有限公司 Method for solving problem of transmission failure of silicon carbide wafer

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